Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 11 - 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites that the DQ arrangement unit “arranges the DQ signals by expanding a width of the DQ signal to correspond to a ratio of the frequency of the clock provided from the high-speed memory and a frequency of the digital physical layer and a data rate of the high-speed memory.”
The phrase “expanding a width of the DQ signal” is unclear because the claim does not specify what “width” refers to (e.g., bit-width, bus-width, number of lanes, or temporal width). Additionally, the phrase “to correspond to a ratio of the frequency … and a data rate” introduces a mathematical relationship that is not defined with reasonable certainty. The claim does not specify how the ratio is calculated, how the data rate is incorporated, or how these values determine the resulting “width.”
Although the specification describes rearranging or aligning DQ signals based on frequency differences between clock domains, the specification does not provide a clear definition, formula, or algorithm that explains how the claimed “width” is expanded as a function of the recited ratio and data rate. As a result, one of ordinary skill in the art would not be able to determine the scope of the claimed relationship with reasonable certainty.
Claim 11 recites “arranging the DQ signals to correspond to a ratio of a frequency of a high-speed memory clock and a frequency of a digital physical layer and a data rate of the high-speed memory.”
Similar to claim 2, the phrase “to correspond to a ratio … and a data rate” introduces an undefined mathematical relationship. The claim does not specify what parameter of the DQ signals is being adjusted to correspond to the ratio (e.g., width, timing, grouping), nor does it define how the ratio and data rate are used to determine the resulting arrangement.
While the specification generally describes rearranging DQ signals when converting between clock domains, it does not provide sufficient detail to define the claimed relationship between the frequency ratio, data rate, and the resulting arrangement of DQ signals. Accordingly, the scope of this limitation is ambiguous.
Claim 12 recites that “the arranging of the DQ signals is performed by expanding a width of the DQ signal to correspond to a product of the frequency ratio and the data rate.”
The phrase “product of the frequency ratio and the data rate” introduces a mathematical expression that is not defined with sufficient clarity. The claim does not specify the units, scaling, or implementation of this product, nor does it explain how the product determines the resulting “width” of the DQ signal.
Although the specification discusses rearranging DQ signals and converting between clock domains, it does not provide a clear description of how a product of a frequency ratio and a data rate is used to determine signal width or arrangement. The absence of such detail renders the scope of the claim unclear.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Butt et al. (US Pat. No. 7215584), hereinafter referred to as Butt in view of Lee et al. (US Pat. No. 7975164), hereinafter referred to as Lee.
As to claim 1, Butt discloses a physical layer (PHY) between a high-speed memory (DDR SDRAM 106, Fig. 1) and a memory controller (DDR PHY 104 disposed between memory controller 102 and DDR SDRAM 106, Fig. 1), the physical layer comprising: an analog physical layer (physical read data paths 114 implementing delay and sampling circuitry at the DDR PHY front-end, Fig. 2, Fig. 3A) including a read data strobe (RDQS) delay unit (slave delay adjustment blocks 124a/128a configured to delay the DQS signal and output PDQS OUT/NDQS OUT, Fig. 3A) that delays an RDQS signal of the high-speed memory and outputs the RDQS signal (slave delay adjustment blocks 124a/128a configured to delay DQS and output PDQS OUT/NDQS OUT, Fig. 3A) and an asynchronous first-in first-out (FIFO) that samples the DQ signal with the RDQS signal and outputs the DQ signal in synchronization with a digital physical layer clock (ASYNC FIFOs 112 receive DQ data sampled by delayed DQS and transfer data from DQS domain to CLK 1X domain, Fig. 2), and a validity signal forming unit that forms a validity signal indicating validity of data output from the asynchronous FIFO (gating/control logic generating RD GATE and GATEON signals to ensure valid read data and prevent invalid states, Fig. 2, Fig. 4), wherein the analog physical layer receives a clock having the same frequency as the high-speed memory and operates (DQS-based sampling in data paths 114 aligned with memory timing, Fig. 2), and the asynchronous FIFO and the validity signal forming unit receive a clock having a lower frequency than the clock provided to the high-speed memory and operate (FIFOs transfer data from DQS domain to lower-frequency CLK 1X domain for the controller, Fig. 2).
Lee discloses, what Butt lacks, a data (DQ) delay unit that delays DQ signals (programmable delay elements 304 applied to each DQ data bit 303 to introduce delay, Fig. 3) and outputs the delayed DQ signals (delayed DQ signals provided to subsequent capture registers after passing through delay elements, Fig. 4A), and a digital physical layer (core domain logic including capture registers and processing stages following the PHY, Fig. 5) including a DQ arrangement unit that arranges the DQ signals (levelization FIFO and register stages 209–212 aligning and organizing DQ bits across byte lanes for proper data formation, Fig. 2).
Butt and Lee are analogous art because they are from the same field of endeavor, namely DDR memory interface physical layer (PHY) design and timing alignment for high-speed memory systems.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Butt and Lee before him or her, to modify the physical layer data path of Butt to include the data (DQ) delay elements and data arrangement (alignment/levelization) logic of Lee.
The suggestion/motivation for doing so would have been to improve timing alignment between DQ and DQS signals and across multiple data lanes in order to compensate for system-level timing variations such as skew, propagation delay, and clock misalignment, as Lee teaches that individual programmable delay elements are applied to each DQ bit to handle timing irregularities and align data (see Fig. 3 showing delay elements on each data bit), and further teaches that alignment logic (e.g., levelization FIFO/register stages) is used to organize and align data across byte lanes (see Fig. 2 showing register stages aligning data), thereby improving reliability and yield in DDR memory interfaces.
Therefore, it would have been obvious to combine Lee with Butt to obtain the invention as specified in the instant claim.
As to claim 2, Lee discloses the physical layer of claim 1, wherein the DQ arrangement unit arranges the DQ signals by expanding a width of the DQ signal (plural DQ bits 303 combined into parallel byte-lane data paths forming widened data words, Fig. 3) to correspond to a ratio of the frequency of the clock provided from the high-speed memory (DQS strobe clock domain associated with incoming DDR data, Fig. 2) and a frequency of the digital physical layer (core clock domain receiving aligned data through register stages, Fig. 2) and a data rate of the high-speed memory (double data rate transfer of DQ bits per DQS edge, Fig. 2) (plural DQ bits 303 forming byte lanes are processed in parallel and passed through levelization FIFO/register stages 209–212 to align and reorganize the data into a wider parallel format for transfer from the DQS domain to the core clock domain operating at a different frequency, Fig. 2, Fig. 3).
As to claim 3, Lee discloses the physical layer of claim 1, wherein the RDQS delay unit is a buffer line (programmable delay element 302 receiving the DQS signal, Fig. 3) having a controllable delay (delay tap values applied to adjust timing of the DQS signal relative to data, Fig. 4A), and the DQ delay unit is the buffer line having the controllable delay (programmable delay elements 302 applied to DQS and programmable delay elements 304 applied to each DQ bit, each implemented as controllable delay lines to adjust timing alignment, Fig. 3, Fig. 4A).
As to claim 4, Lee discloses the physical layer of claim 1, wherein the DQ signals include a first DQ signal (data bit dq0 201, Fig. 2) and a second DQ signal (data bit dq1 within byte lane 303, Fig. 3), and the digital physical layer further includes a DQ signal arrangement unit (levelization FIFO/register stages 209–212 aligning multiple DQ bits, Fig. 2), and the DQ signal arrangement unit arranges the DQ signals (aligning and synchronizing delayed DQ bits across byte lanes through capture registers 207, 208 and subsequent stages, Fig. 2) and outputs the arranged DQ signals to correspond to a ratio of the frequency of the clock provided from the high-speed memory (DQS-based sampling clock domain, Fig. 2) and a frequency of the digital physical layer and a data rate of the high-speed memory (multiple DQ bits such as dq0 201 and dq1 within byte lanes are independently delayed and then aligned through capture registers 207, 208 and subsequent register stages 209–212 to synchronize and organize the signals for output into the core domain clock, Fig. 2).
As to claim 5, Lee discloses the physical layer of claim 4, wherein the DQ signal arrangement unit expands the width of the DQ signal to correspond to a product of the frequency ratio (difference between DQS domain frequency and core clock domain frequency requiring parallelization of data bits, Fig. 2) and the data rate and provides the DQ signal to the asynchronous FIFO (parallel DQ data bits 303 across a byte lane are combined and aligned into a wider data path after passing through delay and alignment stages, thereby effectively expanding the width prior to transfer into downstream synchronization circuitry, Fig. 2, Fig. 3).
As to claim 6, Butt discloses the physical layer of claim 1, wherein the asynchronous FIFO outputs a sampled signal (DQ data sampled using delayed DQS and written into FIFO via PDQS OUT and NDQS OUT signals, Fig. 2) by synchronizing the rearranged DQ signals with a digital physical layer clock (asynchronous FIFOs 112 receive DQ data sampled by delayed DQS via signals DR_PDQ_OUT and DR_NDQ_OUT and transfer the data from the DQS domain to the CLK 1X domain for output to the memory controller, Fig. 2).
As to claim 7, Butt discloses the physical layer of claim 1, wherein the memory controller generates an enable signal (control signal RD GATE generated in response to MC_CMD read command, Fig. 2) in the memory controller to check whether the signal output from the asynchronous FIFO corresponds to a training sequence stored (the delay settings may be stored in a register, col. 12, lines 1 - 3) in the memory controller, and the validity signal forming unit delays a starting edge of the enable signal to correspond to a starting edge of the signal output from the asynchronous FIFO to generate the validity signal (control logic 117 generating RD GATE in response to memory controller command signals MC_CMD and gating circuit 118 generating GATEON to align valid read windows and prevent invalid data from propagating into synchronization logic, Fig. 2, Fig. 4).
As to claim 8, Butt discloses the physical layer of claim 7, wherein the validity signal forming unit controls an edge of the validity signal (timing edges of GATEON controlled via programmable delay stages and flip-flop chains to align with valid DQS/DQ transitions, Fig. 4, Fig. 5) to correspond to edges of the signals output from the asynchronous FIFO (gating circuit 118 generating GATEON with programmable delay stages 130, 131, 132 to align the enable timing edges with the valid DQS/DQ signal timing windows, Fig. 4, Fig. 5).
As to claim 9, Butt discloses the physical layer of claim 7, wherein the validity signal forming unit is a register chain connected in cascade (multiple flip-flops 150a–150n and 160a–160f arranged in series to delay and shape the GATEON signal, forming a cascaded register/delay chain, Fig. 5).
As to claim 10, modified system of Butt does not disclose the physical layer of claim 1, wherein the high-speed memory is a high bandwidth memory 3 (HBM3) memory.
However, the selection of HBM3 memory constitutes the use of a known type of high-speed memory device. HBM3 memory is a well-known and standardized memory technology in the art, and represents a predictable variation of high-speed memory architectures used in conjunction with memory controllers and PHY interfaces.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an HBM3 memory in the system of Butt, as modified by Lee, because doing so amounts to substituting one known high-speed memory type for another to achieve the same purpose of high-speed data storage and transfer.
Such substitution would have been a matter of design choice since the claimed physical layer operates to align and transfer data between a memory and a memory controller, and these functions are generally applicable to different types of high-speed memories, including HBM3. The use of HBM3 would have yielded predictable results, namely enabling high-bandwidth data transfer using known PHY techniques.
Therefore, it would have been obvious to combine Butt and Lee and to utilize an HBM3 memory to obtain the invention as specified in claim 10.
Claims 11 - 19 recite the corresponding limitation of claims 1 - 10. Therefore, they are rejected accordingly.
As to claim 20, Butt discloses the read training method of claim 11, wherein a preamble is added to a head of the RDQS signal (DQS strobe signal includes a leading portion prior to valid data used for synchronization and gating of read operations via RD GATE signal generation and alignment circuitry, Fig. 2) and a postamble is added to an end of the RDQS signal (DQS strobe includes a trailing portion following valid data during which gating logic 118 and delayed control signals terminate valid data capture to prevent invalid sampling, Fig. 4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sankaran et al. (US Pub. No. 20190347125) a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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