Prosecution Insights
Last updated: October 01, 2026
Application No. 18/985,655

A METHOD AND CIRCUIT ARRANGEMENT FOR VOLTAGE PROTECTION

Non-Final OA §102§103§112
Filed
Dec 18, 2024
Examiner
SREEVATSA, SREEYA
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Analog Devices Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
254 granted / 295 resolved
+18.1% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
315
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
34.3%
-5.7% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 295 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending in this application. Information Disclosure Statement The information disclosure statement (IDS) were submitted on 12/18/2024, 04/24/2026 and 06/30/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to because Fig. 2, part “22” should be labeled –25—per specification paragraph [0059]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claim 17 is objected to because of the following informalities: Claim 17 line 2, “a controllable switch a first channel terminal” should be -- a controllable switch, a first channel terminal--. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 12 lines 3-4 recites “wherein the first current mirror component is positioned between the output of the first buffer and the resistive component”. From fig.3 and specification paragraph, it appears that the first current mirror 78 is positioned between output of second buffer 74 and the resistive component 76. For the purposes of examination, the above limitation is interpreted as --wherein the first current mirror component is positioned between the output of the second buffer and the resistive component--. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 and 16-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Takimoto (US 20230013041 A1). Regarding claim 1, Takimoto teaches a solid state switch device (e.g. gate drive circuit and switching device, fig.2), comprising: a controllable switch (i.e. switching device 1, fig.2) comprising a control terminal (e.g. gate of 1, fig.2), a first channel terminal (e.g. drain of 1, fig.2), and a second channel terminal (e.g. source of 1, fig.2), the control terminal operable to control switching of the controllable switch between an off-state and an on-state ([0031], controlled to operate by a control signal supplied from the drive circuit 200), wherein in the on-state the switch allows a current to flow between the first channel terminal and the second channel terminal ([0035], The switching device 1 is switched by a gate voltage applied to the gate terminal between a state in which electrical connection is made between the source terminal and the drain terminal (“on” state) and a state of being cut off (“off” state)); and an overvoltage protection circuit (e.g. circuit comprising voltage detector 7, fig.2) configured to: determine a voltage difference between a first voltage of the first channel terminal and a second voltage of the second channel terminal ([0039], The voltage detector 7 detects a value of a drain-source voltage (inter-terminal voltage) Vds of the switching device 1); and set a control signal to a protection value to operate the controllable switch in the off-state in response to determining that the voltage difference is greater than or equal to a switch threshold ([0042], The off-mode fast drive circuit 5 is configured to stop operation of applying the control signal to the gate terminal when the value of the delayed drain-source voltage Vds is equal to or above a predetermined threshold value). Regarding claim 2, Takimoto teaches the solid state switch device of claim 1, wherein the solid state switch device is configured to use the control signal to, when the voltage difference is greater than or equal to a switch threshold: control the controllable switch to switch to the off-state from the on-state of the controllable switch ([0042], The off-mode fast drive circuit 5 is configured to stop operation of applying the control signal to the gate terminal when the value of the delayed drain-source voltage Vds is equal to or above a predetermined threshold value). Regarding claim 3, Takimoto teaches the solid state switch device of claim 1, wherein the overvoltage protection circuit is configured to: receive an instruction signal for controlling the state of the controllable switch to either an off-state or an on-state (e.g. signal input to On-mode drive circuit 4 and off-mode slow drive circuit 6, fig.2); and, in response to determining that the voltage difference is less than the switch threshold, set the control signal to a pass value, such that when the control signal is a pass value the instruction signal controls the state of the controllable switch ([0146], causes the off-mode slow drive circuit 6 to forcedly cut off the switching device 1) (it is necessarily true that when Vds is normal, input to on-mode drive circuit 4 will pass through). Regarding claim 16, Takimoto teaches the solid state switch device of claim 1, wherein the difference signal is a voltage signal ([0039], The voltage detector 7 detects a value of a drain-source voltage (inter-terminal voltage) Vds of the switching device 1). Regarding claim 17, it is rejected for the same reasons as stated above for claim 1. Regarding claim 18, the method is rejected for the same reasons as stated above for claim 1. Regarding claim 19, the method is rejected for the same reasons as stated above for claim 2. Regarding claim 20, the method is rejected for the same reasons as stated above for claim 3. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Takimoto (US 20230013041 A1), and further in view of McDaniel (US 6400189 B2). Regarding claim 4, Takimoto teaches the solid state switch device of claim 1. Takimoto does not teach, wherein the overvoltage protection circuit comprises: a first buffer comprising an input and an output, wherein the input is electrically coupled to the first channel terminal; and a second buffer comprising an input and an output, wherein the input of the second buffer is electrically coupled to the second channel terminal. McDaniel teaches in a similar field of endeavor of signals being sensed, a buffer (abstract, A buffer circuit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included wherein the overvoltage protection circuit comprises: a first buffer comprising an input and an output, wherein the input is electrically coupled to the first channel terminal; and a second buffer comprising an input and an output, wherein the input of the second buffer is electrically coupled to the second channel terminal in Takimoto, as taught by McDaniel, as it provides the advantage of signal compatibility and prevents electrically loading the controllable switch. Regarding claim 5, Takimoto and McDaniel teach the solid state switch device of claim 4, wherein the overvoltage protection circuit is arranged to generate a difference signal based on the output of the first buffer and the output of the second buffer (Takimoto, [0039], The voltage detector 7 detects a value of a drain-source voltage (inter-terminal voltage) Vds of the switching device 1), wherein the voltage difference is compared to the switch threshold by comparing the difference signal to a comparison threshold, wherein the comparison threshold has a predetermined relationship to the switch threshold (Takimoto, [0042], The off-mode fast drive circuit 5 is configured to stop operation of applying the control signal to the gate terminal when the value of the delayed drain-source voltage Vds is equal to or above a predetermined threshold value). Regarding claim 6, Takimoto and McDaniel teach the solid state switch device of claim 5. Takimoto and McDaniel do not teach, wherein the difference signal is a current signal. It would have been an obvious matter of design choice to have the difference signal is a current signal, since the applicant has not disclosed that the difference signal is a current signal solves any problem or is for a particular reason. It appears that the claimed invention would perform equally well with the difference signal is a current signal. Regarding claim 7, Takimoto and McDaniel teach the solid state switch device of claim 5, wherein the difference signal is proportional to the voltage difference between the first channel terminal and the second channel terminal (Takimoto, [0039], The voltage detector 7 detects a value of a drain-source voltage (inter-terminal voltage) Vds of the switching device 1). Regarding claim 8, Takimoto and McDaniel teach the solid state switch device of claim 5, wherein the overvoltage protection circuit further comprises a resistive component, wherein the output of the first buffer is coupled to a first terminal of the resistive component and, wherein the output of the second buffer is coupled to a second terminal of the resistive component (Takimoto, i.e. resistor 12, fig.2). Regarding claim 9, Takimoto and McDaniel teach the solid state switch device of claim 8, wherein the resistive component is a resistor, wherein an output voltage of the first buffer is proportional to an input voltage of the first buffer, and wherein an output voltage of the second buffer is proportional to an input voltage of the second buffer (McDaniel, Background, while passing a signal between the circuits). Allowable Subject Matter Claims 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 10, Takimoto (US 20230013041 A1) and McDaniel (US 6400189 B2) teach the solid state switch device of claim 5. Takimoto and McDaniel do not teach, wherein the overvoltage protection circuit comprises: a first current mirror arrangement configured to generate the difference signal based on a current flow between the output of the first buffer and the output of the second buffer. Prior art Huber (US 4595966 A), Choi (US 20190214973 A1) and Ohshima (US 20070064368 A1) have been found to be the closest prior art. However, none of the prior art, taken singly or in combination, teach “wherein the overvoltage protection circuit comprises: a first current mirror arrangement configured to generate the difference signal based on a current flow between the output of the first buffer and the output of the second buffer.” Claims 11-15 are indicated as allowable, as they depend on allowable claim 10. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 07/08/2026
Read full office action

Prosecution Timeline

Dec 18, 2024
Application Filed
Jul 09, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
90%
With Interview (+3.8%)
2y 6m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 295 resolved cases by this examiner. Grant probability derived from career allowance rate.

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