DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and are under examination
This office action is FINAL.
Response to Arguments
Applicant’s arguments with respect to claim(s) [ 1-20 ] have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Jeddeloh (US Pub No. 20130254627), hereinafter "Jeddeloh", in view of Sharon et al. (US Pub No. 20140245098), hereinafter "Sharon" ].
As per claim 1, Jeddeloh significantly teaches a memory device , comprising: one or more components configured to (memory devices, methods, and systems [Jeddeloh PP 0002]): associate a first memory stripe with a second memory stripe (a portion of the first stripe 444 - 1 can be updated by writing updated data in a portion of second stripe 444 - 2 [Jeddeloh PP 0051]), wherein the first memory stripe is associated with a first set of data storage elements and a first set of error correction elements (write data can be written in the first stripe 444 - 1 across channels 442 - 1 , . . . , 442 -(N−1). Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047]), and wherein the second memory stripe is associated with a second set of data storage elements and a second set of error correction elements (Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047], writing updated data in a portion of second stripe 444 - 2 that is written across the storage volume 440 . [Jeddeloh PP 0051] – By implication, the second stripe, being written across the same storage volume, also includes parity data on a corresponding channel);
Jeddeloh does not explicitly teach “receive a first codeword associated with the first memory stripe, wherein the first codeword includes a first set of data bits associated with data stored at the first set of data storage elements and a first set of error correction bits associated with parity information stored at the first set of error correction elements; identify a first error in the first set of data bits using the first codeword; correct the first error using the first codeword; receive a second codeword spanning the first memory stripe and the second memory stripe, wherein the second codeword includes a second set of data bits associated with the data stored at the first set of data storage elements, data stored at the second set of data storage elements, the data stored at the at least one error correction element comprising data associated with the first error, and data stored at at least one error correction element, of the first set of error correction elements, and wherein the second codeword includes a second set of error correction bits associated with parity information stored at the second set of error correction elements; identify a second error in the second set of data bits; and correct the second error using the second codeword.”
However, Sharon, in an analogous art, teaches receive a first codeword associated with the first memory stripe (a first codeword (CW1) 160 that has a first set of data bits and a first set of parity bits [Sharon PP 0017]), wherein the first codeword includes a first set of data bits associated with data stored at the first set of data storage elements and a first set of error correction bits associated with parity information stored at the first set of error correction elements (a first codeword (CW1) 160 that has a first set of data bits and a first set of parity bits [Sharon PP 0017]);
identify a first error in the first set of data bits using the first codeword (the decoder 118 may perform a decoding operation according to the first ECC scheme 124 to correct bit errors in the representation 146 [Sharon PP 0024]);
correct the first error using the first codeword (the decoder 118 may perform a decoding operation according to the first ECC scheme 124 to correct bit errors in the representation 146 to recover the requested data. [Sharon PP 0024]);
receive a second codeword spanning the first memory stripe and the second memory stripe (transforms the plurality of individual, shorter codewords (e.g., codewords 160 , 162 , and 164 ) into one longer codeword that may span over multiple (or all) logical pages of a single word line. [Sharon PP 0035]), wherein the second codeword includes a second set of data bits associated with the data stored at the first set of data storage elements, data stored at the second set of data storage elements, the data stored at the at least one error correction element comprising data associated with the first error, and data stored at at least one error correction element, of the first set of error correction elements (a bit-wise logical operation, such as an XOR operation, may be applied to data bits (and to parity bits corresponding to the first ECC scheme 124 ) of the codewords 160 - 164 within the data latches 150 to generate the combined parity bits 144 . [Sharon PP 0023] Enlarged codeword incorporates the parity content of CW1 as data), and wherein the second codeword includes a second set of error correction bits associated with parity information stored at the second set of error correction elements (generate combined parity bits 144 of the combined codeword [Sharon PP 0018]);
identify a second error in the second set of data bits (the decoder 118 may initiate a decoding operation using the combined codeword [Sharon PP 0025]); and
correct the second error using the second codeword (The error-corrected versions of the representation 148 of the second codeword 162 and the representation 150 of the third codeword 164 may be used, with the combined parity bits 144 , by the decoder 118 to decode the first codeword 160 [Sharon PP 0025]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 2, Jeddeloh significantly teaches wherein the first RS payload is larger than the second RS payload (write data can be written in the first stripe 444 - 1 across channels 442 - 1 , . . . , 442 -(N−1). Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047]).
Jeddeloh does not explicitly teach “wherein the first codeword is a first Reed-Solomon (RS) codeword associated with a first RS payload, wherein the second codeword is associated with a second RS codeword associated with a second RS payload”
However, Sharon, in an analogous art, teaches wherein the first codeword is a first Reed-Solomon (RS) codeword associated with a first RS payload (such as a Reed Solomon encoder [Sharon PP 0015]), wherein the second codeword is associated with a second RS codeword associated with a second RS payload (generate a combined codeword on the memory die 103 by encoding the group of codewords 140 according to the second error correction encoding scheme 126 [Sharon PP 0018])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 3, Jeddeloh significantly teaches wherein the one or more components are further configured to replace parity information stored at a first error correction element, of the first set of error correction elements, with a first set of data associated with the first error (a portion of the first stripe 444 - 1 can be updated by writing updated data in a portion of second stripe 444 - 2 [Jeddeloh PP 0051]).
As per claim 4, Jeddeloh significantly teaches wherein the one or more components are further configured to replace parity information stored at a second error correction element, of the first set of error correction elements, with a second set of data associated with the second error (the memory system can update an LBA table … to indicate that the portion of the first stripe 444 - 1 associated with the data that was updated is now invalid [Jeddeloh PP 0051]).
As per claim 5, Jeddeloh significantly teaches wherein the one or more components are further configured to determine the parity information stored at the second set of error correction elements based on replacing the parity information stored at the first error correction element with the first set of data (parity data can allow data associated with an effectively removed portion of a memory stripe to be recreated [Jeddeloh PP 0047]).
As per claim 6, Jeddeloh does not explicitly teach “wherein the one or more components are further configured to: receive a third codeword associated with the first memory stripe and the second memory stripe, wherein the third codeword includes a third set of data bits associated with the data stored at the first set of data storage elements, the data stored at the second set of data storage elements, and data stored at the first set of error correction elements, and wherein the third codeword includes a third set of error correction bits associated with parity information stored at the second set of error correction elements; identify a third error in the third set of data bits; and correct the third error using the third codeword.”
However, Sharon, in an analogous art, teaches wherein the one or more components are further configured to: receive a third codeword associated with the first memory stripe and the second memory stripe (generate a combined codeword on the memory die 103 [Sharon PP 0018]), wherein the third codeword includes a third set of data bits associated with the data stored at the first set of data storage elements, the data stored at the second set of data storage elements, and data stored at the first set of error correction elements (transforms the plurality of individual, shorter codewords (e.g., codewords 160 , 162 , and 164 ) into one longer codeword that may span over multiple (or all) logical pages of a single word line. [Sharon PP 0035]), and wherein the third codeword includes a third set of error correction bits associated with parity information stored at the second set of error correction elements (generate combined parity bits 144 of the combined codeword [Sharon PP 0018]);
identify a third error in the third set of data bits ( the decoder 118 may initiate a decoding operation using the combined codeword [Sharon PP 0025]); and
correct the third error using the third codeword (The error-corrected versions of the representation 148 of the second codeword 162 and the representation 150 of the third codeword 164 may be used, with the combined parity bits 144 , by the decoder 118 to decode the first codeword 160 [Sharon PP 0025]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 7, Jeddeloh significantly teaches wherein the one or more components are further configured to store, in a dynamic storage component, an indication of an association between the first memory stripe and the second memory stripe (the one or more volatile memory devices can store an LBA table 234 and/or a block table 236. [Jeddeloh PP 0037]).
As per claim 8, Jeddeloh significantly teaches a method, comprising: associating, by a memory device, a first memory stripe with a second memory stripe (a portion of the first stripe 444 - 1 can be updated by writing updated data in a portion of second stripe 444 - 2 [Jeddeloh PP 0051]), wherein the first memory stripe is associated with a first set of data storage elements and a first set of error correction elements (write data can be written in the first stripe 444 - 1 across channels 442 - 1 , . . . , 442 -(N−1). Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047]), and wherein the second memory stripe is associated with a second set of data storage elements and a second set of error correction elements (write data and parity data can be striped across the storage volume 440 [Jeddeloh PP 0044]);
Jeddeloh does not explicitly teach “receiving, by the memory device, a first codeword associated with the first memory stripe, wherein the first codeword includes a first set of data bits associated with data stored at the first set of data storage elements and a first set of error correction bits associated with parity information stored at the first set of error correction elements; identifying, by the memory device, a first error in the first set of data bits using the first codeword; correcting, by the memory device, the first error using the first codeword; receiving, by the memory device, a second codeword spanning the first memory stripe and the second memory stripe, wherein the second codeword includes a second set of data bits associated with the data stored at the first set of data storage elements, data stored at the second set of data storage elements, the data stored at the at least one error correction element comprising data associated with the first error, and data stored at at least one error correction element, of the first set of error correction elements, and wherein the second codeword includes a second set of error correction bits associated with parity information stored at the second set of error correction elements; identifying, by the memory device, a second error in the second set of data bits; and correcting, by the memory device, the second error using the second codeword.”
However, Sharon, in an analogous art, teaches receiving, by the memory device, a first codeword associated with the first memory stripe (a first codeword (CW1) 160 that has a first set of data bits and a first set of parity bits [Sharon PP 0017]), wherein the first codeword includes a first set of data bits associated with data stored at the first set of data storage elements and a first set of error correction bits associated with parity information stored at the first set of error correction elements (a first codeword (CW1) 160 that has a first set of data bits and a first set of parity bits [Sharon PP 0017]);
identifying, by the memory device, a first error in the first set of data bits using the first codeword (the decoder 118 may perform a decoding operation according to the first ECC scheme 124 to correct bit errors in the representation 146 [Sharon PP 0024]);
correcting, by the memory device, the first error using the first codeword (the decoder 118 may perform a decoding operation according to the first ECC scheme 124 to correct bit errors in the representation 146 to recover the requested data. [Sharon PP 0024]);
receiving, by the memory device, a second codeword spanning the first memory stripe and the second memory stripe (transforms the plurality of individual, shorter codewords (e.g., codewords 160 , 162 , and 164 ) into one longer codeword that may span over multiple (or all) logical pages of a single word line. [Sharon PP 0035]), wherein the second codeword includes a second set of data bits associated with the data stored at the first set of data storage elements, data stored at the second set of data storage elements, the data stored at the at least one error correction element comprising data associated with the first error, and data stored at at least one error correction element, of the first set of error correction elements (a bit-wise logical operation, such as an XOR operation, may be applied to data bits (and to parity bits corresponding to the first ECC scheme 124 ) of the codewords 160 - 164 within the data latches 150 to generate the combined parity bits 144 . [Sharon PP 0023] Enlarged codeword incorporates the parity content of CW1 as data), and wherein the second codeword includes a second set of error correction bits associated with parity information stored at the second set of error correction elements (generate combined parity bits 144 of the combined codeword [Sharon PP 0018]);
identifying, by the memory device, a second error in the second set of data bits (the decoder 118 may initiate a decoding operation using the combined codeword [Sharon PP 0025]); and
correcting, by the memory device, the second error using the second codeword (The error-corrected versions of the representation 148 of the second codeword 162 and the representation 150 of the third codeword 164 may be used, with the combined parity bits 144 , by the decoder 118 to decode the first codeword 160 [Sharon PP 0025]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 9, Jeddeloh significantly teaches wherein the first RS payload is larger than the second RS payload (write data can be written in the first stripe 444 - 1 across channels 442 - 1 , . . . , 442 -(N−1). Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047]).
Jeddeloh does not explicitly teach “wherein the first codeword is a first Reed-Solomon (RS) codeword associated with a first RS payload, wherein the second codeword is associated with a second RS codeword associated with a second RS payload”
However, Sharon, in an analogous art, teaches wherein the first codeword is a first Reed-Solomon (RS) codeword associated with a first RS payload (such as a Reed Solomon encoder [Sharon PP 0015]), wherein the second codeword is associated with a second RS codeword associated with a second RS payload (generate a combined codeword on the memory die 103 by encoding the group of codewords 140 according to the second error correction encoding scheme 126 [Sharon PP 0018])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 10, Jeddeloh significantly teaches further comprising replacing, by the memory device, parity information stored at a first error correction element, of the first set of error correction elements, with a first set of data associated with the first error (a portion of the first stripe 444 - 1 can be updated by writing updated data in a portion of second stripe 444 - 2 [Jeddeloh PP 0051]).
As per claim 11, Jeddeloh significantly teaches further comprising replacing, by the memory device, parity information stored at a second error correction element, of the first set of error correction elements, with a second set of data associated with the second error (the memory system can update an LBA table … to indicate that the portion of the first stripe 444 - 1 associated with the data that was updated is now invalid [Jeddeloh PP 0051]).
As per claim 12, Jeddeloh significantly teaches further comprising determining, by the memory device, the parity information stored at the second set of error correction elements based on replacing the parity information stored at the first error correction element with the first set of data (parity data can allow data associated with an effectively removed portion of a memory stripe to be recreated [Jeddeloh PP 0047]).
As per claim 13, Jeddeloh does not explicitly teach “further comprising: receiving, by the memory device, a third codeword associated with the first memory stripe and the second memory stripe, wherein the third codeword includes a third set of data bits associated with the data stored at the first set of data storage elements, the data stored at the second set of data storage elements, and data stored at the first set of error correction elements, and wherein the third codeword includes a third set of error correction bits associated with parity information stored at the second set of error correction elements; identifying, by the memory device, a third error in the third set of data bits; and correcting, by the memory device, the third error using the third codeword.”
However, Sharon, in an analogous art, teaches further comprising: receiving, by the memory device, a third codeword associated with the first memory stripe and the second memory stripe (generate a combined codeword on the memory die 103 [Sharon PP 0018]), wherein the third codeword includes a third set of data bits associated with the data stored at the first set of data storage elements, the data stored at the second set of data storage elements, and data stored at the first set of error correction elements (transforms the plurality of individual, shorter codewords (e.g., codewords 160 , 162 , and 164 ) into one longer codeword that may span over multiple (or all) logical pages of a single word line. [Sharon PP 0035]), and wherein the third codeword includes a third set of error correction bits associated with parity information stored at the second set of error correction elements (generate combined parity bits 144 of the combined codeword [Sharon PP 0018]);
identifying, by the memory device, a third error in the third set of data bits (the decoder 118 may initiate a decoding operation using the combined codeword [Sharon PP 0025]); and
correcting, by the memory device, the third error using the third codeword (The error-corrected versions of the representation 148 of the second codeword 162 and the representation 150 of the third codeword 164 may be used, with the combined parity bits 144 , by the decoder 118 to decode the first codeword 160 [Sharon PP 0025]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 14, Jeddeloh significantly teaches further comprising storing, by the memory device and in a dynamic storage component, an indication of an association between the first memory stripe and the second memory stripe (the one or more volatile memory devices can store an LBA table 234 and/or a block table 236. [Jeddeloh PP 0037]).
As per claim 15, Jeddeloh significantly teaches a memory system, comprising: a memory controller (memory system control circuitry 208. [Jeddeloh PP 0024]);
wherein the memory system is configured to: associate, by the memory controller, a first memory stripe with a second memory stripe (a portion of the first stripe 444 - 1 can be updated by writing updated data in a portion of second stripe 444 - 2 [Jeddeloh PP 0051]), wherein the first memory stripe is associated with a first set of data storage elements and a first set of error correction elements (write data can be written in the first stripe 444 - 1 across channels 442 - 1 , . . . , 442 -(N−1). Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047]), and wherein the second memory stripe is associated with a second set of data storage elements and a second set of error correction elements (Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047], writing updated data in a portion of second stripe 444 - 2 that is written across the storage volume 440 . [Jeddeloh PP 0051] – By implication, the second stripe, being written across the same storage volume, also includes parity data on a corresponding channel);
Jeddeloh does not explicitly teach “multiple encoder/decoder components associated with the memory controller; receive, by a first encoder/decoder component, of the multiple encoder/decoder components, a first codeword associated with the first memory stripe, wherein the first codeword includes a first set of data bits associated with data stored at the first set of data storage elements and a first set of error correction bits associated with parity information stored at the first set of error correction elements; identify, by the first encoder/decoder component, a first error in the first set of data bits using the first codeword; correct, by the first encoder/decoder component, the first error using the first codeword; receive, by a second encoder/decoder component, a second codeword spanning the first memory stripe and the second memory stripe, wherein the second codeword includes a second set of data bits associated with the data stored at the first set of data storage elements, data stored at the second set of data storage elements, the data stored at the at least one error correction element comprising data associated with the first error, and data stored at at least one error correction element, of the first set of error correction elements, and wherein the second codeword includes a second set of error correction bits associated with parity information stored at the second set of error correction elements; identify, by the second encoder/decoder component, a second error in the second set of data bits; and correct, by the second encoder/decoder component, the second error using the second codeword.”
However, Sharon, in an analogous art, teaches multiple encoder/decoder components associated with the memory controller (The controller 120 includes an ECC engine 122 that is configured to receive data to be stored to the memory 104 and to generate a codeword … an encoder configured to encode one or more other ECC encoding schemes, or any combination thereof. [Sharon PP 0015], The ECC engine 122 also includes a decoder 118 configured to decode data read from the memory [Sharon PP 0016])
receive, by a first encoder/decoder component, of the multiple encoder/decoder components, a first codeword associated with the first memory stripe (a first codeword (CW1) 160 that has a first set of data bits and a first set of parity bits [Sharon PP 0017]), wherein the first codeword includes a first set of data bits associated with data stored at the first set of data storage elements and a first set of error correction bits associated with parity information stored at the first set of error correction elements (a first codeword (CW1) 160 that has a first set of data bits and a first set of parity bits [Sharon PP 0017]);
identify, by the first encoder/decoder component, a first error in the first set of data bits using the first codeword (the decoder 118 may perform a decoding operation according to the first ECC scheme 124 to correct bit errors in the representation 146 [Sharon PP 0024]);
correct, by the first encoder/decoder component, the first error using the first codeword (the decoder 118 may perform a decoding operation according to the first ECC scheme 124 to correct bit errors in the representation 146 to recover the requested data. [Sharon PP 0024]);
receive, by a second encoder/decoder component, a second codeword spanning the first memory stripe and the second memory stripe (transforms the plurality of individual, shorter codewords (e.g., codewords 160 , 162 , and 164 ) into one longer codeword that may span over multiple (or all) logical pages of a single word line. [Sharon PP 0035]), wherein the second codeword includes a second set of data bits associated with the data stored at the first set of data storage elements, data stored at the second set of data storage elements, the data stored at the at least one error correction element comprising data associated with the first error, and data stored at at least one error correction element, of the first set of error correction elements (a bit-wise logical operation, such as an XOR operation, may be applied to data bits (and to parity bits corresponding to the first ECC scheme 124 ) of the codewords 160 - 164 within the data latches 150 to generate the combined parity bits 144 . [Sharon PP 0023] Enlarged codeword incorporates the parity content of CW1 as data), and wherein the second codeword includes a second set of error correction bits associated with parity information stored at the second set of error correction elements (generate combined parity bits 144 of the combined codeword [Sharon PP 0018]);
identify, by the second encoder/decoder component, a second error in the second set of data bits (the decoder 118 may initiate a decoding operation using the combined codeword [Sharon PP 0025]); and
correct, by the second encoder/decoder component, the second error using the second codeword (The error-corrected versions of the representation 148 of the second codeword 162 and the representation 150 of the third codeword 164 may be used, with the combined parity bits 144 , by the decoder 118 to decode the first codeword 160 [Sharon PP 0025]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 16, Jeddeloh significantly teaches wherein the first RS payload is larger than the second RS payload (write data can be written in the first stripe 444 - 1 across channels 442 - 1 , . . . , 442 -(N−1). Parity data can be written in the first stripe 444 - 1 across channel 442 -N. [Jeddeloh PP 0047]).
Jeddeloh does not explicitly teach “wherein the first codeword is a first Reed-Solomon (RS) codeword associated with a first RS payload, wherein the second codeword is associated with a second RS codeword associated with a second RS payload”
However, Sharon, in an analogous art, teaches wherein the first codeword is a first Reed-Solomon (RS) codeword associated with a first RS payload (such as a Reed Solomon encoder [Sharon PP 0015]), wherein the second codeword is associated with a second RS codeword associated with a second RS payload (generate a combined codeword on the memory die 103 by encoding the group of codewords 140 according to the second error correction encoding scheme 126 [Sharon PP 0018])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 17, Jeddeloh significantly teaches parity information stored at a first error correction element, of the first set of error correction elements, with a first set of data associated with the first error (a portion of the first stripe 444 - 1 can be updated by writing updated data in a portion of second stripe 444 - 2 [Jeddeloh PP 0051]).
Jeddeloh does not explicitly teach “wherein the memory system is further configured to replace, by the first encoder/decoder component”
However, Sharon, in an analogous art, teaches wherein the memory system is further configured to replace, by the first encoder/decoder component (The controller 120 includes an ECC engine 122... The ECC engine 122 also includes a decoder 118 configured to decode data read from the memory 104. [Sharon PP 0015-16])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 18, Jeddeloh significantly teaches parity information stored at a second error correction element, of the first set of error correction elements, with a second set of data associated with the second error (the memory system can update an LBA table … to indicate that the portion of the first stripe 444 - 1 associated with the data that was updated is now invalid [Jeddeloh PP 0051]).
Jeddeloh does not explicitly teach “wherein the memory system is further configured to replace, by the second encoder/decoder component”
However, Sharon, in an analogous art, teaches wherein the memory system is further configured to replace, by the second encoder/decoder component (The controller 120 includes an ECC engine 122... The ECC engine 122 also includes a decoder 118 configured to decode data read from the memory 104. [Sharon PP 0015-16])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 19, Jeddeloh significantly teaches the parity information stored at the second set of error correction elements based on replacing the parity information stored at the first error correction element with the first set of data (parity data can allow data associated with an effectively removed portion of a memory stripe to be recreated [Jeddeloh PP 0047]).
Jeddeloh does not explicitly teach “wherein the memory system is further configured to determine, by the second encoder/decoder component”
However, Sharon, in an analogous art, teaches wherein the memory system is further configured to determine, by the second encoder/decoder component (The controller 120 includes an ECC engine 122... The ECC engine 122 also includes a decoder 118 configured to decode data read from the memory 104. [Sharon PP 0015-16])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
As per claim 20, Jeddeloh does not explicitly teach “wherein the memory system is further configured to: receive, by the second encoder/decoder component, a third codeword associated with the first memory stripe and the second memory stripe, wherein the third codeword includes a third set of data bits associated with the data stored at the first set of data storage elements, the data stored at the second set of data storage elements, and data stored at the first set of error correction elements, and wherein the third codeword includes a third set of error correction bits associated with parity information stored at the second set of error correction elements; identify, by the second encoder/decoder component, a third error in the third set of data bits; and correct, by the second encoder/decoder component, the third error using the third codeword.”
However, Sharon, in an analogous art, teaches wherein the memory system is further configured to: receive, by the second encoder/decoder component, a third codeword associated with the first memory stripe and the second memory stripe (generate a combined codeword on the memory die 103 [Sharon PP 0018]), wherein the third codeword includes a third set of data bits associated with the data stored at the first set of data storage elements, the data stored at the second set of data storage elements, and data stored at the first set of error correction elements (transforms the plurality of individual, shorter codewords (e.g., codewords 160 , 162 , and 164 ) into one longer codeword that may span over multiple (or all) logical pages of a single word line. [Sharon PP 0035]), and wherein the third codeword includes a third set of error correction bits associated with parity information stored at the second set of error correction elements (generate combined parity bits 144 of the combined codeword [Sharon PP 0018]);
identify, by the second encoder/decoder component, a third error in the third set of data bits (the decoder 118 may initiate a decoding operation using the combined codeword [Sharon PP 0025]); and
correct, by the second encoder/decoder component, the third error using the third codeword (The error-corrected versions of the representation 148 of the second codeword 162 and the representation 150 of the third codeword 164 may be used, with the combined parity bits 144 , by the decoder 118 to decode the first codeword 160 [Sharon PP 0025]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have the memory system disclosed by Jeddeloh to incorporate Sharon's teaching of codeword combining, in order to improve error correction capability in memory devices (longer error correction codes typically provide better error correction and a lower error floor than shorter error correction codes, resulting in higher reliability [Sharon PP 0032]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Jeddeloh's invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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