DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
A title such as the following is suggested: Power Converter with Frequency Adjusted Based on Load Current.
Claim Objections
Claim 11 is objected to because of the following informalities: “one or more charge pump” should be ‘one or more charge pumps’. Likewise, “one or more boost converter” should be ‘one or more boost converters’.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-15 are rejected under 35 U.S.C. 102a1 as being anticipated by Ahmed (US 2018/0026526).
With respect to claim 13, Ahmed discloses a method of operating a power converter having a first converter stage (Fig. 1 110) and a second converter stage (Fig.1 1 120), the method comprising generating a first clock signal (Fig. 1 140) for the first converter stage; and adjusting (Fig. 4 415) a frequency of the first clock signal based on a load current (Fig. 1 Sensed current value).
With respect to claim 14, Ahmed discloses the method as claimed in claim 13, wherein the first clock signal has a default frequency (paragraph 17, 500kHz), the method further comprising estimating (Fig. 1 155) the load current; increasing the frequency (Fig. 1 paragraph 17, 1MHz) of the first clock signal above the default frequency when the load current increases above a first threshold value (paragraph 16, first threshold); and lowering the frequency of the first clock signal below (paragraph 17, 250kHz) the default frequency when the load current decreases below a second threshold value (paragraph 16, second threshold).
With respect to claim 15, Ahmed discloses the method as claimed 14, comprising maintaining the first clock signal with the default frequency (paragraph 16, 500kHz) when the load current is between the first threshold value and the second threshold value.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed (US 2018/0026526) in view of Harriman (US 2010/0109713).
With respect to claim 1, Ahmed discloses a power converter comprising a first converter stage (Fig. 1 110) adapted to receive a first clock signal (Fig. 1 140); a second converter stage (Fig. 1 120); and a clock circuit (Fig. 1 145) Ahmed remains silent as to the details of the second converter stage.
Harriman discloses a converter stage adapted to receive a second clock signal (Fig. 1 34) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a second converter stage adapted to receive a second clock signal in order to provide the periodic timing needed to control the second converter.
With respect to claim 2, Ahmed in view of Harriman make obvious the power converter as claimed in claim 1, wherein the clock circuit is configured to increase the frequency of the first clock signal above (paragraph 17, 1MHz) a default frequency (paragraph 17, 500 kHz) when the load current increases above a first threshold value (paragraph 16, first threshold) and to lower the frequency of the first clock signal below (paragraph 17, 250kHz) the default frequency when the load current decreases below a second threshold value (paragraph 16, second threshold).
With respect to claim 3, Ahmed in view of Harriman make obvious the power converter as claimed in claim 1, wherein the clock circuit is configured to estimate the load current based on (Fig. 1 155) a sense signal (Fig. 1 Sensed current value) from the second converter stage (Fig. 1 120).
With respect to claim 4, Ahmed in view of Harriman make obvious the power converter as claimed in claim 3, wherein the sense signal comprises a voltage indicative of an inductor current (paragraph 15, senses current in transistors M1 or M2 which is the current to the inductors L1-L4) of the second converter stage.
With respect to claim 5, Ahmed in view of Harriman make obvious the power converter as claimed in claim 3, wherein the clock circuit comprises an operation frequency control loop (Fig. 1 140,145,110,Vout,125,175) coupled to an oscillator (Fig. 1 145), the operation frequency control loop being configured to generate a control signal (Fig. 1 175) to adjust the frequency of the first clock signal generated by the oscillator.
With respect to claim 8, Ahmed in view of Harriman make obvious the power converter as claimed in claim 1, comprising a clock generator (Harriman Fig. 1 14) configured to generate the second clock signal.
With respect to claim 9, Ahmed in view of Harriman make obvious the power converter as claimed in claim 1, wherein the first converter stage comprises one or more capacitive divider (Fig. 1 112,114,S1-S4); and wherein the second converter stage comprises one or more buck converter (Fig. 1 M1,M2,L1-L4).
With respect to claim 12, Ahmed in view of Harriman make obvious the power converter as claimed in claim 1, wherein the second converter stage comprises a plurality of phases (Fig. 1 4 phases) and wherein the power converter further comprises an integrator (Fig. 1 155) configured to sum sense signals from each phase (paragraph 15 and Fig. 1 current through each transistor of each phase is summed for the total current).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ahmed (US 2018/0026526) in view of Harriman (US 2010/0109713) and further in view of Kaneda (US 2016/0156261).
With respect to claim 6, Ahmed in view of Harriman make obvious the power converter as claimed in claim 5 as set forth above, and Ahmed remains silent as to the details of the clock circuit and controller. The use of of comparators to determine whether a signal fell within a specified range of values was well known before the effective filing date of the claimed invention.
Kaneda discloses wherein the clock circuit comprises a plurality of comparators (Fig. 1 14), each comparator being configured to compare the sense signal from the second converter stage with a reference value (Fig. 4 IREF; 2*Iref) associated with the comparator, and to provide a comparison signal (Fig. 1 14C,14D). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the clock circuit comprises a plurality of comparators, each comparator being configured to compare the sense signal from the second converter stage with a reference value associated with the comparator, and to provide a comparison signal, in order to determine the range the load current was in, in order to select the corresponding clock frequency.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ahmed (US 2018/0026526) in view of Harriman (US 2010/0109713), Kaneda (US 2016/0156261) and further in view of Han (US 2014/0365151).
With respect to claim 7, Ahmed in view of Harriman and Kaneda make obvious the power converter as claimed in claim 6, and Ahmed remains silent as to using a lookup table for the current measurement. It was well known before the effective filing date of the claimed invention to use a look up table to measure current.
Han discloses wherein the control loop is configured to estimate the load current (Fig. 8 Io_est) using a look up table [paragraph 42] listing a plurality of load current values (Fig. 9 0[A]-210[A]) associated with corresponding sense signal values (Fig. 9 0[V]-5.0[V]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the operation frequency control loop is configured to estimate the load current using a look up table listing a plurality of load current values associated with corresponding sense signal values, in order to translate the measured current values to the actual current.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ahmed (US 2018/0026526) in view of Harriman (US 2010/0109713) and further in view of Azrai (US 2005/0213267).
With respect to claim 10, Ahmed in view of Harriman make obvious the power converter as claimed in claim 1, and remain silent as to implementing a plurality of capacitive dividers. It was well known before the effective filing date of the claimed invention to implement a plurality of capacitive dividers.
Azrai discloses wherein the first converter stage comprises a plurality of capacitive dividers (Fig. 3 34’s) coupled in series, and wherein the clock circuit (Fig. 2 21) is configured to provide the first clock signal to at least one (Fig. 3 control signals P1-P5) of the capacitive dividers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the first converter stage comprises a plurality of capacitive dividers coupled in series, and wherein the clock circuit is configured to provide the first clock signal to at least one of the capacitive dividers, in order to reduce the input voltage to the desired output voltage over a wide range of input and output voltages.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ahmed (US 2018/0026526) in view of Harriman (US 2010/0109713) and further in view of Matei (US 2022/0302826).
With respect to claim 11, Ahmed in view of Harriman make obvious the power converter as claimed in claim 1, wherein the voltage is lowered not raised. It was known before the effective filing date of the claimed invention to boost the supply voltage to power higher voltage loads.
Matai discloses wherein the first converter stage comprises one or more charge pump (Fig. 1 105); and wherein the second converter stage comprises one or more boost converter (Fig. 1 110). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the first converter stage comprises one or more charge pump; and wherein the second converter stage comprises one or more boost converter, in order to power loads requiring higher voltage than the available supply voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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