DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 10-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0311783 A1) in view of Suzuki (US 2008/0304204 A1).
Regarding claim 1, Lee et al. disclose a multilayer ceramic capacitor that has a dimension in a first direction along a first axis (T) equal to or greater than 1.5 times [0013] a dimension in a second direction along a second axis (W) orthogonal to the first axis (T), and is to be mounted on a mounting surface (Fig. 5) perpendicular to the first axis (T), the multilayer ceramic capacitor comprising:
a ceramic body (11) having a pair of main surfaces perpendicular to the first axis (T), a pair of side surfaces perpendicular to the second axis (W), and a pair of end surfaces perpendicular to a third axis (L) orthogonal to the first axis (T) and the second axis (W); and
a pair of external electrodes (131, 132) covering the pair of end surfaces, respectively, wherein the ceramic body further includes:
a multilayer portion (11, 21, 22) including a plurality of internal electrodes (21, 22) that are alternately stacked with ceramic layers (11) along a stacking direction parallel to the first axis (T) or the second axis (W) and are led out to the end surfaces, and
a pair of margin portions that are formed along the stacking direction (T), cover the multilayer portion (11, 21, 22) from a width direction (W) of the internal electrodes (21,22), wherein the width direction (W) being orthogonal to the stacking direction (T) and the third axis (L),
wherein the plurality of internal electrodes (21, 22) includes:
a plurality of inner-side internal electrodes (see fig. 2) located in an inner side in the stacking direction, and
a plurality of outer-side internal electrodes (21, 22) that are located in both outer sides in the stacking direction (T) and have a maximum width dimension (Wb) smaller than a minimum width dimension (Wa) of the inner-side internal electrodes.
Lee et al. disclose the claimed invention except for the pair of margin portions contain an additive element composed of at least one of the following elements: Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, a rare earth element, and Sn at a higher concentration than the multilayer portion.
Suzuki discloses a multilayer ceramic capacitor comprising a pair of margin portions (13b, 13b – Fig. 3), wherein the pair of margin portions (13b, 13b) contain an additive element composed of Mg at a higher concentration [0083] than a multilayer portion (1,2,3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the margin portion of Lee et al. so that the pair of margin portions contain an additive element composed of Mg at a higher concentration than the multilayer portion since such a modification would form a highly reliable multilayer ceramic capacitor having improved moisture resistance.
Regarding claim 2, Lee et al. disclose the maximum width dimension of the outer-side internal electrodes (top-bottom) is equal to or greater than two times a thickness dimension of each of the margin portions (see Fig. 1, 2).
Regarding claim 3, Lee et al. disclose the maximum width dimension (see Fig. 2) of the outer-side internal electrodes (top-bottom) is equal to or less than 10 times a thickness dimension of each of the margin portions (see Fig. 2).
Regarding claim 4, the modified Lee et al. disclose respective distances in the width direction (W) between the margin portions and end portions in the width direction of the outer-side internal electrodes (21, 22) are equal to or greater than a thickness dimension of each of the margin portions.
Regarding claim 5, the modified Lee et al. disclose respective distances in the width direction (W) between the margin portions and end portions in the width direction of the outer-side internal electrodes (21, 22) are equal to or less than five times a thickness dimension of each of the margin portions.
Regarding claim 6, the modified Lee et al. disclose the number of the outer-side internal electrodes (top 2 – Fig. 2) stacked in one side in the stacking direction (T) is equal to or greater than 5% of and equal to or less than 25% of the number of all the internal electrodes (21, 22).
Regarding claim 7, the modified Lee et al. disclose the stacking direction is parallel to the second axis (Fig. 3 – W), and wherein the width direction of the internal electrodes is parallel to the first axis (T – Fig. 4).
Regarding claim 10, Lee et al. disclose a circuit board comprising:
the multilayer ceramic capacitor (1) according to claim 1; and
a mounting substrate (210) having the mounting surface (210) and a pair of connection electrodes (221, 222),
the pair of connection electrodes (221, 222) being provided on the mounting surface and connected to the pair of external electrodes (31, 32) of the multilayer ceramic capacitor (1) through solder (230).
Regarding claim 11, Lee et al. disclose a multilayer ceramic capacitor that has a dimension in a first direction (T) along a first axis (T) equal to or greater than 1.3 times a dimension in a second direction (W) along a second axis (W) orthogonal to the first axis (T), and is to be mounted on a mounting surface (bottom) perpendicular to the first axis (T), the multilayer ceramic capacitor comprising:
a ceramic body (1) having a pair of main surfaces (top, bottom) perpendicular to the first axis (T), a pair of side surfaces (front-back) perpendicular to the second axis (W), and a pair of end surfaces (left-right) perpendicular to a third axis (L) orthogonal to the first axis (T) and the second axis (W); and
a pair of external electrodes (31, 32) covering the pair of end surfaces, respectively, wherein the ceramic body further includes:
a multilayer portion including a plurality of internal electrodes (21, 22) that are alternately stacked with ceramic layers (11) along a stacking direction parallel to the first axis (T) or the second axis (W) and are led out to the end surfaces, and a pair of margin portions that are formed along the stacking direction (T), cover the multilayer portion from a width direction of the internal electrodes,
wherein the plurality of internal electrodes (21, 22) includes: a plurality of inner-side internal electrodes located in an inner side in the stacking direction (T), and
a plurality of outer-side internal electrodes that are located in both outer sides in the stacking direction (T) and have a maximum width dimension smaller than a minimum width dimension of the inner-side internal electrodes (see Fig. 1).
Lee et al. disclose the claimed invention except for the pair of margin portions contain an additive element composed of at least one of the following elements: Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, a rare earth element, and Sn at a higher concentration than the multilayer portion.
Suzuki discloses a multilayer ceramic capacitor comprising a pair of margin portions (13b, 13b – Fig. 3), wherein the pair of margin portions (13b, 13b) contain an additive element composed of Mg at a higher concentration [0083] than a multilayer portion (1,2,3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the margin portion of Lee et al. so that the pair of margin portions contain an additive element composed of Mg at a higher concentration than the multilayer portion since such a modification would form a highly reliable multilayer ceramic capacitor having improved moisture resistance.
Regarding claim 12, Lee et al. disclose the maximum width dimension of the outer-side internal electrodes (top-bottom) is equal to or greater than two times a thickness dimension of each of the margin portions (see Fig. 1, 2).
Regarding claim 13, Lee et al. disclose the maximum width dimension (see Fig. 2) of the outer-side internal electrodes (top-bottom) is equal to or less than 10 times a thickness dimension of each of the margin portions (see Fig. 2).
Regarding claim 14, the modified Lee et al. disclose respective distances in the width direction (W) between the margin portions and end portions in the width direction of the outer-side internal electrodes (21, 22) are equal to or greater than a thickness dimension of each of the margin portions.
Regarding claim 15, the modified Lee et al. disclose respective distances in the width direction (W) between the margin portions and end portions in the width direction of the outer-side internal electrodes (21, 22) are equal to or less than five times a thickness dimension of each of the margin portions.
Regarding claim 16, the modified Lee et al. disclose the number of the outer-side internal electrodes (top 2 – Fig. 2) stacked in one side in the stacking direction (T) is equal to or greater than 5% of and equal to or less than 25% of the number of all the internal electrodes (21, 22).
Regarding claim 17, the modified Lee et al. disclose the stacking direction is parallel to the second axis (Fig. 3 – W), and wherein the width direction of the internal electrodes is parallel to the first axis (T – Fig. 4).
Regarding claim 20, Lee et al. disclose a circuit board comprising:
the multilayer ceramic capacitor (1) according to claim 1; and
a mounting substrate (210) having the mounting surface (210) and a pair of connection electrodes (221, 222),
the pair of connection electrodes (221, 222) being provided on the mounting surface and connected to the pair of external electrodes (31, 32) of the multilayer ceramic capacitor (1) through solder (230).
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0311783 A1) and Suzuki (US 2008/0304204 A1), as applied to claims 7 and 17 above, and further in view of Mizuno et al. (US 2007/0025055 A1).
Regarding claims 8 and 18, Lee et al. disclose the claimed invention except for the main surfaces have a higher flatness than the side surfaces.
Mizuno et al. disclose in fig. 3, a multilayer ceramic capacitor comprising internal electrodes (13), wherein the internal electrodes have a main surface and side surfaces (see Fig. 3), wherein the main surfaces have a higher flatness than the side surfaces.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor of Lee et al. so that the main surfaces have a higher flatness than the side surfaces, since such a modification would prevent cracks generated in the multilayer ceramic capacitor when the capacitor is soldered to a printed circuit board.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0311783 A1) and Suzuki (US 2008/0304204 A1), as applied to claims 1 and 19 above, and further in view of Teraoka et al. (US 2016/0227650).
Regarding claims 9 and 19, Lee et al. disclose the claimed invention except for a package comprising: the multilayer ceramic capacitor according to claim 1; a carrier tape having a sealing surface perpendicular to the first axis, and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess.
Teraoka discloses in fig. 9A-9B, a package comprising:
a multilayer ceramic capacitor (100)
a carrier tape (60) having a sealing surface (@ 61) perpendicular to a first axis, and a recess (60a) that is recessed from the sealing surface (@61) in the first direction (top-bottom) and accommodates the multilayer ceramic capacitor (100); and
a top tape (61) that is attached to the sealing surface (@61) and covers the recess.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the multilayer ceramic capacitor of Lee et al. in a package, wherein the package includes a carrier tape having a sealing surface perpendicular to the first axis, and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess, since such a modification would provide a carrier for multiple capacitors with high-capacitance having excellent reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2018/0166217 A1 – multilayer ceramic capacitor higher flatness than the side surfaces
US 2016/0227650 A1 – multilayer ceramic capacitor having internal electrodes arranged perpendicular to a substrate
US 2015/0287533 A1 – multilayer ceramic capacitor wherein T > W
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/ERIC W THOMAS/Primary Examiner, Art Unit 2847
ERIC THOMAS
Primary Examiner
Art Unit 2847
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