Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is responsive to the Amendment and Response filed August 11, 2026 ("the Response"), which replies to the non-final Office action mailed May 13, 2026. In the Response, claims 1, 5-8, 12-15, and 19-20 are amended, claims 17-18 are canceled, and new claims 21-22 are added. The amendment has been entered. Claims 1-16 and 19-22 are pending and are examined herein.
Specification
The objection to the title set forth in the previous Office action is withdrawn. The claims as amended recite a "self-selecting bus decoder," and the existing title, "Methods and Systems for Devices with Self-Selecting Bus Decoder," is now clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
The instant application is a continuation in a chain of continuations of Application No. 12/268,270 (now US 8,402,188), and US 9,785,588, US 10,180,922, and US 10,942,877 each name the same inventors and are commonly assigned. None of the reference patents is available as prior art against the instant application; the rejections below rest solely on the reference patents' claims.
3. Claims 1-16, 19-20, and 22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 9,785,588 ("'588"). Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are either anticipated by, or would have been obvious over, the reference claims, as follows.
Regarding claim 1, '588 claim 16 recites "[a] device, comprising: a self-selecting bus decoder comprising logic configured to: receive a memory mapping configuration; receive a request via a microcontroller bus; and determine if the device should provide a response to the request, based at least in part upon the memory mapping configuration" (instant: a device comprising a circuit comprising a self-selecting bus decoder configured to receive a memory mapping configuration, and to directly receive a signal comprising an operation associated with a memory address from the integrated circuit (the microcontroller on whose bus the request is received)). '588 claim 20 (depending from claim 16) further recites that the decoder "is configured to determine that the device should provide the response when a memory address associated with the request is associated with at least one of a plurality of memory addresses indicated by the memory mapping configuration" (instant: map the memory address based on the memory mapping configuration, and determine that the memory address is mapped to the memory based on the memory address being included in the range of memory addresses). Providing the response when so determined corresponds to the instant "in response to determining ... fulfill the operation" (see also '588 claim 18: "a signal to enable the device to respond to the request"). The claims of '588 do not expressly recite, in claim 16, that the device comprises "memory" or that the indicated addresses are "a range of memory addresses of the memory to be added to an integrated circuit." However, '588 claim 7 recites that the device "comprises double data rate two (DDR2) RAM," and '588 claim 4 recites that "the memory mapping configuration comprises an indication of a plurality of memory addresses provided by the device." It would have been obvious to a person of ordinary skill in the art before the effective filing date to include in the device of '588 claim 16 the RAM and the device-provided plurality of memory addresses recited in '588 claims 4 and 7, because '588 itself claims those features for the same self-selecting bus decoder device, and a set of memory addresses provided by the device's memory that is indicated to the microcontroller-facing decoder is, under the broadest reasonable interpretation, a range of addresses of that memory added to (made accessible to) the microcontroller. The combination is merely the arrangement of features already recited in the reference patent's claims for their established functions, yielding predictable results.
Regarding claim 8, '588 claim 11 recites a method comprising "receiving a request from a microcontroller via a bus; determining a memory address of the request; determining if the memory address is provided by an external device coupled to the microcontroller via the bus; determining a type of the memory request; and determining a response to the memory request," and '588 claim 13 adds "receiving a memory mapping configuration at the external device." '588 claim 12 adds "providing a response from the external device to the microcontroller" (instant: fulfilling the operation). '588 claims 11-13 do not expressly recite that the recited steps are performed "via a self-selecting bus decoder" or that the determination is "based on the memory address being included in the range of memory addresses." '588 claims 16 and 20 recite a self-selecting bus decoder that receives the memory mapping configuration and determines that the device should respond when the request's memory address is among the memory addresses indicated by the memory mapping configuration, and '588 claim 4 recites that the configuration indicates memory addresses provided by the device. It would have been obvious to perform the method steps of '588 claims 11-13 via the self-selecting bus decoder of '588 claims 16 and 20, using the device-provided address indication of '588 claim 4, because the reference patent claims that decoder as the structure that performs precisely those determining steps, with predictable results.
Regarding claim 15, '588 claim 1 recites "[a] system, comprising: a microcontroller; and a device coupled to the microcontroller via a bus, wherein the device comprises a self-selecting bus decoder configured to: receive a memory mapping configuration; receive a request from the microprocessor; and determine if the device should provide a response to the request from the microcontroller, based at least in part upon the memory mapping configuration" (instant: a system comprising an integrated circuit and a peripheral device comprising a self-selecting bus decoder configured to receive a memory mapping configuration and directly receive a signal from the integrated circuit). '588 claim 6 recites that the decoder "is configured to determine that the device should provide the response when a memory address associated with the request is provided by the device based on the memory mapping configuration" (instant: map the address and determine that it is mapped to the memory). '588 claim 4 recites that the memory mapping configuration "comprises an indication of a plurality of memory addresses provided by the device" (instant: range of memory addresses of the memory), and '588 claim 7 recites that the device "comprises double data rate two (DDR2) RAM" (instant: memory). The reference claims do not use the term "range." However, a plurality of memory addresses provided by the device's RAM that is indicated to the microcontroller is, under the broadest reasonable interpretation, a range of memory addresses of the memory added to the microcontroller, and it would have been obvious to combine the features of '588 claims 1, 4, 6, and 7 for the reasons given for claim 1 above.
Regarding claims 2, 9, and 16, '588 claim 7 recites that the device "comprises double data rate two (DDR2) RAM." DDR2 RAM is a species of DRAM, and a species anticipates the genus.
Regarding claims 3 and 10, '588 claim 8 recites that "the request comprises a memory read, a memory write, a memory refresh, a DMA request, or any combination thereof." A memory write is a data storage operation (claim 3) and fulfilling it stores data (claim 10).
Regarding claims 4 and 11, '588 claim 2 recites that "the device comprises a pattern recognition processor." '588 claim 2 does not expressly recite that the operation comprises a data processing operation; however, a request directed to a pattern recognition processor is an operation that is fulfilled by processing data, and it would have been obvious to direct the request of '588 claim 1 to the pattern recognition processing function of the device of '588 claim 2, because that is the function the device is claimed to provide.
Regarding claims 5, 12, and 19, '588 claims 6 and 20 recite determining, for the memory address associated with the request, whether it is provided by the device / associated with the addresses indicated by the memory mapping configuration. '588 claims 6 and 20 do not expressly recite doing so for "each signal"; however, the decoder of '588 claims 1 and 16 evaluates every request it receives against the memory mapping configuration, and applying that determination to each received request would have been obvious as the ordinary, repeated operation of the claimed decoder.
Regarding claims 6, 13, and 20, '588 claim 17 recites "logic to determine a type of the request and a response to the request" (see also '588 claims 9 and 11: "determining a type of the memory request") (instant: identifying a type of the operation), and '588 claim 18 recites "logic configured to provide a signal to enable the device to respond to the request" (instant: initiating a peripheral function circuit of the device to provide a response). '588 claim 15 further recites that "determining a response to the memory request comprises selecting a function of the external device." The reference claims do not use the term "peripheral function circuit"; however, the device function that is enabled or selected to respond to the request is, under the broadest reasonable interpretation, a peripheral function circuit of the device, and it would have been obvious to combine '588 claims 15, 17, and 18 as recited features of the same decoder.
Regarding claims 7 and 14, '588 claim 8 recites memory read, memory write, memory refresh, and DMA requests, each of which is a peripheral function associated with the memory performed for the microcontroller. '588 claim 8 does not expressly recite that these are performed by "the peripheral function circuit"; however, it would have been obvious that the selected device function of '588 claims 15 and 18 performs the memory operations of '588 claim 8, as those are the requests that the claimed device responds to.
Regarding claim 22, '588 claim 5 recites that "the memory mapping configuration comprises an indication of a plurality of memory addresses provided by the microcontroller" (instant: the memory mapping configuration further indicates another range of memory addresses to be provided by the integrated circuit).
4. Claims 1-3, 5-10, 12-16, and 19-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 10,180,922 ("'922"). Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons.
Regarding claim 15, '922 claim 1 recites "[a] system, comprising: a microcontroller; and a peripheral device, directly coupled to the microcontroller, wherein the peripheral device is configured to: generate a memory map; receive a signal from the microcontroller; determine whether the peripheral device should respond to the signal based at least in part upon the memory map; and respond to the signal only when it is determined that the peripheral device should respond to the signal" (instant: a system comprising an integrated circuit and a peripheral device that directly receives a signal from the integrated circuit and fulfills the operation when the address is mapped to its memory). '922 claim 2 recites that the peripheral device "is configured to generate the memory map based upon a received decode set-up and control signal" (instant: receive a memory mapping configuration). '922 claim 8 recites that "the decode set-up and control signal specifies a range of memory addresses provided by memory of the peripheral device, a range of memory addresses provided by the microcontroller, or both" (instant: memory mapping configuration to set up a range of memory addresses of the memory to be added to the integrated circuit), and '922 claim 11 recites that the peripheral device "is configured to determine whether the peripheral device should respond based on whether a memory address of the signal is in memory map" (instant: map the memory address based on the memory mapping configuration and determine that the memory address is mapped to the memory based on inclusion in the range). '922 claim 4 recites that "the peripheral device comprises a memory device" (instant: memory). The '922 claims do not expressly recite that the peripheral-device logic performing these functions is a "self-selecting bus decoder." However, logic of a peripheral device that receives a bus signal, decodes its address against the device's memory map, and itself determines whether the device should respond is, under the broadest reasonable interpretation, a self-selecting bus decoder, and it would have been obvious to a person of ordinary skill in the art to so designate and implement that logic, as a mere labeling of the structure that '922 claims 1, 2, 8, and 11 already require. The instant claim would have been obvious over '922 claims 1, 2, 4, 8, and 11.
Regarding claims 1 and 8, the device of claim 1 and the method of claim 8 recite the same self-selecting bus decoder functions as claim 15 without the separately recited integrated circuit, and are therefore broader in that respect. They would have been obvious over '922 claims 1, 2, 4, 8, and 11 for the reasons given for claim 15; the steps of method claim 8 are the operations the '922 peripheral device is configured to perform.
Regarding claims 2, 9, and 16, '922 claim 9 recites that "the memory device comprises a DRAM memory device."
Regarding claims 3 and 10, '922 claim 4 recites that the peripheral device comprises a memory device. '922 claim 4 does not expressly recite a data storage operation; however, storing data in response to a request is the ordinary function of a memory device, and it would have been obvious for the '922 peripheral device to respond to a signal requesting that data be stored in its memory device.
Regarding claims 5, 12, and 19, '922 claim 11 recites determining whether to respond "based on whether a memory address of the signal is in memory map." Doing so for each received signal is the ordinary, repeated operation of the claimed device, for the reasons given for the corresponding '588 rejection above.
Regarding claims 6, 13, and 20, '922 claim 3 recites that, "upon determining that the peripheral device should respond to the signal, perform a bus-cycle validation to identify whether a requested operation may be properly satisfied by the peripheral device; [and] when the requested operation may be properly satisfied by the peripheral device, provide a cycle enable signal to initiate functionality of the peripheral device" (instant: identifying a type of the operation, and initiating a peripheral function circuit of the device to provide a response). The '922 claim does not use the words "type of the operation" or "peripheral function circuit"; however, identifying whether a requested operation may be properly satisfied requires identifying what operation is requested, and the functionality initiated by the cycle enable signal is, under the broadest reasonable interpretation, a peripheral function circuit. It would have been obvious to so implement '922 claim 3.
Regarding claims 7 and 14, the functionality of '922 claim 3 initiated for a peripheral device comprising a memory device ('922 claim 4) is a peripheral function associated with the memory performed for the microcontroller. It would have been obvious to combine '922 claims 3 and 4 as recited features of the same system.
Regarding claim 21, '922 claim 6 recites "[t]he system of claim 1 without any external devices that facilitate memory management, decoding, or both" (instant: the integrated circuit does not provide any memory management function to enable the memory of the device to be added). '922 claim 6 does not expressly recite that the microcontroller itself provides no memory management function; however, where the peripheral device self-generates its memory map from the decode set-up and control signal and no external device facilitates memory management or decoding, it would have been obvious that the microcontroller need not provide such a function, because the '922 peripheral device claims the memory-mapping and decoding responsibility for itself.
Regarding claim 22, '922 claim 8 recites that the decode set-up and control signal "specifies ... a range of memory addresses provided by the microcontroller, or both" (instant: the memory mapping configuration further indicates another range of memory addresses to be provided by the integrated circuit).
5. Claims 1-3, 5-10, 12-16, and 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 10,942,877 ("'877") in view of the PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, December 18, 1998 ("PCI 2.2").
Regarding claim 1, '877 claim 1 recites "[a] self-selecting bus decoder electronic device, configured to: communicatively couple to a controller electronic device, wherein the self-selecting bus decoder electronic device is peripheral to the controller electronic device; receive one or more signals from the controller electronic device, the one or more signals comprising a request for memory access to memory associated with the self-selecting bus decoder electronic device; and in response to receiving the one or more signals from the controller electronic device, self-selecting the memory access, resulting in provision of the memory access to the memory by the controller electronic device" (instant: device comprising memory and a self-selecting bus decoder that directly receives a signal comprising an operation associated with a memory address from the integrated circuit and fulfills the operation). '877 claims 3 and 9 recite determining that the memory is associated with the device by "identifying a memory address specified in the request for memory access; and determining that the memory address is within a memory address range associated with the self-selecting bus decoder electronic device," and self-selecting the memory access based upon that association (instant: map the memory address and determine that it is mapped to the memory based on being included in the range of memory addresses; fulfill in response). The '877 claims do not recite that the self-selecting bus decoder "receive[s] a memory mapping configuration to set up" the range of memory addresses of the memory "to be added to" the controller.
In the same field of endeavor, PCI 2.2 teaches that "PCI targets (except host bus bridges) are required to implement Base Address register(s) to request a range of addresses which can be used to provide access to internal registers or functions," and that "[t]he configuration software uses the Base Address register to determine how much space a device requires in a given address space and then assigns (if possible) where in that space the device will reside" (PCI 2.2, § 3.2.2, p. 27); see also § 6.2.5.1, p. 202 (Base Address register bits "are used to map the device into" the address space). That is, the peripheral target receives, via its Base Address register, a configuration that sets up the range of addresses of the device that is mapped into the address space used by the host (instant: receive a memory mapping configuration to set up a range of memory addresses of the memory to be added to an integrated circuit).
It would have been obvious to a person of ordinary skill in the art before the effective filing date to have the self-selecting bus decoder electronic device of '877 claims 1, 3, and 9 receive the configuration that sets up its "memory address range" in the manner taught by PCI 2.2, because the '877 claims require a memory address range associated with the device but are silent on how it is established, and PCI 2.2 teaches a known, standardized technique for establishing such a range so that a device can be relocated in the host's address space (PCI 2.2, § 6.2.5, p. 201: "One of the most important functions for enabling superior configurability and ease of use is the ability to relocate PCI devices in the address spaces."). The combination applies a known technique to a known device ready for improvement to yield predictable results (MPEP 2143(I)(D)), and one of ordinary skill would have had a reasonable expectation of success because the PCI Base Address mechanism is a register-based configuration of exactly the range that the '877 decoder compares against.
Regarding claims 8 and 15, '877 claims 13 and 15 recite a method of receiving, at a self-selecting bus decoder electronic device peripheral to a controller electronic device, a request for memory access; determining, via the self-selecting bus decoder, whether the memory is associated with the device by identifying the memory address and determining that it "is within a memory address range associated with the self-selecting bus decoder electronic device"; and, when associated, "self-selecting the memory access, resulting in provision of the memory access to the memory by the controller electronic device" (claim 8). '877 claim 19 recites the controller electronic device that provides the request signal to the self-selecting bus decoder device, and together with '877 claim 1 defines a system of a controller (instant: integrated circuit) and a peripheral self-selecting bus decoder device (claim 15). The missing memory-mapping-configuration limitation would have been obvious in view of PCI 2.2 for the reasons given for claim 1.
Regarding claims 2, 9, and 16, '877 does not claim DRAM. PCI 2.2 teaches target storage media including "DRAM" (PCI 2.2, § 3.5.1.1, p. 75: "the access time of the storage media (e.g., disk, DRAM, etc.)"). It would have been obvious to implement the memory of the '877 device as DRAM, a well-known memory type for bus-attached targets, with predictable results.
Regarding claims 3 and 10, '877 claims 5 and 16 recite that the request comprises "a request to perform a memory operation, the memory operation comprising: a read operation, a write operation, a refresh operation, or any combination thereof." A write operation is a data storage operation that stores data.
Regarding claims 5, 12, and 19, '877 claims 7, 9, and 17 recite address-matching comprising "identifying a memory address specified in the request for memory access; and determining whether the memory address is within a memory address range associated with the self-selecting bus decoder electronic device." Performing that address-matching for each received signal is the ordinary operation of the claimed decoder.
Regarding claims 6, 13, and 20, '877 claims 6, 7, and 17 recite bus-cycle validation comprising "determining that the request can be satisfied by a peripheral device associated with the self-selecting bus decoder electronic device; and upon determining that request can be satisfied by the peripheral device, providing a signal to initiate a peripheral function to satisfy the request." Determining whether a request can be satisfied requires identifying the type of the requested operation; it would have been obvious to so identify it.
Regarding claims 7 and 14, the peripheral function of '877 claim 6 that satisfies a memory-access request ('877 claim 5: read, write, refresh) is a peripheral function associated with the memory performed for the controller.
Reference patents considered but not applied. The claims of US 8,402,188 (each independent claim requires a bus translator or a pattern-recognition processor), US 10,572,414 (identifying a "particular functionality" via a memory map), US 11,782,859 (bus-cycle validation circuitry without address-range mapping), and US 12,197,363 (pattern-recognition processor as supplemental microcontroller functionality) have been reviewed. Although they share the specification of the instant application, their claims are directed to features not recited in the instant claims and they are not relied on for double patenting at this time. Applicant is reminded that any terminal disclaimer filed to overcome the above rejections should be directed to each of US 9,785,588, US 10,180,922, and US 10,942,877.
Claim Objections
6. Claim 1 is objected to because of the following informality: in line 3, "a circuit comprises a self-selecting bus decoder configured to" is grammatically incomplete. It is suggested that the phrase be amended to read "a circuit that comprises a self-selecting bus decoder configured to."
Appropriate correction is required.
Claim Interpretation
7. The term "self-selecting bus decoder" is given its broadest reasonable interpretation in light of the specification, which describes a decoder of a peripheral device that "receives a memory mapping configuration and self-selects memory access, as requested by a signal from the microcontroller 94 on each bus-cycle" (Spec. ¶ [0077]) and that determines whether the peripheral device "should respond to this address range, i.e., if the memory address range is 'mapped' to the peripheral device" (Spec. ¶ [0079]). Under that interpretation, a bus decoder of a device that itself decodes a bus address against an address range assigned to that device and claims (selects) the bus transaction for the device when the address falls in that range is a "self-selecting bus decoder."
8. The phrase "to be added to an integrated circuit" in claims 1, 8, and 15 is interpreted as requiring that the configured range of memory addresses of the device's memory be made accessible (i.e., mapped into the address space used by) the integrated circuit that issues the signal.
9. New claim 21 recites a negative limitation directed to the integrated circuit ("the integrated circuit does not provide any memory management function to enable the memory of the device to be added"). In device claim 1 the integrated circuit is not a positively recited element of the claimed device; claim 21 therefore further limits the environment in which the device operates. The limitation has nonetheless been considered in full.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-3, 5-10, 12-16, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, December 18, 1998 ("PCI 2.2"). PCI 2.2 was published more than one year before the earliest effective filing date of the instant claims (November 10, 2008); the 35 U.S.C. 102(b)(1) exceptions do not apply. Page citations below are to the printed page numbers of PCI 2.2.
Regarding claim 1, PCI 2.2 discloses a device (a PCI target device, e.g., a PCI add-in device on the PCI Local Bus; PCI 2.2, § 1.4, p. 3, Fig. 1-2) comprising: memory (a target "agent mapped in the Memory Address Space" from which data is read and to which data is written, § 3.1.1, p. 22; target "storage media (e.g., disk, DRAM, etc.)," § 3.5.1.1, p. 75); and a circuit comprises a self-selecting bus decoder (the target's address-decode logic: "each potential target compares the address with its Base Address register(s) to determine if it is the target of the current transaction. If it is the target, the device asserts DEVSEL# to claim the access," § 3.2.2, p. 27; "A target must do a full decode before driving/asserting DEVSEL#," § 3.6.1, p. 89; "positive decoding — A method of address decoding in which a device responds to accesses only within an assigned address range," Glossary, p. 300) configured to: receive a memory mapping configuration to set up a range of memory addresses of the memory to be added to an integrated circuit ("PCI targets (except host bus bridges) are required to implement Base Address register(s) to request a range of addresses which can be used to provide access to internal registers or functions ... The configuration software uses the Base Address register to determine how much space a device requires in a given address space and then assigns (if possible) where in that space the device will reside," § 3.2.2, p. 27; Base Address register bits "are used to map the device into" the address space, § 6.2.5.1, p. 202; the host bridge "provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address spaces," § 1.4, p. 3 — i.e., the assigned range is made accessible to the host bridge / processor integrated circuit); directly receive a signal from the integrated circuit, wherein the signal comprises an operation associated with a memory address ("Bus commands indicate to the target the type of transaction the master is requesting. Bus commands are encoded on the C/BE[3::0]# lines during the address phase," § 3.1, p. 21, including "Memory Read" (0110) and "Memory Write" (0111); "[t]he Memory Read command is used to read data from an agent mapped in the Memory Address Space," § 3.1.1, p. 22; the target is connected on the same PCI Local Bus as the bridge, § 1.4, p. 3, Fig. 1-2); map the memory address based on the memory mapping configuration (the target "compares the address with its Base Address register(s)," § 3.2.2, p. 27); determine that the memory address is mapped to the memory based on the memory address being included in the range of memory addresses ("If the first byte addressed by the transaction maps into the target's address range, it asserts DEVSEL# to claim the access," § 3.6.1, p. 89); and in response to determining that the memory address is mapped to the memory, fulfill the operation ("DEVSEL# is driven by the target of the current transaction ... to indicate that it is responding to the transaction," and "a target must assert DEVSEL# (claim the transaction) before or coincident with signaling any other target response," § 3.6.1, p. 88; the target "completes the initial data phase by asserting TRDY# (to accept or provide the requested data)," § 3.5.1.1, p. 75).
Regarding claim 2, PCI 2.2 discloses wherein the memory comprises DRAM (target "storage media (e.g., disk, DRAM, etc.)," § 3.5.1.1, p. 75).
Regarding claim 3, PCI 2.2 discloses wherein the operation comprises a data storage operation ("The Memory Write command is used to write data to an agent mapped in the Memory Address Space. When the target returns 'ready,' it has assumed responsibility for the coherency ... of the subject data," § 3.1.1, p. 22).
Regarding claim 5, PCI 2.2 discloses wherein the self-selecting bus decoder is configured to map a respective memory address of each signal received from the integrated circuit based on the memory mapping configuration ("When a transaction is initiated on the interface, each potential target compares the address with its Base Address register(s) to determine if it is the target of the current transaction," § 3.2.2, p. 27 — i.e., on every transaction).
Regarding claim 6, PCI 2.2 discloses wherein fulfilling the operation by the self-selecting bus decoder comprises: identifying a type of the operation ("Bus commands indicate to the target the type of transaction the master is requesting," § 3.1, p. 21, with the command encodings of § 3.1.1, p. 21); and initiating a peripheral function circuit of the device to provide a response to the integrated circuit (Base Address register ranges "provide access to internal registers or functions" of the target, § 3.2.2, p. 27; after claiming the transaction, the target "complete[s] the initial data phase ... by asserting TRDY# (to accept or provide the requested data)," § 3.5.1.1, p. 75).
Regarding claim 7, PCI 2.2 discloses wherein the peripheral function circuit is configured to perform one or more peripheral functions associated with the memory for the integrated circuit (memory read and memory write of data of "an agent mapped in the Memory Address Space," § 3.1.1, p. 22).
Regarding claims 8-10 and 12-14, method claims 8-10 and 12-14 recite the functions performed by the device of claims 1-3 and 5-7, respectively, as method steps performed "via" the self-selecting bus decoder, and are rejected for the same reasons, the cited PCI 2.2 target performing each recited step. As to claim 10, fulfilling a Memory Write command stores data (§ 3.1.1, p. 22).
Regarding claim 15, PCI 2.2 discloses a system (PCI Local Bus system, § 1.4, p. 3, Fig. 1-2), comprising: an integrated circuit (the "Bridge/Memory Controller" component through which the processor is connected to PCI, Fig. 1-2; § 1.4, p. 3); and a peripheral device (a PCI target device on the PCI Local Bus, e.g., an add-in board, § 1.4, p. 3), wherein the peripheral device comprises memory and a self-selecting bus decoder configured to perform the receiving, directly receiving, mapping, determining, and fulfilling functions recited, as discussed for claim 1 above, which discussion is incorporated here.
Regarding claims 16, 19, and 20, these claims recite the limitations of claims 2, 5, and 6, respectively, in the system of claim 15, and are rejected for the reasons given for those claims.
Claim Rejections - 35 USC § 103
11. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claims 4, 11 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over the PCI 2.2 in view of Gove et al. (“Gove”) (US No. 6,260,088).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Gove reference; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
Regarding claim 4, PCI 2.2 discloses the device of claim 1, as discussed above, in which the operation received from the integrated circuit is a bus command directed to a target whose Base Address register range "can be used to provide access to internal registers or functions" of the target (§ 3.2.2, p. 27). PCI 2.2 does not disclose wherein the operation comprises a data processing operation.
In the same field of endeavor, Gove teaches a single integrated circuit in which parallel processors 100-103 are connected via crossbar switch 20 to memories 10 (Gove, col. 6:63-7:9; Fig. 2), and in which the parallel processors "perform most of the system's operations," "perform the equivalent of many reduced instruction set computer (RISC)-like operations per cycle," and "provide a formidable data processing capability, particularly for image and graphics processing"; each parallel processor "can perform three accesses per cycle, through the crossbar switch to the memory, one for instructions and two for data. A multiply and an ALU operation can also be performed by each PP every cycle" (Gove, col. 35:39-53). Gove further teaches distributing data among the memories by address ("sliced addressing") so that the processors can operate on it in parallel (Gove, col. 23:7-26; Fig. 24). That is, Gove teaches arithmetic/logic data processing operations performed on data accessed at memory addresses.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to have the PCI 2.2 target device provide a data processing function (e.g., arithmetic/logic operations as taught by Gove) responsive to the operation received from the integrated circuit, because PCI 2.2 expressly contemplates targets whose address ranges provide access to device "functions" (§ 3.2.2, p. 27) and shows processing devices such as graphics and motion video on the bus (§ 1.4, p. 3, Fig. 1-2), and Gove teaches the known benefit of placing processors with multiply and ALU capability next to the memories holding the data so that data processing is performed with high throughput (Gove, col. 35:39-53). The combination uses a known technique to improve a similar device in the same way, yielding predictable results (MPEP 2143(I)(C)), and one of ordinary skill would have had a reasonable expectation of success because the PCI target claims and completes the transaction in the same manner regardless of the internal function that services it.
Regarding claim 11, PCI 2.2 in view of Gove teaches the method of claim 8, wherein fulfilling the operation comprises processing data, for the reasons given for claim 4.
Claims 21 and 22 are not rejected over prior art in this action; they stand rejected on the ground of nonstatutory double patenting as set forth above. See the Examiner's Note below.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Closest BRI reads in the PCI 2.2 rejection. Applicant may contest (a) that the PCI host "Bridge/Memory Controller" is "an integrated circuit" to which the memory is "added," and (b) that the Base Address register value written by configuration software is a "memory mapping configuration" that is "received" by the self-selecting bus decoder. The examiner's position is that under the broadest reasonable interpretation both are met: the bridge is a discrete bus component whose processor accesses the target's memory at the address range the Base Address register establishes (§ 1.4, p. 3; § 3.2.2, p. 27), and the Base Address register is a register of the target itself that receives the assigned range. If further support is required, the rejection may be supplemented with PCI 2.2 § 6.2.5 (pp. 201-204) and with the pertinent prior art listed below.
Claims 21 and 22. The examiner has not applied prior art to claim 21 (integrated circuit providing no memory-management function to enable the addition) or claim 22 (memory mapping configuration also indicating a range provided by the integrated circuit). In a PCI system, address-space management is performed by configuration software executing on the host, and each target's Base Address registers describe only that target's own ranges. These limitations correspond to the specification's description of a single-chip microcontroller that "does not provide any memory management, bus translation, or other externally accessible functions or components to enable the addition of the peripheral device" and a decode set-up and control signal that may specify "a range of memory addresses provided by the microcontroller" (Spec. ¶¶ [0076], [0079]). Claims 21 and 22 are not indicated as allowable because they stand rejected for double patenting and depend from rejected claim 1, and further search may be made if they are incorporated into an independent claim.
Response to Arguments
13. Rejections over Dowling. The rejection of claims 1-3, 5-6, 8-10, 12-13, 15-17, and 19-20 under 35 U.S.C. 102(a)(1) as anticipated by Dowling (US 6,760,833), the rejection of claims 4, 11, and 18 under 35 U.S.C. 103 over Dowling in view of Gove et al. (US 6,260,088), and the rejection of claims 7 and 14 under 35 U.S.C. 103 over Dowling in view of Bruner et al. (US 6,061,751) are withdrawn in view of the amendment and Applicant's arguments. See Response to Arguments below. Claims 17-18 are canceled, rendering their rejections moot.
Applicant's arguments (Response, pp. 2-4) that Dowling does not disclose a self-selecting bus decoder configured to "receive a memory mapping configuration to set up a range of memory addresses of the memory to be added to an integrated circuit" and to "determine that the memory address is mapped to the memory based on the memory address being included in the range of memory addresses," as now recited in independent claims 1, 8, and 15, have been fully considered and are persuasive. Dowling's CPU core and embedded-DRAM coprocessor are designed together to jointly implement a single processor (Dowling, Abstract), and the row-pointer passage previously relied upon (Dowling, col. 18) concerns maintaining active DRAM rows for sense-amp caching rather than determining whether a received address falls within a configured address range. Accordingly, the rejections based on Dowling are withdrawn.
14. However, upon further consideration and search necessitated by the amendment, new grounds of rejection are made under 35 U.S.C. 102(a)(1) and 103 in view of the PCI Local Bus Specification, Revision 2.2, and, independently, under the doctrine of nonstatutory double patenting over Applicant's own issued parent patents, as set forth below.
Conclusion
15. Claims 1-16 and 19-22 are rejected. Claims 17-18 are cancelled.
16. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Ball et al., US 2002/0138709 A1, teach a PCI memory address decoding; describes host writing each Base Address register with the allocated base address, a PCI device receiving a transaction whose address falls within its address range, and the device claiming the transaction by driving DEVSEL# low (¶¶ [0005], [0042], [0045]).
Williams, US 5,968,151, teaches a positive vs. subtractive decode; each PCI device is assigned an address range, performs its own address decoding, and positively claims the cycle by asserting DEVSEL# when it sees its address.
Shanley & Anderson, *PCI System Architecture*, 4th ed., MindShare Inc./Addison-Wesley (1999), teach the textbook treatment of PCI configuration, Base Address register programming, and target address decode.
Smith et al., US 2008/0291765 A1; Park et al., US 2006/0140047 A1, of record; array selection block mapping an input region to a physical location, and self-generated peripheral strobe using a peripheral device selection signal.
US 8,402,188; US 10,572,414; US 11,782,859; US 12,197,363 - Applicant's own family patents; considered for double patenting and not applied, as explained above.
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
