DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2004348788 (hereinafter JP788, relying on the most relevant portions of the attached PE2E English Machine Translation) and CN 115620785 (hereinafter CN785, relying on the most relevant portions of the attached PE2E English Machine Translation).
Regarding claim 1, JP788 discloses a memory system including a storage controller for transmitting a read command to a memory device including a plurality of planes [FIG.25, Abstract: a nonvolatile semiconductor memory device and can perform read and write having a control logic circuit generating read selection signals which select one plane for read out of a plurality of planes], the memory system comprising: a command generation circuit configured to generate a first read command signal including an address signal set for each of the plurality of planes or a second read command signal including an address signal applied collectively to the plurality of planes [Description, Abstract: a control logic circuit generating read selection signals which select one plane for read out of a plurality of planes, address selection circuit arranged at each plane, each address selecting circuit configured so as to receive read signals from the control logic circuits]; a command selection circuit configured to determine either the first read command signal or the second read command signal as the read command [FIG. 26, 27, Abstract: a control logic circuit generating read selection signals which select one plane for read out of a plurality of planes]; and a memory controller configured to transmit the determined read command to the memory device [Abstract: a nonvolatile semiconductor memory device and can perform read and write having a control logic circuit generating read selection signals which select one plane for read out of a plurality of planes],
JP788 does not explicitly disclose wherein the command generation circuit is configured to generate the first read command signal based on read levels for correction of the plurality of planes being different from each other.
CN785, however, discloses wherein the command generation circuit is configured to generate the first read command signal based on read levels for correction of the plurality of planes being different from each other [Description, FIG, 9A, 9B: receiving a first read command, read operation in a page is used on another plane to correct read levels of other pages and correcting the reading level of other pages of the first plane].
It would have been obvious to one of ordinary skill in the art to have the command generation circuit being configured to generate the first read command signal based on read levels for correction of the plurality of planes being different from each other in order to improve data reliability (Background).
Regarding claim 2, CN785 discloses the memory system of claim 1, wherein the command generation circuit is configured to generate the second read command signal based on a read level of a first plane among the plurality of planes [FIG. 9A, 9B, Description: additional read command used on another plane to correct read levels of other pages].
Regarding claim 3, CN785 discloses the memory system of claim 1, wherein the command generation circuit is configured to generate a first address signal based on a read level of a first plane among the plurality of planes and generate a second address signal based on a read level of a second plane among the plurality of planes [Description, Specific Implementation Section].
Regarding claim 4, JP788 discloses the memory system of claim 3, wherein the command generation circuit is configured to generate the first read command signal including the first address signal and the second address signal [Abstract].
Regarding claim 5, CN785 discloses the memory system of claim 1, comprising an analysis circuit configured to determine whether a deviation in read levels of the plurality of planes is equal to or greater than a preset standard [Description, Claim 5].
Regarding claim 6, CN785 discloses the memory system of claim 5, wherein the command selection circuit is configured to, based on determining, as a result of the determination of the analysis circuit, that the deviation in the read levels of the plurality of planes is equal to or greater than the preset standard, determine the first read command signal as the read command [Description, Claim 5].
Regarding claim 7, CN785 discloses the memory system of claim 1, comprising a buffer memory configured to store read levels of the plurality of planes [Claim 16].
Regarding claims 8 and 15, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claims 9 and 16, the rationale in the rejection of claim 2 is herein incorporated.
Regarding claims 10 and 17, the rationale in the rejection of claim 3 is herein incorporated.
Regarding claims 11 and 18, the rationale in the rejection of claim 4 is herein incorporated.
Regarding claims 12 and 19, the rationale in the rejection of claim 5 is herein incorporated.
Regarding claims 13 and 20, the rationale in the rejection of claim 6 is herein incorporated.
Regarding claim 14, the rationale in the rejection of claim 7 is herein incorporated.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. TW 202328917 to INFINEON (hereinafter INFINEON, relying on the most relevant portions of the attached PE2E English Machine Translation) discloses memory controller to read ECC data from ECC memory prior to a read command.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARDOCHEE CHERY whose telephone number is (571)272-4246. The examiner can normally be reached 900-500.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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