Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5, 7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2004/0117441) in view of Tian et al. (Adaptive GPU Cache Bypassing) and further in view of Taylor (US 2004/0181634).
Regarding claim 1, Liu discloses an apparatus for processing, comprising:
at least one first memory; and at least one processor coupled to the at least one first memory and, based at least in part on information stored in the at least one first memory [see paragraph 39; data-aware data flow manager (DADFM) may be implemented as processor executable instructions stored in memory], the at least one processor is configured to:
obtain an indication of data for a memory access process, wherein the data for the memory access process is associated with data processing [see paragraph 36; server sends request to store data];
determine whether space is available for the data and an address of the data in a cache; and
store, based on space being available in the cache, the data and the address of the data in the cache; or refrain from storing, based on space being unavailable in the cache, the data and the address of the data in the cache [see paragraphs 78 & 80; DADFM keeps track of how much cache space is free, and in response to a request to write data, it is determined if there is enough space in the cache to cache the data. If there is insufficient space, the cache is bypassed and the data is written directly to its intended target (another storage device), otherwise data may be written to cache normally. When caching data, an address of some sort (traditionally a tag) of the data must be stored with the data so that the data can be located on a subsequent access].
Liu discloses implementing the cache bypassing taught above in a CPU, but fails to disclose its use in a graphics processing system (GPU).
Tian discloses a GPU system that can bypass its cache for blocks that are unlikely to be referenced again before eviction [see abstract].
At the time of the invention it would have been obvious to a person of ordinary skill in the art to utilize the cache bypassing based on free space in the GPU environment of Tian.
The motivation for doing so would have been to improve efficiency and power consumption of a GPU [see Tian, Abstract].
Therefore, it would have been obvious to combine Tian with Liu for the benefits listed above, to obtain the invention as specified in claims 1-2, 5, 7, and 9-20.
Liu additionally discloses retrieving data from a cache in response to a read request [see paragraph 33], but does not expressly disclose receiving a request for the data and the address of the data; retrieving, based on the request and storage of the data and the address of the data in the cache, the data and the address of the data from the cache; or retrieving, based on the request and refrainment of the storage of the data and the address of the data in the cache, the data and the address of the data from at least one memory.
Taylor discloses a cache memory in which the data and tag (address) are co-located [see Fig. 2]. During a memory read operation, the microprocessor initially provides the memory read address to the system controller over a shared data/address bus to initiate a read from the main memory. The cache tag and associated cache data are thus retrieved sequentially if present in the cache [see paragraphs 41 & 73].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the tag (address) retrieval in addition to the data in the system of Liu and Tian.
The motivation for doing so would have been to confirm that the requested data is present in the cache [see Taylor, paragraph 73].
Therefore, it would have been obvious to combine Taylor with Liu and Tian for the benefits listed above, to obtain the invention as specified in claims 1-2, 5, 7, and 9-20.
Regarding claim 2, the combination discloses the apparatus of claim 1, wherein to determine whether there is space available for the data and the address of the data in the cache, the at least one processor is configured to:
determine whether a storage capacity of the cache is greater than or equal to a storage space for the data and the address of the data [see Liu, paragraphs 78 & 80; it is determined if there is enough free capacity in the cache to store the requested data].
Regarding claim 5, the combination discloses the apparatus of claim 2, wherein to determine whether the storage capacity of the cache is greater than or equal to the storage space for the data and the address of the data, the at least one processor is configured to:
compare the storage capacity of the cache with the storage space for the data and the address of the data; and determine whether the storage capacity of the cache is greater than or equal to the storage space for the data and the address of the data [see Liu, paragraphs 78 & 80; it is determined if there is enough free capacity in the cache to store the requested data; some type of comparison must be made to determine this].
Regarding claim 7, the combination discloses the apparatus of claim 2, wherein the cache is a clutch cache or a clutch buffer [see Liu, paragraph 40; a cache memory is disclosed; since the claims (and specification) fails to disclose what a clutch cache is or how it differs from any other type of cache memory, the cache of Liu, under BRI, is interpreted as a clutch cache], and wherein to determine whether the storage capacity of the cache is greater than or equal to the storage space for the data and the address of the data, the at least one processor is configured to:
determine whether the storage capacity of the clutch cache or the clutch buffer is
greater than or equal to the storage space for the data and the address of the data [see Liu, paragraphs 78 & 80; it is determined if there is enough free capacity in the cache to store the requested data].
Regarding claim 9, the combination discloses the apparatus of claim 8, wherein to retrieve the data and the address of the data from the cache, the at least one processor is configured to: read the data and the address of the data from the cache [see Liu, paragraph 33; in response to a read request, data is retrieved from cache]; and wherein to retrieve the data and the address of the data from the at least one memory, the at least one processor is configured to: read the data and the address of the data from the at least one memory [see Liu, paragraph 67; wherein a cache is set to only cache write data, reads must be serviced from storage other than cache].
Regarding claim 10, the combination discloses the apparatus of claim 9, wherein to read the data and the address of the data from the at least one memory, the at least one processor is configured to:
read the data and the address of the data from at least one random access memory (RAM) [see Tian, section 2; memory may be DRAM].
Regarding claim 11, the combination discloses the apparatus of claim 8, wherein to retrieve the data and the address of the data from the cache, or retrieve the data and the address of the data from the at least one memory, the at least one processor is configured to:
receive a request for the data and the address of the data; and retrieve the data and the address of the data from the cache or the at least one memory [see Tian, section 3.2; a tag associated with an access request is searched, and the data is retrieved from the cache or lower level memory based on a hit or miss of the tag in the cache].
Regarding claim 12, the combination discloses the apparatus of claim 11, wherein the at least one processor is further configured to:
determine whether the requested address of the data is identical to the retrieved
address of the data from the cache [see Tian, section 3.2; a tag associated with an access request is searched, and the data is retrieved from the cache or lower level memory based on a hit or miss of the tag in the cache].
Regarding claim 13, the combination discloses the apparatus of claim 12, wherein the at least one processor is further configured to:
output, based on the requested address of the data being identical to the retrieved address of the data from the cache, the retrieved data from the cache; or output, based on the requested address of the data not being identical to the retrieved address of the data from the cache, the retrieved data from the at least one memory [see Tian, section 3.2; a tag associated with an access request is searched, and the data is retrieved from the cache or lower level memory based on a hit or miss of the tag in the cache].
Regarding claim 14, the combination discloses the apparatus of claim 1, wherein to store, based on space being available in the cache, the data and the address of the data in the cache, the at least one processor is configured to:
store the data and the address of the data in the cache; and refrain from storing the data and the address of the data in at least one memory [see Liu, paragraph 115; write-back caching policy may be implemented; wherein data is stored only in cache and only written to storage when evicted from the cache],
wherein the at least one memory is at least one static random access memory (RAM)
(SRAM) or at least one dynamic RAM (DRAM) [see Tian, section 2; memory may be DRAM].
Regarding claim 15, the combination discloses the apparatus of claim 1, wherein to refrain from storing, based on space not being available in the cache, the data and the address of the data in the cache, the at least one processor is configured to:
refrain from storing the data and the address of the data in the cache; and
store the data and the address of the data in at least one memory [see Tian, section 3.2; if decision is to bypass cache, data is not stored in cache, but written to a lower level memory], wherein the at
least one memory is at least one static random access memory (RAM) (SRAM) or at least
one dynamic RAM (DRAM) [see Tian, section 2; memory may be DRAM].
Regarding claim 16, the combination discloses the apparatus of claim 1, wherein to store the data and the address of the data in the cache, the at least one processor is configured to: write the data and the address of the data in the cache; and
wherein to refrain from storing the data and the address of the data in the cache, the at least one processor is configured to: refrain from writing the data and the address of the data in the cache [see Liu, paragraph 78; when there is no available free space within cache, the cache is bypassed and data is not stored in cache].
Regarding claim 17, the combination discloses the apparatus of claim 1, wherein to obtain the indication of the data for the memory access process, the at least one processor is configured to:
receive the indication of the data for the memory access process from at least one other component at a graphics processing unit (GPU), a central processing unit (CPU), or a display processing unit (DPU), wherein the data for the memory access process is at least one of: graphics data, image data, display data, video data, processing data, instruction data, or data associated with an access pattern for a queue [see Tian, section 3.3; data access may come from a GPU and relate to accesses reflecting an access pattern].
Regarding claim 18, the combination discloses the apparatus of claim 1, wherein the at least one processor is further configured to:
output an indication of storage of the data and the address of the data in the cache
or refrainment of the storage of the data and the address of the data in the cache [see Liu, paragraph 36; DADFM informs server that data has been stored in storage in response to a write request].
Claims 19-20 recite similar claim limitations to claim 1 above, and the same citations and interpretations are used to reject claims 19-20.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Tian and Taylor, and further in view of Chan et al. (US 5,442,747).
Regarding claim 3, the combination of Liu and Tian and Taylor discloses the apparatus of claim 2 as discussed above.
The combination does not expressly disclose determining whether an available depth of the cache is greater than or equal to the storage space for the data and the address of the data.
Chan discloses a cache storage system in which a cache capacity may be determined with the use of the depth of a queue [see Col. 5,lines 55-67].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the depth counters of Chan in the system of Liu and Tian and Taylor.
The motivation for doing so would have been to determine if data should be retrieved from or stored in the cache [see Chan, Col. 5, lines 55-67].
Therefore, it would have been obvious to combine Chan with Liu and Tian and Taylor for the benefits listed above, to obtain the invention as specified in claim 3.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Tian and Taylor and further in view of Augustine (Finite State Machines).
Regarding claim 6, the combination of Liu and Tian and Taylor disclose the apparatus of claim 2 as discussed above, including determining in the cache, whether the storage capacity of the cache is greater than or equal to the storage space for the data and the address of the data [see above rejection of claim 2].
The combination does not expressly disclose the determining is performed using a finite state machine (FSM).
Augustine discloses the usage of a finite state machine (FSM) as a useful abstraction for sequential circuits [see article].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the FSM of Augustine in the system of Liu and Tian and Taylor.
The motivation for doing so would have been for the flexibility and low processor overheads FSMs provide [see Augustine, article].
Therefore, it would have been obvious to combine Augustine with Liu and Tian and Taylor for the benefits listed above, to obtain the invention as specified in claim 6.
Response to Arguments
Applicant’s arguments, filed 9/15/2026, with respect to the rejection(s) of claim(s) 1-2, 5 and 7-20 under Liu in view of Tian and Taylor have been fully considered and are not persuasive.
Applicants argue that “nowhere in Liu and Taylor is there any mention of receive a request for the data and the address of the data; and retrieve, based on the request and storage of the data and the address of the data in the cache, the data and the address of the data from the cache; or retrieve, based on the request and refrainment of the storage of the data and the address of the data in the cache, the data and the address of the data from at least one memory, as recited in claim 1”. Applicant argues with additional detail how Tian does not teach the above limitation. However, Tian was not relied upon for teaching the related pre-amended limitation. Taylor was a reference brought in to show that a cache memory in which the data and tag (address) are co-located [see Fig. 2]. During a memory read operation, the microprocessor initially provides the memory read address to the system controller over a shared data/address bus to initiate a read from the main memory [see paragraphs 41 & 73; this reads upon the new limitation of receiving a request for data and the address of the data]. The cache tag and associated cache data are thus retrieved sequentially if present in the cache [see paragraphs 41 & 73; this reads upon the new limitation of retrieve, based on the request and storage of the data and the address of the data in the cache, the data and the address of the data from the cache]. It would have been obvious to a person of ordinary skill in the art to utilize the tag (address) retrieval in addition to the data in the system of Liu and Tian to be able to confirm that the requested data is present in the cache [see Taylor, paragraph 73].
Therefore, the combination of Liu, Tian and Taylor disclose the new limitation of receive a request for the data and the address of the data; and retrieve, based on the request and storage of the data and the address of the data in the cache, the data and the address of the data from the cache; or retrieve, based on the request and refrainment of the storage of the data and the address of the data in the cache, the data and the address of the data from at least one memory, as recited in claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137
