DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1, 3-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chauvel et al. (US 2002/0069341), “Chauvel”, in view of Favor (US 2002/0078302).
2. As per claim 1, Chauvel discloses a first cache storage [a level one (L1) cache, abstract]; a first cache control circuit coupled to the first cache storage and configured to: receive a memory transaction [memory transactions for L1 caches 202 & 206, figure 2A]; and determine whether data associated with the memory transaction is stored in the first cache storage [determining an L1 cache miss, paragraph 90]; a second cache storage [a level two (L2) cache, abstract]; and a second cache control circuit coupled to the second cache storage and configured to: receive the memory transaction [memory transactions for L2 cache(s) 900, figure 4].
Chauvel does not disclose expressly a store queue coupled to a cache storage; and determining whether the data associated with a memory transaction is stored in either the cache storage or the store queue.
Favor discloses a store queue [a retry queue, abstract] coupled to a cache storage [a cache, abstract]; and determining whether the data associated with a memory transaction is stored in either the cache storage [cache hit, paragraph 20] or the store queue [cache miss, paragraph 22].
Chauvel and Favor are analogous art because they are from the same field of endeavor of caching.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Chauvel by including the retry queue as taught by Favor in figure 2.
The motivation for doing so would have been a “non-blocking” cache fill as expressly taught by Favor in the abstract.
3. As per claim 3, the cited prior arts disclose wherein: the first cache storage and the first cache control circuit are associated with a level one (L1) main cache [a level one (L1) cache, abstract, Chauvel]; and the second cache storage, the store queue, and the second cache control circuit are associated with a L1 victim cache [a TLB victim location, paragraph 37, Chauvel].
4. As per claim 4, the cited prior arts disclose a first cache system that includes the first cache storage [a level one (L1) cache, abstract, Chauvel], the first cache control circuit, the second cache storage [a level two (L2) cache, abstract, Chauvel], the store queue [a retry queue, abstract, Favor], and the second cache control circuit; and a second cache system coupled to the first cache system, wherein the first cache system is configured to provide the memory transaction to the second cache system based on the data not being stored in the first cache storage, the second cache storage, or the store queue [a level three (L3) cache system, paragraph 30, Chauvel].
5. As per claim 5, the cited prior arts disclose wherein: the first cache system is a level one (L1) cache system [a level one (L1) cache, abstract, Chauvel]; and the second cache system is a level two (L2) cache system [a level two (L2) cache, abstract, Chauvel].
6. As per claim 6, the cited prior arts disclose wherein: the memory transaction is a first memory transaction; the data is a first set of data; and the first cache control circuit is configured to, based on a second memory transaction, evict a second set of data from the first cache storage for storing in the second cache storage [cache destaging is inherent in multi-level cache systems, abstract, Chauvel].
7. As per claim 7, the cited prior arts disclose wherein the first cache control circuit is configured to evict the second set of data from the first cache storage for storing in the second cache storage when the second set of data is clean [“valid clean”, paragraph 14, Favor].
8. As per claim 8, the cited prior arts disclose wherein: the first cache storage is associated with a first type of associativity; and the second cache storage is associated with a second type of associativity that is different from the first type [a cache associativity as a design choice, paragraph 51, Chauvel].
9. As per claim 9, the cited prior arts disclose wherein: the first cache storage has a direct-mapped associativity; and the second cache storage is fully associative [a cache associativity as a design choice, paragraph 51, Chauvel].
10. As per claim 10, the cited prior arts disclose wherein the second cache control circuit is configured to, based on the data being stored in either the second cache storage or the store queue, cause the data to be stored in the first cache storage [Data needed by CPU is necessarily promoted to L1 cache, abstract, Chauvel].
11. As per claim 11, Chauvel discloses wherein the second cache control circuit is configured to retrieve the data from the store queue [abstract, Favor].
12. As per claim 12, Chauvel discloses a processor core [System Host 120, figure 1]; and a cache system that includes: an interface [Traffic Control 110, figure 1] coupled to the processor core; a first cache storage [a level one (L1) cache, abstract]; a first cache control circuit coupled to the first cache storage and the interface and configured to: receive a memory transaction from the processor core [memory transactions for L1 caches 202 & 206, figure 2A]; and determine whether data associated with the memory transaction is stored in the first cache storage [determining an L1 cache miss, paragraph 90]; a second cache storage [a level two (L2) cache, abstract]; and a second cache control circuit coupled to the second cache storage and the interface and configured to: receive the memory transaction [memory transactions for L2 cache(s) 900, figure 4].
Chauvel does not disclose expressly a store queue coupled to a cache storage; and determining whether the data associated with a memory transaction is stored in either the cache storage or the store queue.
Favor discloses a store queue [a retry queue, abstract] coupled to a cache storage [a cache, abstract]; and determining whether the data associated with a memory transaction is stored in either the cache storage [cache hit, paragraph 20] or the store queue [cache miss, paragraph 22].
Chauvel and Favor are analogous art because they are from the same field of endeavor of caching.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Chauvel by including the retry queue as taught by Favor in figure 2.
The motivation for doing so would have been a “non-blocking” cache fill as expressly taught by Favor in the abstract.
13. As per claim 13, Chauvel discloses receiving, by a first memory control circuit and a second memory control circuit, a memory transaction [memory transactions for L1 caches 202 & 206, figure 2A] [memory transactions for L2 cache(s) 900, figure 4]; determining, by the first memory control circuit, whether data associated with the memory transaction is stored in a first cache storage [determining an L1 cache miss, paragraph 90].
Chauvel does not disclose expressly determining whether the data associated with a memory transaction is stored in a cache storage or a store queue coupled to the cache storage.
Favor discloses determining whether the data associated with a memory transaction is stored in a cache storage [cache hit, paragraph 20] or a store queue coupled to the cache storage [cache miss resulting in a retry queue access, paragraph 22, abstract].
Chauvel and Favor are analogous art because they are from the same field of endeavor of caching.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Chauvel by including the retry queue as taught by Favor in figure 2.
The motivation for doing so would have been a “non-blocking” cache fill as expressly taught by Favor in the abstract.
14. As per claim 15, the cited prior arts wherein: the first cache storage and the first memory control circuit are associated with a level one (L1) main cache [a level one (L1) cache, abstract, Chauvel]; and the second cache storage, the store queue, and the second memory control circuit are associated with a L1 victim cache [a TLB victim location, paragraph 37, Chauvel].
15. As per claim 16, the cited prior arts disclose wherein: the memory transaction is a first memory transaction; the data is a first set of data; and the method further comprises, based on a second memory transaction, evicting, using the first memory control circuit, a second set of data from the first cache storage to the second cache storage [cache destaging is inherent in multi-level cache systems, abstract, Chauvel].
16. As per claim 17, the cited prior arts disclose wherein: the first cache storage is associated with a first type of associativity; and the second cache storage is associated with a second type of associativity that is different from the first type [a cache associativity as a design choice, paragraph 51, Chauvel].
17. As per claim 18, the cited prior arts disclose wherein: the first cache storage has a direct-mapped associativity; and the second cache storage is fully associative [a cache associativity as a design choice, paragraph 51, Chauvel].
18. As per claim 19, the cited prior arts disclose based on the data being stored in either the second cache storage or the store queue, causing the data to be stored in the first cache storage [Data needed by CPU is necessarily promoted to L1 cache, abstract, Chauvel].
19. As per claim 20, the cited prior arts disclose retrieving the data from the store queue [abstract, Favor].
Conclusion
A. Allowable Subject Matter
Claims 2 and 14 are objected to.
The closest prior art of record, “Chauvel” teaches a multi-level cache system.
The primary reasons for allowance of claim 2 in the instant application is the combination with the inclusion in these claims that “wherein the second cache control circuit is configured to determine whether the data is stored in either the second cache storage or the store queue concurrent with the first cache control circuit determining whether the data is stored in the first cache storage”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 14 in the instant application is the combination with the inclusion in these claims that “wherein the determining by the first memory control circuit is concurrent with the determining by the second memory control circuit”. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP.
B. Claims Rejected
Claims 1, 3-13, and 15-20 are rejected.
C. Direction for Future Remarks
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/JAE U YU/Primary Examiner, Art Unit 2138