Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant: Information Disclosure Statement (IDS) filed on 2/20/25 was considered.
Claims 1-20 are presented for examination.
Drawings
The drawings are objected to because of the following minor informalities:
Figures 1, 2, 3, 7 and 10 should be designated by a legend such as --Prior Art—
because only that which is old is illustrated. See MPEP ' 608.02(g).
Correction is required.
Claim Rejections - 35 USC ' 112
Claim 20 is rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
There is insufficient antecedent basis for the limitations.
Claim 20 depends on claim 11, recites on line 2, the limitation of “the third dies (i.e. plurals of dies) assembly”, whereas claim 11 recites a third die (i.e. single die). Therefore, examiner cannot determine if the third dies in claim 20 is the same as that of the third die in claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by St. Amand et al (US 7071568).
With regard to claim 1 and 11, St. Amand discloses a multi-die memory chip (col. 1, line 19-25 discloses multi-die memory chips), comprising, a substrate (fig. 1A, substrate 20); a first die assembly (fig. 1A, D1) mounted above the substrate (fig. 1A, substrate 20); a spacer (fig. 1A, adhesive layer 27) mounted above the substrate (fig. 1A, substrate 20) (col.5, L61-62); a second die assembly (fig. 1A, D2) mounted above the first die assembly (fig. 1A, D1) and the spacer (fig. 2A, spacer S1A) such that a bottom on the second die assembly (fig.1A, bottom of D2) at least partially faces a top of the first die assembly (fig.1A, D1) and at least partially faces a top of the spacer (fig. 1A, S1A); and an electrical pathway extending between a top of the substrate and a bottom of the second die assembly (fig..1A, top of substrate 20 and the bottom of D2).
With regard to claim 2 and 12, St. Amand discloses wherein the spacer is ceramic (col. 33, L50-56).
With regard to claim 3 and 13, St. Amand discloses wherein the first die assembly includes a single die (col. 5, L1-15).
With regard to claim 4 and 14, St. Amand discloses wherein the first die assembly includes a first plurality of dies (col. 10, L6-18).
With regard to claim 6 and 16, St. Amand discloses wherein the second die assembly (fig. 1A, D2) includes a single die (col. 5, L1-3).
With regard to claim 7 and 17, St. Amand discloses wherein the second die assembly includes a second plurality of dies (col. 10, L6-17).
With regard to claim 8 and 18, St. Amand discloses wherein the second plurality of dies (col. 10, L6-7) are stacked and interconnected using Through Silicon Vias connected by solder balls (col. 2, L1-14).
With regard to claim 9, 19 and 20, St. Amand discloses wherein the electrical pathway extends in a gap between the spacer and the first die assembly (col. 8, L8-27).
With regard to claim 10, St. Amand discloses wherein the spacer (fig. 1A, S1A) physically supports the second die assembly (fig. 1A, D2) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 15 are rejected under 35 U.S.C. 103(a) as being unpatentable over St. Amand et al (US Pat. No. 7,071,568) in view of Gillingham (US Pat. No. 8,711,573)
With regard to claim 5 and 15, St Amand, as applied in prior rejection, disclosed all claimed subject matter except wherein the first plurality of dies are stacked and interconnected using Through Silicon Vias connected by solder balls. However, Gillingham teaches stacked semiconductor die electrically interconnected using Through Silicon Vias and solder balls, wherein the TSVs extend through the silicon substrate of respective dies and are connected through a line conductive pads and solder ball interconnections. Gillingham further teaches that this vertical interconnection arrangement can be repeated to interconnect multiple stack memory chips, Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the stack dies D1-D3 of St. Amand to incorporate the TSV and solder-ball interconnection arrangement as taught by Gillingham. Such modification would have been to provide higher density vertical electrical interconnection between the stack memory dies, reduce reliance on the peripheral wiring bonding, and accommodate additional electrical connection within the stack semiconductor package.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Frans (2013/0336039) discloses multiple semiconductor memory dies arranged in a vertical stack and electrically interconnected using through-die vias, including through-silicon vias, with conductive interconnects between adjacent dies. However, Frans does not disclose the claimed arrangement in which an upper die assembly is positioned over both a lower die assembly and a separate spacer, with the bottom of the upper die assembly at least partially facing both structures. Frans also does not disclose the claimed electrical pathway extending in the gap associated with that spacer arrangement.
When responding to the office action, Applicants’ are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) days from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha, whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825
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