Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 27 – 30 and 37 - 40 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Pat. No. 10313099), hereinafter referred to as Li in view of Xu et al. (US Pub. No. 20210028788), hereinafter referred to as Xu.
As to claim 27, Li discloses a multi-lane integrated circuit transceiver device (multi-lane coherent transceiver, 200, Fig. 2) comprising a first plurality of parallel transceivers (first set of lanes LN1-LN2 operating in parallel, LN1-LNn, Fig. 2) each transceiver in the first plurality of transceivers including a transmit block/receive block pair (transceiver lanes providing transmit and receive functionality, LN1-LNn, Fig. 2), a second plurality of parallel transceivers (second set of lanes LN2-LN4 operating in parallel, LN1-LNn, Fig. 2) each transceiver in the second plurality of transceivers including a transmit block/receive block pair (transceiver lanes providing transmit and receive functionality, LN1-LNn, Fig. 2), and digital clock generation and distribution circuitry (clock generation circuit including PLL and frequency divider, Fig. 2); and digital control circuitry (reset synchronization circuit, 210, Fig. 2, Li).
Xu discloses, what Li lacks, a first integrated circuit die (first circuit die, 210, Fig. 2A; 310, Fig. 3A) and a second integrated circuit die (second circuit die, 230, Fig. 2A; 330, Fig. 3A);
configured to distribute a digital clock signal (clock signal source, Fig. 2A) to each of the first integrated circuit die and the second integrated circuit die (clock signal source circuit distributing timing signals to multiple circuit dies, 2 tier stacked die, Figs. 2A ) with minimized clock skew (minimizing clock skew between the first integrated circuit die and the second integrated circuit die using a hierarchical timing signal distribution network, PLL 202, buffers 212-218, Figs. 2A and 2B); including a digital loop circuit (PLL clock circuit, 202, Figs. 2A and 3A) to lock output of the clock generation circuitry to a baseline clock (PLL generating and locking distributed timing signals to a reference clock source, 202, Figs. 2A and 3A).
Li and Xu are analogous art because they are from the same field of endeavor, namely high-speed multi-lane integrated circuit transceivers and clock generation/distribution for synchronized operation of integrated circuit devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Li and Xu before him or her, to modify the multi-lane coherent transceiver of Li to include the multi-die clock generation and hierarchical timing signal distribution circuitry of Xu.
The suggestion/motivation for doing so would have been to improve synchronization in a multi-die implementation of Li's transceiver.
Therefore, it would have been obvious to combine Xu with Li to obtain the invention as specified in the instant claim.
As to claim 28, Li in view of Xu discloses the multi-lane integrated circuit transceiver device of claim 27, wherein the digital loop circuit comprises a frequency-locked loop (PLL clock circuit generating a synchronized clock, 202, Figs. 2A and 3A, Xu) to lock output of the clock generation circuitry to the baseline clock (PLL generating and locking distributed timing signals to a reference clock source, 202, Figs. 2A and 3A, Xu).
As to claim 29, Li in view of Xu discloses the multi-lane integrated circuit transceiver device of claim 27, wherein the first integrated circuit die is a primary integrated circuit die (first circuit die, 210, Fig. 2A, Xu) comprising no more than N transmit block/receive block pairs configured to form a first group of transmit block/receive block pairs (parallel transceiver lanes, LN1-LNn, Fig. 2, Li, this part is not expressly disclosed as no more than N transmit block/receive block pairs), the second integrated circuit die is a secondary integrated circuit die (second circuit die, 230, Fig. 2A, Xu) comprising no more than N transmit block/receive block pairs configured to form a second group of transmit block/receive block pairs (parallel transceiver lanes, LN1-LNn, Fig. 2, Li), the digital clock generation and distribution circuitry comprises respective clock generation circuitry on each of the first integrated circuit die and the second integrated circuit die (PLL clock circuitry on circuit dies, 202; local PLL, Figs. 2A and 3A, Xu) and distribution circuitry configured to distribute a digital clock signal output by respective clock generation circuitry on one of the first integrated circuit die and the second integrated circuit die for use as the baseline clock by the respective digital clock generation circuitry on each of the first integrated circuit die and the second integrated circuit die (clock source circuit distributing timing signals between multiple circuit dies, Figs. 2A, 3A, and 3B, Xu).
As to claim 30, Li in view of Xu discloses the multi-lane integrated circuit transceiver device of claim 29, wherein the digital clock distribution circuitry further comprises buffer circuitry on the first integrated circuit die and the second integrated circuit die (clock buffers, 214, 216, 218, Figs. 2A and 2B, Xu) configured to transmit the digital clock signal output by the one respective receive block off of the first integrated circuit die and onto both the first integrated circuit die and the second integrated circuit die (hierarchical timing signal distribution network distributing clock signals between circuit dies, Figs. 2A and 2B, Xu; it would have been an obvious matter of design choice to source the distributed clock from any suitable circuit block, including a receive block, because the particular source of the distributed clock merely represents a predictable design implementation while performing the same clock distribution function) and the first integrated circuit die and the second integrated circuit die together form a single 2N-lane transceiver (it would have been an obvious matter of design choice to configure the combined first and second N-lane integrated circuit dies as a single 2N-lane transceiver because combining two N-lane transceiver dies predictably yields a transceiver having an aggregate of 2N lanes while performing the same intended communication function).
Claims 37 - 40 recite the corresponding limitation of claims 27 - 30. Therefore, they are rejected accordingly.
Allowable Subject Matter
Claims 31 – 36 and 41 – 46 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Litichever et al. (US Pub. No. 20180225230) A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights