DETAILED ACTION
The instant application having Application No. 18/987,152 has claims 1-20 pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made of applicant’s claim for foreign priority based on an application filed in REPUBLIC OF KOREA on 12/26/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2024 is being considered by the examiner.
Claim Language
Claims 8, 14, 15, and 20 recite limitations which, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger.
The limitations in the claims following “when” (for example, in claim 8: “when the set values of the flags are the first value”) are not positively recited in the claims, as the limitations, as claimed, are conditionally executed without accounting for the possibility of the condition falling only on one of the recited conditions. The method may never be required to execute the conditions because “when” is a temporal conditional precedent that may never be reached within the scope of the claim under the broadest reasonable interpretation. The examiner recommends amending the instances of limitations reliant on the language reciting “when” to instead recite “in response to” (for example, in claim 8: “deactivating a memory protection unit (MPU) configured to monitor access to the memory[[,]] in response to [[when]] the set values of the flags [[are]] corresponding to the first value”).
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding “The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim”); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites changing set values of at least one flag and the QM module modifying the change to the ASIL module. The intended scope of the QM module modifying said change to the ASIL module is unclear. Specifically, while ‘modify the change’ portion may be interpreted to comprise further changing the flag, the intended meaning/operation of said modifying being directed to the ASIL module is unclear. If the claim was intended to be directed towards notifying the change(s) to the ASIL module by the QM module, the examiner recommends amending the instance of ‘modify’ to ‘notify’.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. (JP 2017016410 A) in view of Zbiciak et al. (US 20120191933 A1) in view of Altman et al. (US 20130305006 A1) in view of Lasko et al. (US 20190196984 A1) in view of Zhang et al. (US 20250173178 A1).
As per claim 1,
1. An electronic device comprising: a memory configured to be partitioned into an automotive safety integrity level (ASIL) area and a quality management (QM) area; [Kubota teaches a system operating in one of two modes comprising supervisor/user modes with different access rights and a memory divided into QM and ASIL areas, the ASIL area being accessible by supervisor mode tasks having safety levels such as ASIL-D but prohibited from being accessed by user mode tasks having safety levels such as QM, whereas the QM area is accessible by both supervisor mode (e.g. ASIL-D) and user mode (e.g. QM) tasks (please see the attached translated foreign reference for Kubota (JP 2017016410 A): para. 13-14, 38; fig. 1 and associated paragraphs); where a memory management unit (MPU) may be used to realize the access restrictions to the ASIL area (monitoring) (para. 14)] a QM module configured to: perform memory access of writing or reading data in certain areas of the ASIL area; [Where Kubota teaches prohibiting QM tasks from accessing ASIL area using a memory management unit (MPU) as shown above, Kubota also discloses that a setting may be configured to permit some access and further discloses that permission/prohibition may be set for each area for each type of access (para. 14), where it would have been obvious for one of ordinary skill in the arts, provided with Kubota’s disclosure, directed towards generally prohibiting access to ASIL area by QM tasks using a memory management unit as well as providing a setting for specifying permission/prohibition for each type of access, to provide for a combination where the memory management unit may be configured with a setting to allow access to ASIL area by at least some or all access types via QM tasks in order to provide for greater flexibility in data processing.]
Kubota does not explicitly disclose, but Zbiciak discloses:
a QM module [Kubota as shown above teaches tasks and areas pertaining to supervisor mode and user mode; Zbiciak similarly discloses supervisor mode and user mode as well as respective supervisor code and user code to be ran on a CPU (para. 54-55)] an ASIL module configured to: deactivate a memory protection unit (MPU) configured to monitor access to the memory when the at least one flag is set to the first value; and activate the MPU or maintain a state of the MPU when the at least one flag is set to the second value. [Kubota as shown above teaches supervisor mode associated with ASIL area and a memory management unit (MPU) being configured to prohibit and/or allow access by user/QM tasks to ASIL area; Zbiciak teaches a supervisor being granted access to memory protection configurations and capable of changing memory protection configurations (para. 55, 72), where it would have been obvious for one of ordinary skill in the arts, provided with Kubota’s disclosure, directed towards a memory management unit restricting accesses (monitoring) to ASIL area by QM tasks under user mode but capable of being set to allow the accesses, with Zbiciak’s disclosures, directed towards a supervisor capable of modifying memory protection configurations, to provide for a combination where a supervisor (ASIL module) may be configured to activate or deactivate the memory restriction via memory management unit on the ASIL area from a user/QM module in order to provide for greater flexibility in memory protection management)]
Kubota and Zbiciak are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota and Zbiciak, to modify the disclosures by Kubota to include disclosures by Zbiciak since they both teach data storage and protection, wherein Zbiciak is directed towards improved flexibility in memory management (para. 3-10). Therefore, it would be applying a known technique (system comprising supervisor/user codes corresponding to supervisor/user modes, the supervisor mode being capable of modifying memory protection configurations) to a known device (system comprising supervisor/user modes and memory management module, the memory management module may be configured to provide access rights, for the user mode, to ASIL area assigned to the supervisor mode) ready for improvement to yield predictable results (system comprising supervisor/user modes executed in correspondence with supervisor/user codes (modules) and memory management module, the memory management module being configurable to provide access rights, by the user module, to ASIL area assigned to the supervisor module, where said configuration to the memory management module may be provided by the supervisor module in order to provide for greater flexibility in assigning memory access permissions). MPEP 2143
Kubota in view of Zbiciak does not explicitly disclose, but Altman discloses:
at least one flag;; set the at least one flag to a first value;; an ASIL module configured to: deactivate a memory protection unit (MPU) configured to monitor access to the memory when the at least one flag is set to the first value; and activate the MPU or maintain a state of the MPU when the at least one flag is set to the second value.
[Kubota in view of Zbiciak as shown above teaches a user/QM module having its access restricted to a QM area but the restriction to ASIL area potentially being deactivated by a supervisor/ASIL module; Altman similarly discloses an application, executed in a limited privilege memory domain, requesting access to domain managed by a memory device and potentially being granted access by the memory device (para. 12, 61-65; figs. 3-4 and associated paragraphs), the application communicating the request by writing to a location (e.g. doorbell) in its (application) memory space to alert the memory device of an access request to a region of the device, by having the write to said location being reflected on a second location managed by the memory device (para. 61-67, 48); it would have been obvious for one of ordinary skill in the arts, provided with disclosures by Kubota in view of Zbiciak, directed towards a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module, and disclosures by Altman, directed towards an application belong to a limited privilege domain being given access to a memory device region by a memory device after indicating access request on a doorbell on the application’s limited privilege domain, to provide for a combination where a user/QM module may request access to a region of ASIL area by indicating access request on a doorbell to alert the supervisor/ASIL module. Doing so would provide for improved flexibility in managing restriction of the ASIL area by providing a low-overhead means for user/QM module to initiate access request]
[Where Kubota in view of Zbiciak in view of Altman as shown above teaches an user/QM module requesting access to a region of ASIL area by using a doorbell in the QM area, it does not explicitly disclose a doorbell comprising a flag; Lasko teaches a first and a second memory, the first memory having regions which may be separately integrity protected, wherein the second memory comprises bits (flags) which may be used to enable/disable integrity protection on the respective regions of the first memory (abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph), where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Kubota in view of Zbiciak in view of Altman, directed towards a user/QM module writing to a doorbell in the QM area for communicating request to access a supervisor/ASIL region, and the disclosures by Laskos, directed towards bit values of a first memory indicating whether a corresponding region of a second memory should be protected, to provide for a combination where the QM area doorbell may comprise bits that may be set by the user/QM module to signal granting or denying access to the corresponding ASIL region by the supervisor/ASIL in order to provide for improved simplicity in conveying access requests]
Kubota, Zbiciak, and Altman are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak and Altman, to modify the disclosures by Kubota in view of Zbiciak to include disclosures by Altman since they both teach data storage and protection, wherein Altman is directed towards improved performance in association with access management (para. 4-5). Therefore, it would be applying a known technique (an application communicating access request to a memory region of a device by writing to a location within a memory area assigned to the application) to a known device (a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module generally having access restricted to QM area being given access to a region of ASIL area by a supervisor/ASIL module, the user/QM module communicating a request for access to the region by writing to a location within the QM area; doing so would provide for greater simplification in communicating access requests between different modules). MPEP 2143
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
Kubota in view of Zbiciak in view of Altman in view of Lasko does not explicitly disclose, but Zhang discloses:
and set the at least one flag to a second value after having performed the memory access; and [Kubota in view of Zbiciak in view of Altman in view of Lasko as shown above teaches user/QM module communicating access request, for an ASIL region, to a supervisor/ASIL module by setting a bit in the QM area; it does not explicitly disclose, but Zhang discloses a first node obtaining a write lock corresponding to a write object on second, primary node, performing update to the corresponding write object, and sending a transaction completion notification to an upper-layer application prior to sending a write lock release message to the second node (para. 29, 177-178, 195-203; figs. 4, 6, 7A-7C and associated paragraphs); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Kubota in view of Zbiciak in view of Altman in view of Laskos providing for a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module, and disclosures by Zhang, directed towards a node obtaining a write lock for accessing an object in a primary node and releasing the write lock by communicating a write lock release message to the primary node after sending a transaction completion message to a upper-layer application, to provide for a combination where the user/QM module may similarly communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region]
Kubota, Zbiciak, Altman, Lasko, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman in view of Lasko and Zhang, to modify the disclosures by Kubota in view of Zbiciak in view of Altman in view of Lasko to include disclosures by Zhang since they both teach data storage and protection, wherein Zhang is directed towards transaction processing efficiency (para. 3-6). Therefore, it would be applying a known technique (a first node receiving a lock for accessing data of a second node, the first node sending a transaction completion message to an upper-layer application prior to communicating a write lock release message to the second node) to a known device (a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module modifying a bit to communicate access request to a region managed by a supervisor/ASIL module, where the user/QM module may communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region). MPEP 2143
As per claim 2, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 1 as shown above and further teaches:
2. The electronic device of claim 1, wherein the MPU is configured to generate, in a state of being activated, an exception when the QM module accesses the ASIL area. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang discloses a memory protection hardware which, upon detecting an invalid access, generates an exception (Zbiciak: para. 146)]
Kubota and Zbiciak are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota and Zbiciak, to modify the disclosures by Kubota to include disclosures by Zbiciak since they both teach data storage and protection, wherein Zbiciak is directed towards improved flexibility in memory management (para. 3-10). Therefore, it would be applying a known technique (system comprising supervisor/user codes corresponding to supervisor/user modes, the supervisor mode being capable of modifying memory protection configurations) to a known device (system comprising supervisor/user modes and memory management module, the memory management module may be configured to provide access rights, for the user mode, to ASIL area assigned to the supervisor mode) ready for improvement to yield predictable results (system comprising supervisor/user modes executed in correspondence with supervisor/user codes (modules) and memory management module, the memory management module being configurable to provide access rights, by the user module, to ASIL area assigned to the supervisor module, where said configuration to the memory management module may be provided by the supervisor module in order to provide for greater flexibility in assigning memory access permissions). MPEP 2143
As per claim 3, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 1 as shown above and further teaches:
3. The electronic device of claim 1, wherein the at least one flag includes multiple flags, wherein, when all the multiple flags are set to the first value, the ASIL module is configured to deactivate the MPU, and wherein, when at least one of the multiple flags is set to the second value, the ASIL module is configured to activate the MPU. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a plurality of bits corresponding to protection status of respective regions of the area (see claim 1 above; Lasko: abstract; para. 24; fig. 2A and associated paragraph), where having all the bits to set to remove access restrictions to all the regions may correspond to deactivating the memory management unit, and having at least one flag set to maintain access restriction on at least one region may correspond to activating the memory management unit.]
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 4, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 3 as shown above and further teaches:
4. The electronic device of claim 3, wherein the multiple flags comprise a first flag and a second flag, and wherein the QM module is configured to access the first flag and the second flag, which are dispersed, at different times to set the first flag and the second flag to the first value. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above (see claim 1 above; Lasko: abstract; para. 24; fig. 2A and associated paragraph) indicates bits being on respective locations (dispersed) (see fig. 2A) and does not require all the bits to be set to the same value (para. 24), where, therefore, the bits may necessarily be set/reset at different times.]
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 5, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 1 as shown above and further teaches:
5. The electronic device of claim 1, wherein the ASIL module is configured to access the ASIL area and the QM area. [Kubota as shown above shows an both the ASIL area and QM area being accessible by ASIL tasks (para. 13-14, 38; fig. 1 and associated paragraphs)]
As per claim 6, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 1 as shown above and further teaches:
6. The electronic device of claim 1, wherein the at least one flag includes multiple flags, [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang shows a plurality of bits (Lasko: para. 24)] and when changing set values of the multiple flags, the QM module is configured to modify the change to the ASIL module. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang shows the supervisor/ASIL module being alerted of an indication for access request (doorbell) on the QM area (see claim 1 above; see Altman: para. 48, 60-67 on the doorbell write being reflected in another location managed by the memory device)]
Kubota, Zbiciak, and Altman are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak and Altman, to modify the disclosures by Kubota in view of Zbiciak to include disclosures by Altman since they both teach data storage and protection, wherein Altman is directed towards improved performance in association with access management (para. 4-5). Therefore, it would be applying a known technique (an application communicating access request to a memory region of a device by writing to a location within a memory area assigned to the application) to a known device (a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module generally having access restricted to QM area being given access to a region of ASIL area by a supervisor/ASIL module, the user/QM module communicating a request for access to the region by writing to a location within the QM area; doing so would provide for greater simplification in communicating access requests between different modules). MPEP 2143
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 7, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 1 as shown above and further teaches:
7. The electronic device of claim 1, wherein access of the QM module to the ASIL area is limited to the certain areas of the ASIL area. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches respective bits in QM area associated with access to corresponding regions in ASIL area (see claim 1 above; Lasko: (abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph); the examiner also respectively notes that the claim’s recitation of the certain areas of the ASIL area may be interpreted as any or all areas of the ASIL area, as the claim does not specify which portions of ASIL areas are to be included or precluded from said certain areas.]
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 8,
8. A method for protecting an automotive safety integrity level (ASIL) memory area, the method comprising:; wherein the QM module is accessible to a QM area of a memory;; wherein the ASIL module is accessible to an ASIL area of the memory;; [Kubota teaches a system operating in one of two modes comprising supervisor/user modes with different access rights and a memory divided into QM and ASIL areas, the ASIL area being accessible by supervisor mode tasks having safety levels such as ASIL-D but prohibited from being accessed by user mode tasks having safety levels such as QM, whereas the QM area is accessible by both supervisor mode (e.g. ASIL-D) and user mode (e.g. QM) tasks (please see the attached translated foreign reference for Kubota (JP 2017016410 A): para. 13-14, 38; fig. 1 and associated paragraphs); where a memory management unit (MPU) may be used to realize the access restrictions to the ASIL area (monitoring) (para. 14)] performing memory access, wherein in the memory, the QM module accesses the ASIL area;; [Where Kubota teaches prohibiting QM tasks from accessing ASIL area using a memory management unit (MPU) as shown above, Kubota also discloses that a setting may be configured to permit some access and further discloses that permission/prohibition may be set for each area for each type of access (para. 14), where it would have been obvious for one of ordinary skill in the arts, provided with Kubota’s disclosure, directed towards generally prohibiting access to ASIL area by QM tasks using a memory management unit as well as providing a setting for specifying permission/prohibition for each type of access, to provide for a combination where the memory management unit may be configured with a setting to allow access to ASIL area by at least some or all access types via QM tasks in order to provide for greater flexibility in data processing.]
Kubota does not explicitly disclose, but Zbiciak discloses:
module [Kubota as shown above teaches tasks and areas pertaining to supervisor mode and user mode; Zbiciak similarly discloses supervisor mode and user mode as well as respective supervisor code and user code to be ran on a CPU (para. 54-55)] and activating the MPU by the ASIL module. [Kubota as shown above teaches supervisor mode associated with ASIL area and a memory management unit (MPU) being configured to prohibit and/or allow access by user/QM tasks to ASIL area; Zbiciak teaches a supervisor being granted access to memory protection configurations and capable of changing memory protection configurations (para. 55, 72), where it would have been obvious for one of ordinary skill in the arts, provided with Kubota’s disclosure, directed towards a memory management unit restricting accesses (monitoring) to ASIL area by QM tasks under user mode but capable of being set to allow the accesses, with Zbiciak’s disclosures, directed towards a supervisor capable of modifying memory protection configurations, to provide for a combination where a supervisor (ASIL module) may be configured to activate or deactivate the memory restriction via memory management unit on the ASIL area from a user/QM module in order to provide for greater flexibility in memory protection management)]
Kubota and Zbiciak are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota and Zbiciak, to modify the disclosures by Kubota to include disclosures by Zbiciak since they both teach data storage and protection, wherein Zbiciak is directed towards improved flexibility in memory management (para. 3-10). Therefore, it would be applying a known technique (system comprising supervisor/user codes corresponding to supervisor/user modes, the supervisor mode being capable of modifying memory protection configurations) to a known device (system comprising supervisor/user modes and memory management module, the memory management module may be configured to provide access rights, for the user mode, to ASIL area assigned to the supervisor mode) ready for improvement to yield predictable results (system comprising supervisor/user modes executed in correspondence with supervisor/user codes (modules) and memory management module, the memory management module being configurable to provide access rights, by the user module, to ASIL area assigned to the supervisor module, where said configuration to the memory management module may be provided by the supervisor module in order to provide for greater flexibility in assigning memory access permissions). MPEP 2143
Kubota in view of Zbiciak does not explicitly disclose, but Altman discloses:
setting flags to a first value by a quality management (QM) module,; checking set values of the flags by an ASIL module,; deactivating a memory protection unit (MPU) configured to monitor access to the memory, when the set values of the flags are the first value;
[Kubota in view of Zbiciak as shown above teaches a user/QM module having its access restricted to a QM area but the restriction to ASIL area potentially being deactivated by a supervisor/ASIL module; Altman similarly discloses an application, executed in a limited privilege memory domain, requesting access to domain managed by a memory device and potentially being granted access by the memory device (para. 12, 61-65; figs. 3-4 and associated paragraphs), the application communicating the request by writing to a location (e.g. doorbell) in its (application) memory space to alert the memory device of an access request to a region of the device by having the write to said location being reflected on a second location managed by the memory device (para. 61-67, 48); it would have been obvious for one of ordinary skill in the arts, provided with disclosures by Kubota in view of Zbiciak, directed towards a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module, and disclosures by Altman, directed towards an application belong to a limited privilege domain being given access to a memory device region by a memory device after indicating access request on a doorbell on the application’s limited privilege domain which is reflected on a location managed by the memory device to alert the memory device, to provide for a combination where a user/QM module may request access to a region of ASIL area by indicating access request on a doorbell which is reflected on a location in the ASIL area to alert the supervisor/ASIL module. Doing so would provide for improved flexibility in managing restriction of the ASIL area by providing a low-overhead means for user/QM module to initiate access request]
[Where Kubota in view of Zbiciak in view of Altman as shown above teaches an user/QM module requesting access to a region of ASIL area by using a doorbell in the QM area, the doorbell being reflected on the ASIL area to alert the supervisor/ASIL module, it does not explicitly disclose a doorbell comprising a flag; Lasko teaches a first and a second memory, the first memory having regions which may be separately integrity protected, wherein the second memory comprises bits (flags) which may be used to enable/disable integrity protection on the respective regions of the first memory (abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph), where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Kubota in view of Zbiciak in view of Altman, directed towards a user/QM module writing to a doorbell in the QM area for alerting a supervisor/ASIL of a request to access a supervisor/ASIL region, and the disclosures by Laskos, directed towards bit values of a first memory indicating whether a corresponding region of a second memory should be protected, to provide for a combination where the QM area doorbell may comprise bits that may be set by the user/QM module to signal activating or deactivating restriction to the corresponding ASIL region by the supervisor/ASIL in order to provide for improved simplicity in conveying access requests]
Kubota, Zbiciak, and Altman are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak and Altman, to modify the disclosures by Kubota in view of Zbiciak to include disclosures by Altman since they both teach data storage and protection, wherein Altman is directed towards improved performance in association with access management (para. 4-5). Therefore, it would be applying a known technique (an application communicating access request to a memory region of a device by writing to a location within a memory area assigned to the application) to a known device (a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module generally having access restricted to QM area being given access to a region of ASIL area by a supervisor/ASIL module, the user/QM module communicating a request for access to the region by writing to a location within the QM area; doing so would provide for greater simplification in communicating access requests between different modules). MPEP 2143
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
Kubota in view of Zbiciak in view of Altman in view of Lasko does not explicitly disclose, but Zhang discloses:
setting the flags to a second value by the QM module; [Kubota in view of Zbiciak in view of Altman in view of Lasko as shown above teaches user/QM module communicating access request, for an ASIL region, to a supervisor/ASIL module by setting a bit in the QM area; it does not explicitly disclose, but Zhang discloses a first node obtaining a write lock corresponding to a write object on second, primary node, performing update to the corresponding write object, and sending a transaction completion notification to an upper-layer application prior to sending a write lock release message to the second node (para. 29, 177-178, 195-203; figs. 4, 6, 7A-7C and associated paragraphs); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Kubota in view of Zbiciak in view of Altman in view of Laskos providing for a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module, and disclosures by Zhang, directed towards a node obtaining a write lock for accessing an object in a primary node and releasing the write lock by communicating a write lock release message to the primary node after sending a transaction completion message to a upper-layer application, to provide for a combination where the user/QM module may similarly communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region]
Kubota, Zbiciak, Altman, Lasko, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman in view of Lasko and Zhang, to modify the disclosures by Kubota in view of Zbiciak in view of Altman in view of Lasko to include disclosures by Zhang since they both teach data storage and protection, wherein Zhang is directed towards transaction processing efficiency (para. 3-6). Therefore, it would be applying a known technique (a first node receiving a lock for accessing data of a second node, the first node sending a transaction completion message to an upper-layer application prior to communicating a write lock release message to the second node) to a known device (a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module modifying a bit to communicate access request to a region managed by a supervisor/ASIL module, where the user/QM module may communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region). MPEP 2143
As per claim 10, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 8 as shown above and further teaches:
10. The method of claim 8, further comprising: respectively changing set values of the flags by multiple functions of the QM module. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a plurality of bits that may be changed by a user/QM module (see claim 8 above; Lasko: abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph), where changing of each flag may correspond to respective one of multiple functions]
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 11, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 8 as shown above and further teaches:
11. The method of claim 8, further comprising: locating the flags in the QM area; and [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches the user/QM module modifying the bits in the QM area (see claim 8 above; Lasko: abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph)] accessing, by the ASIL module and the QM module, the flags without being authorized. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches both the supervisor/ASIL module and user/QM module having access to QM area by default (see claim 1 above; Kobuta: para. 13-14; Lasko: abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph); Altman also teaches the ASIL area managed by the supervisor/ASIL module having a location reflecting changes to the bit by the user/QM module (Altman: para. 61-67, 48)]
Kubota, Zbiciak, and Altman are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak and Altman, to modify the disclosures by Kubota in view of Zbiciak to include disclosures by Altman since they both teach data storage and protection, wherein Altman is directed towards improved performance in association with access management (para. 4-5). Therefore, it would be applying a known technique (an application communicating access request to a memory region of a device by writing to a location within a memory area assigned to the application) to a known device (a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module generally having access restricted to QM area being given access to a region of ASIL area by a supervisor/ASIL module, the user/QM module communicating a request for access to the region by writing to a location within the QM area; doing so would provide for greater simplification in communicating access requests between different modules). MPEP 2143
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 12, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 8 as shown above and further teaches:
12. The method of claim 8, further comprising: forming the QM area and the ASIL area by partitioning one memory device. [Kubota teaches a memory divided into QM and ASIL areas (13-14, 38)]
As per claim 13, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 8 as shown above and further teaches:
13. The method of claim 8, further comprising: setting the ASIL area and the ASIL module to an ASIL D level. [Kubota teaches the supervisor mode executing ASIL-D tasks on the ASIL area (para. 13-14)]
As per claim 14, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 8 as shown above and further teaches:
14. The method of claim 8, further comprising: activating the MPU or maintaining a state of the MPU when at least one of the flags does not have the first value as a set value after checking the set values of the flags. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a plurality of bits corresponding to protection status of respective regions of the area (see claim 1 above; Lasko: abstract; para. 24; fig. 2A and associated paragraph), where having all the bits to set to remove access restrictions to all the regions may correspond to deactivating the memory management unit, and having at least one flag set to maintain access restriction on at least one region may correspond to activating the memory management unit.]
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 15,
15. A method for protecting an automotive safety integrity level (ASIL) memory, the method comprising:; wherein the QM module is accessible to a QM area of a memory;; wherein the ASIL module is accessible to a ASIL area of the memory;; [Kubota teaches a system operating in one of two modes comprising supervisor/user modes with different access rights and a memory divided into QM and ASIL areas, the ASIL area being accessible by supervisor mode tasks having safety levels such as ASIL-D but prohibited from being accessed by user mode tasks having safety levels such as QM, whereas the QM area is accessible by both supervisor mode (e.g. ASIL-D) and user mode (e.g. QM) tasks (please see the attached translated foreign reference for Kubota (JP 2017016410 A): para. 13-14, 38; fig. 1 and associated paragraphs); where a memory management unit (MPU) may be used to realize the access restrictions to the ASIL area (monitoring) (para. 14)] performing memory access, wherein in the memory, the QM module accesses the ASIL area; [Where Kubota teaches prohibiting QM tasks from accessing ASIL area using a memory management unit (MPU) as shown above, Kubota also discloses that a setting may be configured to permit some access and further discloses that permission/prohibition may be set for each area for each type of access (para. 14), where it would have been obvious for one of ordinary skill in the arts, provided with Kubota’s disclosure, directed towards generally prohibiting access to ASIL area by QM tasks using a memory management unit as well as providing a setting for specifying permission/prohibition for each type of access, to provide for a combination where the memory management unit may be configured with a setting to allow access to ASIL area by at least some or all access types via QM tasks in order to provide for greater flexibility in data processing.]
Kubota does not explicitly disclose, but Zbiciak discloses:
module [Kubota as shown above teaches tasks and areas pertaining to supervisor mode and user mode; Zbiciak similarly discloses supervisor mode and user mode as well as respective supervisor code and user code to be ran on a CPU (para. 54-55)] and activating the MPU by the ASIL module. [Kubota as shown above teaches supervisor mode associated with ASIL area and a memory management unit (MPU) being configured to prohibit and/or allow access by user/QM tasks to ASIL area; Zbiciak teaches a supervisor being granted access to memory protection configurations and capable of changing memory protection configurations (para. 55, 72), where it would have been obvious for one of ordinary skill in the arts, provided with Kubota’s disclosure, directed towards a memory management unit restricting accesses (monitoring) to ASIL area by QM tasks under user mode but capable of being set to allow the accesses, with Zbiciak’s disclosures, directed towards a supervisor capable of modifying memory protection configurations, to provide for a combination where a supervisor (ASIL module) may be configured to activate or deactivate the memory restriction via memory management unit on the ASIL area from a user/QM module in order to provide for greater flexibility in memory protection management)]
Kubota and Zbiciak are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota and Zbiciak, to modify the disclosures by Kubota to include disclosures by Zbiciak since they both teach data storage and protection, wherein Zbiciak is directed towards improved flexibility in memory management (para. 3-10). Therefore, it would be applying a known technique (system comprising supervisor/user codes corresponding to supervisor/user modes, the supervisor mode being capable of modifying memory protection configurations) to a known device (system comprising supervisor/user modes and memory management module, the memory management module may be configured to provide access rights, for the user mode, to ASIL area assigned to the supervisor mode) ready for improvement to yield predictable results (system comprising supervisor/user modes executed in correspondence with supervisor/user codes (modules) and memory management module, the memory management module being configurable to provide access rights, by the user module, to ASIL area assigned to the supervisor module, where said configuration to the memory management module may be provided by the supervisor module in order to provide for greater flexibility in assigning memory access permissions). MPEP 2143
Kubota in view of Zbiciak does not explicitly disclose, but Altman discloses:
setting flags to a first value by a quality management (QM) module,; notifying, by the QM module, state changes of the flags to an ASIL module,; deactivating, by the ASIL module, a memory protection unit (MPU) configured to monitor access to the memory when the flags are set to the first value; [Kubota in view of Zbiciak as shown above teaches a user/QM module having its access restricted to a QM area but the restriction to ASIL area potentially being deactivated by a supervisor/ASIL module; Altman similarly discloses an application, executed in a limited privilege memory domain, requesting access to domain managed by a memory device and potentially being granted access by the memory device (para. 12, 61-65; figs. 3-4 and associated paragraphs), the application communicating the request by writing to a location (e.g. doorbell) in its (application) memory space to alert the memory device of an access request to a region of the device by having the write to said location being reflected on a second location managed by the memory device (para. 61-67, 48); it would have been obvious for one of ordinary skill in the arts, provided with disclosures by Kubota in view of Zbiciak, directed towards a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module, and disclosures by Altman, directed towards an application belong to a limited privilege domain being given access to a memory device region by a memory device after indicating access request on a doorbell on the application’s limited privilege domain which is reflected on a location managed by the memory device to alert the memory device, to provide for a combination where a user/QM module may request access to a region of ASIL area by indicating access request on a doorbell which is reflected on a location in the ASIL area to alert the supervisor/ASIL module. Doing so would provide for improved flexibility in managing restriction of the ASIL area by providing a low-overhead means for user/QM module to initiate access request]
[Where Kubota in view of Zbiciak in view of Altman as shown above teaches an user/QM module requesting access to a region of ASIL area by using a doorbell in the QM area, the doorbell being reflected on the ASIL area to alert the supervisor/ASIL module, it does not explicitly disclose a doorbell comprising a flag; Lasko teaches a first and a second memory, the first memory having regions which may be separately integrity protected, wherein the second memory comprises bits (flags) which may be used to enable/disable integrity protection on the respective regions of the first memory (abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph), where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Kubota in view of Zbiciak in view of Altman, directed towards a user/QM module writing to a doorbell in the QM area for alerting a supervisor/ASIL of a request to access a supervisor/ASIL region, and the disclosures by Laskos, directed towards bit values of a first memory indicating whether a corresponding region of a second memory should be protected, to provide for a combination where the QM area doorbell may comprise bits that may be set by the user/QM module to signal activating or deactivating restriction to the corresponding ASIL region by the supervisor/ASIL in order to provide for improved simplicity in conveying access requests]
Kubota, Zbiciak, and Altman are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak and Altman, to modify the disclosures by Kubota in view of Zbiciak to include disclosures by Altman since they both teach data storage and protection, wherein Altman is directed towards improved performance in association with access management (para. 4-5). Therefore, it would be applying a known technique (an application communicating access request to a memory region of a device by writing to a location within a memory area assigned to the application) to a known device (a user/QM module generally having access restricted to QM area being given access to ASIL area by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module generally having access restricted to QM area being given access to a region of ASIL area by a supervisor/ASIL module, the user/QM module communicating a request for access to the region by writing to a location within the QM area; doing so would provide for greater simplification in communicating access requests between different modules). MPEP 2143
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
Kubota in view of Zbiciak in view of Altman in view of Lasko does not explicitly disclose, but Zhang discloses:
notifying, by the QM module, completion of the memory access to the ASIL module; [Kubota in view of Zbiciak in view of Altman in view of Lasko as shown above teaches user/QM module communicating access request, for an ASIL region, to a supervisor/ASIL module by setting a bit in the QM area; it does not explicitly disclose, but Zhang discloses a first node obtaining a write lock corresponding to a write object on second, primary node, performing update to the corresponding write object, and sending a transaction completion notification to an upper-layer application prior to sending a write lock release message to the second node (para. 29, 177-178, 195-203; figs. 4, 6, 7A-7C and associated paragraphs); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Kubota in view of Zbiciak in view of Altman in view of Laskos providing for a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module, and disclosures by Zhang, directed towards a node obtaining a write lock for accessing an object in a primary node and releasing the write lock by communicating a write lock release message to the primary node after sending a transaction completion message to a upper-layer application, to provide for a combination where the user/QM module may similarly communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region]
Kubota, Zbiciak, Altman, Lasko, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman in view of Lasko and Zhang, to modify the disclosures by Kubota in view of Zbiciak in view of Altman in view of Lasko to include disclosures by Zhang since they both teach data storage and protection, wherein Zhang is directed towards transaction processing efficiency (para. 3-6). Therefore, it would be applying a known technique (a first node receiving a lock for accessing data of a second node, the first node sending a transaction completion message to an upper-layer application prior to communicating a write lock release message to the second node) to a known device (a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module modifying a bit to communicate access request to a region managed by a supervisor/ASIL module, where the user/QM module may communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region). MPEP 2143
As per claim 16, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 15 as shown above and further teaches:
16. The method of claim 15, further comprising: setting, by the QM module, the flags to a second value after notifying, by the QM module, completion of the memory access to the ASIL module. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a user/QM module notifying the supervisor/ASIL module of transaction completion prior to changing the bit to release its access to the ASIL region (see claim 15 above; Zhang: para. 29, 177-178, 195-203; figs. 4, 6, 7A-7C and associated paragraphs)]
Kubota, Zbiciak, Altman, Lasko, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman in view of Lasko and Zhang, to modify the disclosures by Kubota in view of Zbiciak in view of Altman in view of Lasko to include disclosures by Zhang since they both teach data storage and protection, wherein Zhang is directed towards transaction processing efficiency (para. 3-6). Therefore, it would be applying a known technique (a first node receiving a lock for accessing data of a second node, the first node sending a transaction completion message to an upper-layer application prior to communicating a write lock release message to the second node) to a known device (a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module modifying a bit to communicate access request to a region managed by a supervisor/ASIL module, where the user/QM module may communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region). MPEP 2143
As per claim 17, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 15 as shown above and further teaches:
17. The method of claim 15, further comprising: setting, by the QM module, the flags to a second value before or after notifying, by the QM module, completion of the memory access to the ASIL module. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a user/QM module notifying the supervisor/ASIL module of transaction completion prior to changing the bit to release its access to the ASIL region (see claim 15 above; Zhang: para. 29, 177-178, 195-203; figs. 4, 6, 7A-7C and associated paragraphs)]
Kubota, Zbiciak, Altman, Lasko, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman in view of Lasko and Zhang, to modify the disclosures by Kubota in view of Zbiciak in view of Altman in view of Lasko to include disclosures by Zhang since they both teach data storage and protection, wherein Zhang is directed towards transaction processing efficiency (para. 3-6). Therefore, it would be applying a known technique (a first node receiving a lock for accessing data of a second node, the first node sending a transaction completion message to an upper-layer application prior to communicating a write lock release message to the second node) to a known device (a user/QM module modifying a bit to communicate access/restriction to a region managed by a supervisor/ASIL module) ready for improvement to yield predictable results (a user/QM module modifying a bit to communicate access request to a region managed by a supervisor/ASIL module, where the user/QM module may communicate for release of access to the ASIL region by further modifying the bit after sending a transaction completion message to the supervisor/ASIL module in order to provide greater certainty in ensuring completion of the relevant operations prior to restricting access to the region). MPEP 2143
As per claim 18, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 15 as shown above and further teaches:
18. The method of claim 15, wherein the QM module includes multiple functions and the flags are commonly used by the multiple functions. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a plurality of bits that may be changed by a user/QM module (see claim 8 above; Lasko: abstract; para. 24, 34; claims 1, 7; fig. 2A and associated paragraph), where changing of each flag may correspond to respective one of multiple functions]
Kubota, Zbiciak, Altman, and Lasko are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman and Lasko, to modify the disclosures by Kubota in view of Zbiciak in view of Altman to include disclosures by Lasko since they both teach data storage and protection, wherein Lasko is directed towards improved data integrity (para. 2-4). Therefore, it would be applying a known technique (a memory comprising bits indicating whether a corresponding region of a second memory should be integrity protected) to a known device (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by writing to a doorbell within QM area) ready for improvement to yield predictable results (a user/QM module generally being restricted from accessing an ASIL area requesting access to a region of ASIL area by setting a corresponding bit within the QM area in order to provide for improved simplicity in conveying access requests). MPEP 2143
As per claim 20, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 15 as shown above and further teaches:
20. The method of claim 15, further comprising: generating, by the MPU, in a state of being activated, an exception when the QM module access the ASIL area. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang discloses a memory protection hardware which, upon detecting an invalid access, generates an exception (Zbiciak: para. 146)]
Kubota and Zbiciak are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota and Zbiciak, to modify the disclosures by Kubota to include disclosures by Zbiciak since they both teach data storage and protection, wherein Zbiciak is directed towards improved flexibility in memory management (para. 3-10). Therefore, it would be applying a known technique (system comprising supervisor/user codes corresponding to supervisor/user modes, the supervisor mode being capable of modifying memory protection configurations) to a known device (system comprising supervisor/user modes and memory management module, the memory management module may be configured to provide access rights, for the user mode, to ASIL area assigned to the supervisor mode) ready for improvement to yield predictable results (system comprising supervisor/user modes executed in correspondence with supervisor/user codes (modules) and memory management module, the memory management module being configurable to provide access rights, by the user module, to ASIL area assigned to the supervisor module, where said configuration to the memory management module may be provided by the supervisor module in order to provide for greater flexibility in assigning memory access permissions). MPEP 2143
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. (JP 2017016410 A) in view of Zbiciak et al. (US 20120191933 A1) in view of Altman et al. (US 20130305006 A1) in view of Lasko et al. (US 20190196984 A1) in view of Zhang et al. (US 20250173178 A1) in view of Natarajan et al. (US 20190102296 A1).
As per claim 9, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 8 as shown above. It does not explicitly disclose, but Natarajan discloses:
9. The method of claim 8, further comprising: locating the flags in positions spaced apart from each other across registers. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a user/QM module modifying bits in the QM area (see claim 1 above); Natarajan discloses use of a write data register for writing data, and, prior to the write data register being released/overwritten, copying data of the write data register to a backup data register to ensure safe programming of the write data (para. 22-26)]
Kubota, Zbiciak, Altman, Lasko, Zhang, and Natarajan are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang and Natarajan, to modify the disclosures by Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang to include disclosures by Natarajan since they both teach data storage and protection, wherein Natarajan is directed towards safe programming of write data (para. 23). Therefore, it would be applying a known technique (use of a write data register for storing data to an array; transferring data of write data register to backup data register prior to overwriting the write data register) to a known device (a user/QM module modifying bits in a QM area) ready for improvement to yield predictable results (a user/QM module modifying bits in a QM area, wherein the modification bits may be written using a write data register which is copied to a second, backup data register prior to overwriting the write data register in order to provide for safer data writes). MPEP 2143
As per claim 19, Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang teaches claim 15 as shown above. It does not explicitly disclose, but Natarajan discloses:
19. The method of claim 15, further comprising: locating the flags in registers where there are possibilities to be contaminated in terms of hardware. [Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang as shown above teaches a user/QM module modifying bits in the QM area (see claim 1 above); Natarajan discloses use of a write data register for writing data, and, prior to the write data register being released/overwritten, copying data of the write data register to a backup data register to ensure safe programming of the write data in event of programming failure (para. 22-26)]
Kubota, Zbiciak, Altman, Lasko, Zhang, and Natarajan are analogous to the claimed invention because they are in the same field of endeavor involving data storage and protection.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang and Natarajan, to modify the disclosures by Kubota in view of Zbiciak in view of Altman in view of Lasko in view of Zhang to include disclosures by Natarajan since they both teach data storage and protection, wherein Natarajan is directed towards safe programming of write data (para. 23). Therefore, it would be applying a known technique (use of a write data register for storing data to an array; transferring data of write data register to backup data register prior to overwriting the write data register) to a known device (a user/QM module modifying bits in a QM area) ready for improvement to yield predictable results (a user/QM module modifying bits in a QM area, wherein the modification bits may be written using a write data register which is copied to a second, backup data register prior to overwriting the write data register in order to provide for safer data writes). MPEP 2143
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Mansbart et al. (US 20240134709 A1) teaches a plurality of cores being assigned supervisor/user modes and the supervisor mode core capable of configuring a memory protection units.
Ito et al. (US 20180203823 A1) teaches a system comprising an ASIL core, a QM core, and a memory protection unit, and a shared memory divided into a QM region and an ASIL region, wherein the QM core may access the ASIL region via direct memory access.
Conclusion
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/E.Y.K./Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135