Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-19 are pending.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Haghighi et. al. U.S. Patent Pub No. 2016/0054933 (hereinafter Haghighi) in view of Kucherov et. al. US Patent Pub No. 2020/0349087 (hereinafter Kucherov).
Regarding Claim 1, Haghighi teaches a system comprising: processing circuitry including a cache memory (Figure 1; Para27-30 processor 102includes cache hierarchy 192); an internal memory operably coupled to the processing circuitry (Figure 1, memory type 1 118, shown to be DRAM. Paragraph 0029 shows that fast memories are accessed by processor 102 via a first protocol, making them “internal” to a processor/first chipset/memory type 1 grouping, and slower but non-volatile memories such as the HDD and SSD that make up can be assessed by processor 102 by a second chipset, making them “external” to the processor and first chipset);
accelerator circuitry operably coupled to the processing circuitry and the internal memory (Fig.2,5; Para56-58 accelerator processors 208 help perform tasks for the memory controller including determining routing of data accesses; Paragraph 61-64 memory controller 204 determines where to store data based on data category or storage preferences.).
However, Haghighi fails to teach but Kucherov teaches the accelerator circuitry configurable to: store, in the internal memory, copies of select blocks of data having respective addresses that map to respective locations in an external memory (Fig.5; Para70-71 primary memory 518 includes higher tier storage and intermediate tier storage, with the high tier storage including RAM, and that the memory units 516a-516n correspond to 216a-n. Storage units 514 are low tier storage and include storage elements 512a-512n corresponding to 308a-308n. Paragraph 0074 shows that some user data may be stored in 516b and some in storage device 512; Figure 8 step 812 shows that data is copied to higher tier storage keeping existing copy in low tier storage. Paragraph 0086 shows that the higher tier storage can be 516b and a copy can be included in a cache in primary memory 518.),
wherein at least a portion of data in each of the select blocks of data has an access request frequency that is greater than a threshold frequency (Fig. 5, Para74-75; Fig.8 step 810 shows that data is copied to higher tier when its activity exceeds a threshold value, discussed in paragraph 0086.);
intercept, from the processing circuitry, an access request for data having a target address that maps to a target location in the external memory (Figure 8 step 816 shows that a read receipt is received for user data, Para86-87.);
determine that a copy of data corresponding to the access request is present in one of the copies of select blocks of data stored in the internal memory(Figure 8 step 818 shows that it is determined if the user data is in a higher tier, Para86-87); and
remap the access request to an address in the internal memory for the copy of data corresponding to the access request (Figure 8 step 820 shows that data is read from higher tier storage in step 820, Para86-87).
Haghighi and Kucherov are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Haghighi, and incorporating the data tiering method, as taught by Kucherov.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Kucherov (Para2).
Regarding claim 2, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches wherein the accelerator circuitry is further configurable to track access of data of each of the select blocks of data to determine the access request frequency of the corresponding select block of data (Fig.5,8 Para61,74-75 "The embodiments described herein enable tiering of metadata pages to lower tier storage based on the frequency of its access and the availability of space in the high tier storage." Para85-87).
Regarding claim 3, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches wherein the access request frequency of each of the select blocks of data is adjusted over time (Fig.5, 8; Para74-75, 85-86).
Regarding claim 4, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches wherein, to adjust the access request frequency of each of the select blocks of data, the accelerator circuitry is further configurable to weigh more heavily access requests for data in the corresponding select block of data that occurred in a more recent subset of a time during which access requests for data in the corresponding select block of data have been made (Fig.5,8; Para61, 75-75,86-87).
Regarding claim 5, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches wherein the accelerator circuitry includes transaction tracker circuitry configurable to track access of data of each of the select blocks of data to determine the access request frequency of the corresponding select block of data(Fig.5,8 Para61,74-75, 85-87).
Regarding claim 6, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches wherein the accelerator circuitry further includes transaction mapping circuitry configurable to perform the remap operation(Fig.4,5; Para60-61 "the control subsystem 302b may be configured to maintain a mapping between IO addresses associated with data and the corresponding chunk hashes.").
Regarding claim 7, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches a first memory having a first latency; and a second memory having a second memory having a second latency that is greater than the first memory, wherein, for each copy of a select block of data stored in the internal memory, the accelerator circuitry is further configurable to store the copy of the select block of data in one of the first memory and the second memory based on the access frequency of the corresponding select block of data(Fig.4,5,8; Para60-61, 85-87)
Regarding claim 8, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Haghighi teaches further comprising the external memory, wherein the system is embodied as an integrated circuit (IC), and the external memory is external to the IC (Fig.1 Para27-30).
Regarding claim 9, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches further comprising: a controller configurable to provide a clock signal, wherein the access request frequency of each of the select blocks of data is adjusted over time based on the clock signal(Fig.5, 8; Para74-75, 86-87).
Regarding claim 10, the combination of Haghighi and Kucherov teaches all the limitations of the base claims as outlined above.
Further, Kucherov teaches further comprising: a copy engine configurable to copy each of the select blocks of data having respective addresses that map to respective locations in the external memory in response to determining that the access request frequency of the corresponding select block of data is greater than the threshold frequency(Fig.5,8; Para86-87 "Otherwise, the copy of the user data stored in the low tier storage is read in block 808.") .
Regarding claims 11-19, the combination of Haghighi and Kucherov teaches these claims according to the reasoning set forth in claim 1-10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sugimori, US20170139826 teaches Garbage collecting and monitoring access frequency.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135