DETAILED ACTION
This action responds to Application No. 18/987269, filed 12/19/2024.
Claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/07/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 3, 5, 6, 7, 8-9, 10, 12, 13, 14, 15-17, 18, 19, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 3-4, 7, 8, 9, 10-11, 7, 13, 15, 16, 18, and 19 of U.S. Patent No. 12211548. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims merely represent broadened versions of the claims in Patent No. 12211548, as follows:
Claim
Patent No. 12211548
Instant Application
1
A memory device, comprising: a memory array comprising a set of memory cells; and control logic, operatively coupled with the memory array, to perform operations comprising:
A memory device, comprising: a memory array comprising a set of memory cells; and control logic, operatively coupled with the memory array, to perform operations comprising: (claim 1)
causing a programming pulse to be applied to a set of wordlines, wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions;
causing a programming pulse to be applied to a set of wordlines comprising a set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions, and a set of inter-cell regions of a charge trap layer (claim 1)
executing a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions; and executing a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.
executing a first erase cycle on the first set of even-numbered wordlines to remove a first subset of the set of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines; and executing a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.
2
The memory device of claim 1, wherein the first erase sub-operation comprises a first erase cycle.
executing a first erase cycle (claim 1)
3
The memory device of claim 2, wherein the first erase cycle comprises a first set of one or more erase pulses.
erase pulse applied during the first erase cycle (claim 4)
5
The memory device of claim 1, the operations further comprising causing a high voltage level to be applied to the second subset of wordlines during the first erase sub-operation, wherein the high voltage level is greater than or equal to an erase voltage level of an erase pulse applied during the first erase sub-operation.
The memory device of claim 1, the operations further comprising causing a high voltage level to be applied to the second set of odd-numbered wordlines during the first erase cycle (claim 3)
wherein the high voltage level is greater than or equal to an erase voltage level of an erase pulse applied during the first erase cycle (claim 4)
6
The memory device of claim 1, wherein, following the executing of the second erase sub-operation, a third subset of the set of electrons remain in a set of inter-cell regions of a charge trap layer.
The memory device of claim 1, wherein, following the executing of the second erase cycle, a third subset of the set of electrons remain in the set of inter-cell regions of the CT layer (claim 7)
7
The memory device of claim 6, the operations further comprising, following the executing of the second erase sub-operation, executing a programming operation to program the first subset of the set of electrons and the second subset of the set of electrons.
The memory device of claim 7, the operations further comprising, following the executing of the second erase cycle, executing a programming operation to program the first set of memory cells and the second set of memory cells (claim 8)
8
A method comprising: causing a programming pulse to be applied to a set of wordlines corresponding to a set of memory cells of a memory device,
A method comprising: causing, at a first time, a programming pulse to be applied to a set of wordlines corresponding to a set of memory cells (claim 9)
wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions;
wherein the programming pulse causes injection of a set of electrons into a charge trap (CT) layer of a memory device (claim 9)
executing a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions; and executing a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.
executing, at a second time, a first erase cycle on a first set of even-numbered wordlines to remove a first subset of the set of electrons from a first set of gate regions corresponding to the first set of even-numbered wordlines; and
executing, at a third time, a second erase cycle on a second set of odd-numbered wordlines to remove a second subset of the set of electrons from a second set of gate regions corresponding to the second set of odd-numbered wordlines, wherein a third subset of electrons occupy a set of inter-cell regions of the CT layer (claim 9)
9
The method of claim 8, wherein the first erase sub-operation comprises a first erase cycle.
executing, at a second time, a first erase cycle (claim 9)
10
The method of claim 9, wherein the first erase cycle comprises a first set of one or more erase pulses.
an erase pulse applied during the first erase cycle (claim 11)
12
The method of claim 8, further comprising causing a high voltage level to be applied to the second subset of wordlines during the first erase sub-operation, wherein the high voltage level is greater than or equal to an erase voltage level of an erase pulse applied during the first erase sub-operation.
The method of claim 9, further comprising:causing, during the first erase cycle, a high voltage level to be applied to the second set of odd-numbered wordlines; and causing, during the first erase cycle, a ground voltage level to be applied to the first set of even-numbered wordlines (claim 10)
The method of claim 10, wherein the high voltage level is greater than or equal to an erase voltage level of an erase pulse applied during the first erase cycle (claim 11)
13
The method of claim 9, wherein, following the executing of the second erase sub-operation, a third subset of the set of electrons remain in a set of inter-cell regions of a charge trap layer.
The memory device of claim 1, wherein, following the executing of the second erase cycle, a third subset of the set of electrons remain in the set of inter-cell regions of the CT layer (claim 7)
14
The method of claim 13, further comprising, following the executing of the second erase sub-operation, executing a programming operation to program the first subset of the set of electrons and the second subset of the set of electrons.
The method of claim 9, further comprising executing, at fourth time, a programming operation to program the set of memory cells (claim 13)
15
A memory device comprising: a memory array comprising a set of memory cells; and control logic, operatively coupled with the memory array, to perform operations comprising:
A memory device comprising: a memory array comprising a plurality of memory cells; and control logic, operatively coupled with the memory array, to perform operations comprising: (claim 15)
causing injection of a set of electrons into a charge trap (CT) layer of the memory device
wherein the programming pulse causes injection of a set of electrons into a charge trap (CT) layer of a memory device (claim 15)
causing removal of a first subset of the set of electrons from a first set of gate regions of the memory device; and causing removal of a second subset of the set of electrons from a second set of gate regions of the memory device.
executing, at a second time, a first erase cycle on a first set of even-numbered wordlines to remove a first subset of the set of electrons from a first set of gate regions corresponding to the first set of even-numbered wordlines; and executing, at a third time, a second erase cycle on a second set of odd-numbered wordlines to remove a second subset of the set of electrons from a second set of gate regions corresponding to the second set of odd-numbered wordlines, wherein a third subset of electrons occupy a set of inter-cell regions of the CT layer (claim 15)
16
The memory device of claim 15, wherein the first subset of the set of electrons are caused to be removed by executing a first erase sub-operation of an erase operation.
executing, at a second time, a first erase cycle on a first set of even-numbered wordlines to remove a first subset of the set of electrons from a first set of gate regions corresponding to the first set of even-numbered wordlines (claim 15)
17
The memory device of claim 16, wherein the second subset of the set of electrons are caused to be removed by executing a second erase sub-operation of the erase operation.
executing, at a third time, a second erase cycle on a second set of odd-numbered wordlines to remove a second subset of the set of electrons from a second set of gate regions corresponding to the second set of odd-numbered wordlines (claim 15)
18
The memory device of claim 17, the operations further comprising: causing, during the first erase sub-operation, a first voltage level to be applied to the second subset of wordlines; and causing, during the first erase sub-operation, a ground voltage level to be applied to the first subset of wordlines
The memory device of claim 15, the operations further comprising:causing, during the first erase cycle, a high voltage level to be applied to the second set of odd-numbered wordlines; and causing, during the first erase cycle, a ground voltage level to be applied to the first set of even-numbered wordlines (claim 16)
19
The memory device of claim 18, the operations further comprising: causing, during the second erase sub-operation, a second voltage level to be applied to the first subset of wordlines; and causing, during the second erase sub-operation, the ground voltage level to be applied to the second subset of wordlines.
The memory device of claim 15, the operations further comprising:causing, during the second erase cycle, a high voltage level to be applied to the first set of even-numbered wordlines; and causing, during the second erase cycle, a ground voltage level to be applied to the second set of odd-numbered wordlines (claim 18)
20
The memory device of claim 15, the operations further comprising executing a programming operation to program the set of memory cells.
The memory device of claim 15, further comprising executing, at fourth time, a programming operation to program the set of memory cells (claim 19)
Claims 4 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 9 of US Patent No. 12211548 in view of Yang et al (US 10861571) [hereinafter “Yang 2”].
Re claim 4, Patent No. 12211548 discloses the device of claim 3, but does not explicitly disclose an erase verify operation.
Yang 2 discloses that each of the first set of one or more erase pulses is followed by an erase verify operation (Fig. 12). The flowchart repeatedly sends erase pulses, followed by erase verify operations.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the multi-level cell memory of Patent No. 12211548 to perform an erase verify after each erase pulse, as in Yang 2, because Yang 2 suggests that performing an erase verify would enable the memory to repeat erase pulse operations until it can be verified that the cells were actually successfully erased, thus ensuring proper erasure (col. 25, lines 21-33).
Re claim 11, Patent No. 12211548 and Yang 2 disclose the device of claim 4; accordingly, they also disclose a method implemented by that device, as in claim 11, respectively (see Yang 1, claim 16).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 8-10, 12, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2019/0362798 A1) [hereinafter “Yang 1”].
Re claim 1, Yang 1 discloses the following:
A memory device, comprising: a memory array comprising a set of memory cells (Fig. 1C; abstract). The memory comprises an array of memory cells;
control logic, operatively coupled with the memory array, to perform operations comprising: (Fig. 2, controller 238). The controller is coupled to the memory die (memory array);
causing a programming pulse to be applied to a set of wordlines, wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions (¶ 25-26, 28, and 46). The memory cells utilize floating-gate transistors (gate regions)(¶ 25). The blocks are divided into wordlines (¶ 26). A refresh/recover command includes sending a programming pulse to all programmed cells in a block (applied to a set of wordlines) (¶ 28) by injecting charge (causes a set of electrons to be injected) into the block, which includes first and second sub-blocks, each of which contain floating-gate transistors (first set of gate regions, second set of gate regions (¶ 46);
executing a first sub-erase operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions; and executing a second sub-erase operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from a second set of gate regions (¶ 37). The block may be divided into first and second sub-blocks (sets of wordlines), each of which may be erased independently (executing a first sub-erase operation and executing a second sub-erase operation).
Yang 1 discloses the limitations of claim 1 above; however, it is not explicitly stated whether each of these limitations appears in the same embodiment; nevertheless, it would have been obvious to one having ordinary skill in the art (AIA ) to combine the limitations of Yang into a common embodiment, because it would be obvious to make these elements integral (MPEP § 2144.04(V)(B)).
Re claim 2, Yang 1 discloses the device of claim 1, and further discloses that the first erase sub-operation comprises a first erase cycle (¶ 33). The sub-block erase operation is an erase operation (erase cycle).
Re claim 3, Yang 1 discloses the device of claim 2, and further discloses that the erase cycle comprises a first set of one or more erase pulses (¶ 113). The programming operation signals may include one or more erase pulses.
Re claim 5, Yang 1 discloses the device of claim 1, and further discloses causing a high voltage level to be applied to the second subset of wordlines during the first erase sub-operation, wherein the high voltage level is greater than or equal to an erase voltage level of an erase pulse applied during the first erase sub-operation (¶ 34). When a first sub-block is erased (during the first erase sub-operation), a high voltage of 20V is applied to the second sub-block wordlines (second subset of wordlines), which is higher than the 0V applied to the first sub-block wordlines (greater than or equal to an erase voltage level of an erase pulse applied during the first erase sub-operation.
Re claims 8-10 and 12, Yang 1 discloses the devices of claims 1-3 and 5, respectively; accordingly, it also discloses methods implemented by those devices, as in claims 8-10 and 12, respectively (see Yang 1, claim 16).
Re claim 15, Yang 1 discloses the following:
A memory device, comprising: a memory array comprising a set of memory cells (Fig. 1C; abstract). See claim 1 above;
control logic, operatively coupled with the memory array, to perform operations comprising: (Fig. 2, controller 238). See claim 1 above;
causing injection of a set of electrons into a charge trap (CT) layer of the memory device (¶ 46). Charge can be injected into a charge trap layer of the memory device;
causing removal a first subset of the set of electrons from a first set of gate regions of the memory device; and causing removal of a second subset of the set of electrons from a second set of gate regions (¶ 37). The block may be divided into first and second sub-blocks (sets of wordlines), each of which may be erased independently (executing a first sub-erase operation and executing a second sub-erase operation).
Yang 1 discloses the limitations of claim 1 above; however, it is not explicitly stated whether each of these limitations appears in the same embodiment; nevertheless, it would have been obvious to one having ordinary skill in the art (AIA ) to combine the limitations of Yang into a common embodiment, because it would be obvious to make these elements integral (MPEP § 2144.04(V)(B)).
Re claim 16, Yang 1 discloses the device of claim 15, and further discloses that the first subset of the set of electrons are caused to be removed by executing a first sub-erase operation of an erase operation (¶ 37). See claim 1 above.
Re claim 17, Yang 1 discloses the device of claim 16, and further discloses that the second subset of the set of electrons are caused to be removed by executing a second erase sub-operation of the erase operation (¶ 37). See claim 1 above.
Re claim 18, Yang 1 discloses the device of claim 17, and further discloses the operations further comprising: causing, during the first erase sub-operation, a first voltage level to be applied to the second subset of wordlines; and causing, during the first erase sub-operation, a ground voltage to be applied to the first subset of wordlines (¶ 34). During erasing a first sub-block (first erase sub-operation), a 20V (first voltage level) is applied to the second sub-block, while a 0V (ground voltage level) is applied to the first sub-block.
Re claim 19, Yang 1 discloses the device of claim 18, and further discloses the operations further comprising: causing, during the second erase sub-operation, a second voltage level to be applied to the first subset of wordlines; and causing, during the second erase sub-operation, a ground voltage to be applied to the second subset of wordlines (¶ 34). During erasing a second sub-block (second erase sub-operation), a 20V (second voltage level) is applied to the first sub-block), while a 0V (ground voltage level) is applied to the second sub-block.
Re claims 20, Yang 1 discloses the device of claim 15, and further discloses operations further comprising executing a programming operation to program the set of memory cells (¶ 27-28). The blocks and sub-blocks can be programmed using a program operation.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yang 1 in view of Yang et al (US 10861571) [hereinafter “Yang 2”].
Re claim 4, Yang 1 discloses the device of claim 3, but does not explicitly disclose an erase verify operation.
Yang 2 discloses that each of the first set of one or more erase pulses is followed by an erase verify operation (Fig. 12). The flowchart repeatedly sends erase pulses, followed by erase verify operations.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the multi-level cell memory of Yang 1 to perform an erase verify after each erase pulse, as in Yang 2, because Yang 2 suggests that performing an erase verify would enable the memory to repeat erase pulse operations until it can be verified that the cells were actually successfully erased, thus ensuring proper erasure (col. 25, lines 21-33).
Re claim 11, Yang 1 and Yang 2 disclose the device of claim 4; accordingly, they also disclose methods implemented by those devices, as in claims 8-10 and 12, respectively (see Yang 1, claim 16).
Claims 6-7 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang 1 in view of Lee et al (US 7142455 B1).
Re claim 6, Yang 1 discloses the device of claim 1, and further discloses a charge-trap layer (¶ 46).
However, Yang 1 does not explicitly describe the electrons in a set of inter-cell regions of a charge trap layer.
Lee discloses that following the executing of the second erase sub-operation, a third subset of the set of electrons remain in a set of inter-cell regions of a charge trap layer (col. 4, lines 20-39). De-trapping of holes/electrons in the charge-trap layer occurs at some point after repeated program/erase cycles of multi-level flash memory cells (after executing of the second erase sub-operation).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the multi-level cell memory of Yang 1 to utilize de-trapping (removing holes/electrons) from a charge trap layer after program/erase cycles, rather than during them, because Lee suggests that this would reduce read margin disturbance (col. 3, lines 6-10).
Re claim 7, Yang 1 and Lee disclose the device of claim 6, and Lee further discloses following the executing of the second erase sub-operation, executing a programming operation to program the first subset of the set of electrons and the second subset of the set of electrons (col. 4, lines 10-19). The cells are repeatedly erased and then re-programmed with data. Accordingly, a programming instruction for the first and second subset of electrons into the wordlines occurs after the erase sub-operations.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the mult-level cell sub-block erasure of Yang 1 to execute programming instructions on the erased sub-blocks after the erasure, as in Lee, because it would be applying a known technique to improve a similar device in the same way. Yang 1 discloses erasing sub-blocks in a multi-level cell memory. Lee also discloses erasing sub-blocks in a multi-level cell memory, which has been improved in a similar way to the claimed invention, to subsequently program data back into these erased locations, as in Lee, because it would yield the predictable improvement of allowing said erased memory to be reused to hold new data.
Re claims 13-14, Yang 1 and Lee disclose the devices of claims 6-7, respectively; accordingly, they also disclose methods implemented by those devices, as in claims 13-14, respectively (see Yang 1, claim 16).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Schuette (US 2013/0124787 A1) Discloses a MLC memory programming higher and lower pages utilizing odd/even wordlines (¶ 31).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132