DETAILED ACTION
Claims 1-20 are present for examination.
Claims 1, 7, 9, 15 and 17 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/16/2026 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13, 15 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-10, 13, 15-18 and 20 of U.S. Patent No. 12,204,788 in view of Palmer (US 11,194,511).
Claim 1 of the present application corresponds to claim 1 of the ‘788 patent, where “A system storage…” corresponds to claim 1, line 1 of the ‘788 patent; where “a plurality of storage devices comprising multiplane dies…” corresponds to claim 1, line 2-3 of the ‘788 patent; “a storage system controller operatively coupled to the plurality of storage devices…” corresponds to claim 1, line 4-6 of the ‘788 patent; and “in response to adjusting the number of planes, utilize a block size for allocating blocks by combining a set of erase blocks…” corresponds to claim 1, line 12-15 of the ‘788 patent.
The ‘788 patent does not teach identify an amount of power to be used by the storage system; and adjust a number of planes of one or more of the multiplane dies used simultaneously for accessing data such that a power usage of the storage system is less than or equal to the amount of power.
However, Palmer teaches identify an amount of power to be used by the storage system (see column 6, line 67 and column 7, lines 1-4; each of the memory devices 220-1 to 220-M corresponds to a respective memory channel, which can comprise a group of memory devices. Also in column 15, lines 49-54; determining a power estimate based on the number of active channels and the scheduling of intervals for each command type on each active channel); and adjust a number of planes of one or more of the multiplane dies used simultaneously for accessing data (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) such that a power usage of the storage system is less than or equal to the amount of power (see column 15, lines 53-63; the estimate can be compared to a power budget to provide a power budget error. At 807, the number of active channels can be adjusted to reduce the power budget error. For example, if the power budget error indicates the memory device is using more power than allowed by the power budget, the number of channels can be reduced to reduce power usage).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by the ‘788 patent to include the above mentioned to provide high performance while conforming to the power budget (see Palmer, column 15, lines 4-6 and column 20, lines 63-67).
Claim 2 of the present application corresponds to claim 4 of the ‘788 patent, where “move one or more portions from a first erase block…” corresponds to claim 4, lines 1-4 of the ‘788 patent.
Claim 3 of the present application corresponds to claim 5 of the ‘788 patent, where “identify the one or more portions of the first erase block…” corresponds to claim 5, lines 1-5 of the ‘788 patent.
Claim 4 of the present application corresponds to claim 6 of the ‘788 patent, where “wherein moving one or more portions from the first erase block to the second erase block is performed during a garbage…” corresponds to claim 6, lines 1-4 of the ‘788 patent.
Claim 5 of the present application corresponds to claim 7 of the ‘788 patent, where “wherein moving one or more portions from the first erase block to the second erase block is performed during a defragmentation…” corresponds to claim 7, lines 1-4 of the ‘788 patent.
Claim 6 of the present application corresponds to claim 8 of the ‘788 patent, where “wherein the block size is larger than a previous…” corresponds to claim 8, lines 1-2 of the ‘788 patent.
Claim 7 of the present application corresponds to claim 9 of the ‘788 patent, where “wherein the number of planes of the multiplane die used simultaneously…” corresponds to claim 9, lines 1-3 of the ‘788 patent.
Claim 8 of the present application corresponds to claim 10 of the ‘788 patent, where “write data to a storage device of the plurality of storage devices, wherein different portions…” corresponds to claim 10, lines 1-6 of the ‘788 patent.
Claim 9 of the present application corresponds to claim 13 of the ‘788 patent, where “A method…” corresponds to claim 13, line 1 of the ‘788 patent; where “in response to adjusting the number of planes, utilizing a block size for allocating blocks by combining a set of erase blocks…” corresponds to claim 13, line 9-12 of the ‘788 patent.
The ‘788 patent does not teach identifying an amount of power to be used by the storage system; and adjusting a number of planes of one or more of the multiplane dies used simultaneously for accessing data such that a power usage of the storage system is less than or equal to the amount of power.
However, Palmer teaches identifying an amount of power to be used by the storage system (see column 6, line 67 and column 7, lines 1-4; each of the memory devices 220-1 to 220-M corresponds to a respective memory channel, which can comprise a group of memory devices. Also in column 15, lines 49-54; determining a power estimate based on the number of active channels and the scheduling of intervals for each command type on each active channel); and adjusting a number of planes of one or more of the multiplane dies used simultaneously for accessing data (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) such that a power usage of the storage system is less than or equal to the amount of power (see column 15, lines 53-63; the estimate can be compared to a power budget to provide a power budget error. At 807, the number of active channels can be adjusted to reduce the power budget error. For example, if the power budget error indicates the memory device is using more power than allowed by the power budget, the number of channels can be reduced to reduce power usage).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by the ‘788 patent to include the above mentioned to provide high performance while conforming to the power budget (see Palmer, column 15, lines 4-6 and column 20, lines 63-67).
Claim 10 of the present application corresponds to claim 15 of the ‘788 patent, where “moving one or more portions from a first erase block…” corresponds to claim 15, lines 1-4 of the ‘788 patent.
Claim 11 of the present application corresponds to claim 16 of the ‘788 patent, where “identifying the one or more portions of the first erase block…” corresponds to claim 16, lines 1-4 of the ‘788 patent.
Claim 12 of the present application corresponds to claim 17 of the ‘788 patent, where “wherein moving one or more portions from the first erase block to the second erase block is performed during a garbage…” corresponds to claim 17, lines 1-4 of the ‘788 patent.
Claim 13 of the present application corresponds to claim 18 of the ‘788 patent, where “wherein moving one or more portions from the first erase block to the second erase block is performed during a defragmentation…” corresponds to claim 18, lines 1-4 of the ‘788 patent.
Claim 15: ‘788 patent does not teach wherein the number of planes of the multiplane die used simultaneously for accessing data is increased.
However, Palmer teaches wherein the number of planes of the multiplane die used simultaneously (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) for accessing data is increased (see column 12, lines 10-15 and column 13, lines 12-30; a memory controller to arbitrate activation and de-activation of the die of a multiple memory die device to maintain as many active die as possible while still managing power consumption of the memory device to a power budget. In certain examples, the method can be replicated and run in parallel with one or more other similar methods for each active die. At 601, a die can be enabled (i.e., die/planes may be enabled therefore increasing the number of die/planes)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by the ‘788 patent to include the above mentioned to provide high performance while conforming to the power budget (see Palmer, column 15, lines 4-6 and column 20, lines 63-67).
Claim 17 of the present application corresponds to claim 20 of the ‘788 patent, where “A non-transitory computer readable…” corresponds to claim 20, lines 1-3 of the ‘788 patent; where “in response to adjusting the number of planes, utilize a block size for allocating blocks by combining a set of erase blocks…” corresponds to claim 20, lines 11-14 of the ‘788 patent.
The ‘788 patent does not teach identify an amount of power to be used by the storage system; and adjust a number of planes of one or more of the multiplane dies used simultaneously for accessing data such that a power usage of the storage system is less than or equal to the amount of power.
However, Palmer teaches identify an amount of power to be used by the storage system (see column 6, line 67 and column 7, lines 1-4; each of the memory devices 220-1 to 220-M corresponds to a respective memory channel, which can comprise a group of memory devices. Also in column 15, lines 49-54; determining a power estimate based on the number of active channels and the scheduling of intervals for each command type on each active channel); and adjust a number of planes of one or more of the multiplane dies used simultaneously for accessing data (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) such that a power usage of the storage system is less than or equal to the amount of power (see column 15, lines 53-63; the estimate can be compared to a power budget to provide a power budget error. At 807, the number of active channels can be adjusted to reduce the power budget error. For example, if the power budget error indicates the memory device is using more power than allowed by the power budget, the number of channels can be reduced to reduce power usage).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by the ‘788 patent to include the above mentioned to provide high performance while conforming to the power budget (see Palmer, column 15, lines 4-6 and column 20, lines 63-67).
Claims 14 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,204,788 and Palmer (US 11,194,511) in view of Sinclair (US7,383,375).
With respect claim 14, ‘788 patent and Palmer do not teach wherein the block size is larger than a previous block size.
However, Sinclair teaches wherein adaptive metablock size may be determined based on the nature of the data (control data, data from host) or may be determined based on boundaries within the data, such as boundaries between files (see column 4, lines 45-53)… an adaptive metablock is an example of a metablock that does not have fixed size (i.e., a new block may be larger or smaller than previous one) (see claim 13, lines 13-16 and column 18, lines 34-46).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by ‘788 patent and Palmer to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 18, ‘788 patent and Palmer do not teach wherein the processing device is further to: move one or more portions from a first erase block to a second erase block, the first erase block having the block size for allocating blocks.
However, Sinclair teaches an adaptive metablock has a variable number of erase blocks. The erase blocks of a metablock may be from fewer than all the planes of the memory array (see column 4, lines 62-65)… where data is relocated, adaptive metablock size may be based on the number of logical groups that contain relocated data (see column 21, lines 31-33). Adaptive logical block 1340 and adaptive metablock 1341 may be formed by copying data from adaptive metablock 1331 in the memory array (i.e., data from erased block in adaptive metablock are moved/copied to another) (see column 17, lines 39-45).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by ‘788 patent and Palmer to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 19, ‘788 patent and Palmer do not teach wherein the processing device is further to: identify the one or more portions of the first erase block based on metadata, the metadata indicating live data within the first erase blocks.
However, Sinclair teaches complete original metablock may be considered a fully obsolete original metablock when all valid sectors within it have been copied (see column 41, lines 6-11)… If any partially obsolete original metablocks exist 4743 (complete original metablocks) then reduced size metablocks are allocated 4745 as relocated metablocks and valid sectors are copied 4747 until the original block is fully obsolete 4749 (i.e., block with valid data is moved/copied) (see column 42, lines 62-67).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by ‘788 patent and Palmer to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 20, ‘788 patent and Palmer do not teach wherein moving one or more portions from the first erase block to the second erase block is performed during a garbage collection operation of the storage system.
However, Sinclair teaches wherein obsolete metablocks 84, 85 are eventually erased and made available again during garbage collection. Combining the updated data sectors 81 with the original sectors may be done when the data is received. Alternatively, sectors of updated data 81 may be written to another location and may be combined with original data at a later time as part of garbage collection (see column 12, lines 15-30).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by ‘788 patent and Palmer to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
Claims 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,204,788 and Palmer (US 11,194,511) in view of Karamcheti et al. (US9,286,002).
With respect claim 16, ‘788 patent and Palmer do not teach writing data to a storage device of the plurality of storage devices, wherein different portions of the data are written to different planes of the multiplane dies and wherein a number of different portions is equal to the number of planes.
However, Karamcheti et al. teaches wherein a package is a multi-chip module that includes one or more flash memory dice. Each flash memory die may be composed of flash planes that include constituent blocks of memory cells where data are stored (see column 6, lines 116-19)… the data chunks may be striped across 8 different dice in 8 different packages along with parity encoding to provide the ability to reconstruct the data chunks in the event of the loss of any single die or package (i.e., portion of data is written to different dies) (see column 15, lines 27-30).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by ‘788 patent and Palmer to include the above mentioned to provide performance improvement and data reliability (see Karamcheti, column 3, lines 43-45 and 56-60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 11,194,511) in view of Parker (US 2020/0125294).
With respect claim 1, Palmer teaches a plurality of storage devices comprising multiplane dies (see column 3, lines 62-67 and column 4, lines 1-4; memory device 110 includes a memory controller 115 and a memory array 120 including, for example, a number of individual memory device. Also in column 6, lines 19-36; memory array 120 can include one or more memory devices. The individual memory devices can include several memory cells arranged in, for example, a number of devices, planes); and
a storage system controller operatively coupled to the plurality of storage devices, the storage system controller comprising a processing device (see Fig. 1 and 2 and column 7, lines 53-58; memory controller 115/215 coupled to memory) configured to:
identify an amount of power to be used by the storage system (see column 6, line 67 and column 7, lines 1-4; each of the memory devices 220-1 to 220-M corresponds to a respective memory channel, which can comprise a group of memory devices. Also in column 15, lines 49-54; determining a power estimate based on the number of active channels and the scheduling of intervals for each command type on each active channel);
adjust a number of planes of one or more of the multiplane dies used concurrently for accessing data (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) such that a power usage of the storage system is less than or equal to the amount of power (see column 15, lines 53-63; the estimate can be compared to a power budget to provide a power budget error. At 807, the number of active channels can be adjusted to reduce the power budget error. For example, if the power budget error indicates the memory device is using more power than allowed by the power budget, the number of channels can be reduced to reduce power usage).
Palmer does not teach in response to adjusting the number of planes, utilize a block size for allocating blocks by combining a set of erase blocks at a same address in separate planes based on the adjusted number of planes, wherein the block size corresponds to the adjusted number of planes concurrently for accessing data.
However, Parker teaches wherein two planes 10 for each die 111 are shown in FIG. 4, but the die can include any number of planes, such as 2, 4, 6, 8 or more planes… a superblock 50 comprises one or more blocks 20 striped across each plane 10 of each of the dies 111-1 to 111-N to store data streams. For high performance SSDs, a data stream is written to multiple pages 30 across multiple dies 111 of the superblock 50 simultaneously or concurrently. Similarly, read operation of pages 30 across multiple dies 111 of superblock 50 can be performed simultaneously or concurrently (see paragraphs 42-43); and wherein an erasable unit of superblock 50 of FIG. 4 increases in size with the number of planes (i.e., size of the erasable unit/blocks is adjusted when the number of planes is adjusted) (see paragraph 77).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Palmer to include the above mentioned to improve performance of the memory (see Parker, paragraph 60).
With respect claim 7, Palmer teaches wherein the number of planes of the multiplane die used concurrently (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) for accessing data is increased (see column 12, lines 10-15 and column 13, lines 12-30; a memory controller to arbitrate activation and de-activation of the die of a multiple memory die device to maintain as many active die as possible while still managing power consumption of the memory device to a power budget. In certain examples, the method can be replicated and run in parallel with one or more other similar methods for each active die. At 601, a die can be enabled (i.e., die/planes may be enabled therefore increasing the number of die/planes)).
With respect claim 9, Palmer teaches identifying an amount of power to be used by a storage system (see column 6, line 67 and column 7, lines 1-4; each of the memory devices 220-1 to 220-M corresponds to a respective memory channel, which can comprise a group of memory devices. Also in column 15, lines 49-54; determining a power estimate based on the number of active channels and the scheduling of intervals for each command type on each active channel) comprising a plurality of storage devices comprising multiplane dies (see column 3, lines 62-67 and column 4, lines 1-4; memory device 110 includes a memory controller 115 and a memory array 120 including, for example, a number of individual memory device. Also in column 6, lines 19-36; memory array 120 can include one or more memory devices. The individual memory devices can include several memory cells arranged in, for example, a number of devices, planes);
adjusting a number of planes of one or more of the multiplane dies used concurrently for accessing data (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) such that a power usage of the storage system is less than or equal to the amount of power (see column 15, lines 53-63; the estimate can be compared to a power budget to provide a power budget error. At 807, the number of active channels can be adjusted to reduce the power budget error. For example, if the power budget error indicates the memory device is using more power than allowed by the power budget, the number of channels can be reduced to reduce power usage).
Palmer does not teach in response to adjusting the number of planes, utilizing a block size for allocating blocks by combining a set of erase blocks at a same address in separate planes, wherein the block size corresponds to the adjusted number of planes used concurrently for accessing data.
However, Parker teaches wherein two planes 10 for each die 111 are shown in FIG. 4, but the die can include any number of planes, such as 2, 4, 6, 8 or more planes… a superblock 50 comprises one or more blocks 20 striped across each plane 10 of each of the dies 111-1 to 111-N to store data streams. For high performance SSDs, a data stream is written to multiple pages 30 across multiple dies 111 of the superblock 50 simultaneously or concurrently. Similarly, read operation of pages 30 across multiple dies 111 of superblock 50 can be performed simultaneously or concurrently (see paragraphs 42-43); and wherein an erasable unit of superblock 50 of FIG. 4 increases in size with the number of planes (i.e., size of the erasable unit/blocks is adjusted when the number of planes is adjusted) (see paragraph 77).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer to include the above mentioned to improve performance of the memory (see Parker, paragraph 60).
With respect claim 17, Palmer teaches a non-transitory computer readable storage medium storing instructions which, when executed, cause a processing device of a storage system controller (see column 22, lines 44-52; “machine readable medium” can include any transitory or non-transitory medium that is capable of storing, encoding, or carrying transitory or non-transitory instructions for execution by the machine 1100 and that cause the machine 1100 to perform any one or more of the techniques of the present disclosure) to:
identify an amount of power to be used by a storage system (see column 6, line 67 and column 7, lines 1-4; each of the memory devices 220-1 to 220-M corresponds to a respective memory channel, which can comprise a group of memory devices. Also in column 15, lines 49-54; determining a power estimate based on the number of active channels and the scheduling of intervals for each command type on each active channel) comprising a plurality of storage devices comprising multiplane dies (see column 3, lines 62-67 and column 4, lines 1-4; memory device 110 includes a memory controller 115 and a memory array 120 including, for example, a number of individual memory device. Also in column 6, lines 19-36; memory array 120 can include one or more memory devices. The individual memory devices can include several memory cells arranged in, for example, a number of devices, planes;
adjust a number of planes of one or more of the multiplane dies used concurrently for accessing data (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) such that a power usage of the storage system is less than or equal to the amount of power(see column 15, lines 53-63; the estimate can be compared to a power budget to provide a power budget error. At 807, the number of active channels can be adjusted to reduce the power budget error. For example, if the power budget error indicates the memory device is using more power than allowed by the power budget, the number of channels can be reduced to reduce power usage).
Palmer does not teach in response to adjusting the number of planes, utilize a block size for allocating blocks by combining a set of erase blocks at a same address in separate planes, wherein the block size corresponds to the adjusted number of planes used concurrently for accessing data.
However, Parker teaches wherein two planes 10 for each die 111 are shown in FIG. 4, but the die can include any number of planes, such as 2, 4, 6, 8 or more planes… a superblock 50 comprises one or more blocks 20 striped across each plane 10 of each of the dies 111-1 to 111-N to store data streams. For high performance SSDs, a data stream is written to multiple pages 30 across multiple dies 111 of the superblock 50 simultaneously or concurrently. Similarly, read operation of pages 30 across multiple dies 111 of superblock 50 can be performed simultaneously or concurrently (see paragraphs 42-43); and wherein an erasable unit of superblock 50 of FIG. 4 increases in size with the number of planes (i.e., size of the erasable unit/blocks is adjusted when the number of planes is adjusted) (see paragraph 77).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the storage medium taught by Palmer to include the above mentioned to improve performance of the memory (see Parker, paragraph 60).
Claim(s) 2-6, 10-15 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 11,194,511) and Parker (US 2020/0125294) as applied to claims 1, 9 and 17 above, and further in view of Sinclair (US7,383,375).
With respect claim 2, Palmer and Parker do not teach wherein the processing device is further configured to: move one or more portions from a first erase block to a second erase block, the first erase block having the block size for allocating blocks.
However, Sinclair teaches an adaptive metablock has a variable number of erase blocks. The erase blocks of a metablock may be from fewer than all the planes of the memory array (see column 4, lines 62-65)… where data is relocated, adaptive metablock size may be based on the number of logical groups that contain relocated data (see column 21, lines 31-33). Adaptive logical block 1340 and adaptive metablock 1341 may be formed by copying data from adaptive metablock 1331 in the memory array (i.e., data from erased block in adaptive metablock are moved/copied to another) (see column 17, lines 39-45).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 3, Palmer and Parker do not teach wherein the processing device is further configured to: identify the one or more portions of the first erase block based on metadata, the metadata indicating live data within the first erase blocks.
However, Sinclair teaches complete original metablock may be considered a fully obsolete original metablock when all valid sectors within it have been copied (see column 41, lines 6-11)… If any partially obsolete original metablocks exist 4743 (complete original metablocks) then reduced size metablocks are allocated 4745 as relocated metablocks and valid sectors are copied 4747 until the original block is fully obsolete 4749 (i.e., block with valid data is moved/copied) (see column 42, lines 62-67).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 4, Palmer and Parker do not teach wherein moving one or more portions from the first erase block to the second erase block is performed during a garbage collection operation of the storage system.
However, Sinclair teaches wherein obsolete metablocks 84, 85 are eventually erased and made available again during garbage collection. Combining the updated data sectors 81 with the original sectors may be done when the data is received. Alternatively, sectors of updated data 81 may be written to another location and may be combined with original data at a later time as part of garbage collection (see column 12, lines 15-30).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 5, Palmer and Parker do not teach wherein moving one or more portions from the first erase block to the second erase block is performed during a defragmentation operation of the storage system.
However, Sinclair teaches wherein metablock 1420 becomes full and must be consolidated… uring the first consolidation, only the most recent copy of each sector is copied to new adaptive metablocks 1422-1424. For updated data, the most recent copy comes from adaptive metablock 1420, for data that is not updated the most recent copy comes from adaptive metablock 1410. Consolidation combines data from adaptive metablock 1410 and adaptive metablock 1420 in logical sequence (see column 18, lines 34-46).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 6, Palmer and Parker do not teach wherein the block size is larger than a previous block size.
However, Sinclair teaches wherein adaptive metablock size may be determined based on the nature of the data (control data, data from host) or may be determined based on boundaries within the data, such as boundaries between files (see column 4, lines 45-53)… an adaptive metablock is an example of a metablock that does not have fixed size (i.e., a new block may be larger or smaller than previous one) (see claim 13, lines 13-16 and column 18, lines 34-46).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 10, Palmer and Parker do not teach moving one or more portions from a first erase block to a second erase block, the first erase block having the block size for allocating blocks.
However, Sinclair teaches an adaptive metablock has a variable number of erase blocks. The erase blocks of a metablock may be from fewer than all the planes of the memory array (see column 4, lines 62-65)… where data is relocated, adaptive metablock size may be based on the number of logical groups that contain relocated data (see column 21, lines 31-33). Adaptive logical block 1340 and adaptive metablock 1341 may be formed by copying data from adaptive metablock 1331 in the memory array (i.e., data from erased block in adaptive metablock are moved/copied to another) (see column 17, lines 39-45).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 11, Palmer and Parker do not teach identifying the one or more portions of the first erase block based on metadata, the metadata indicating live data within the first erase blocks.
However, Sinclair teaches complete original metablock may be considered a fully obsolete original metablock when all valid sectors within it have been copied (see column 41, lines 6-11)… If any partially obsolete original metablocks exist 4743 (complete original metablocks) then reduced size metablocks are allocated 4745 as relocated metablocks and valid sectors are copied 4747 until the original block is fully obsolete 4749 (i.e., block with valid data is moved/copied) (see column 42, lines 62-67).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 12, Palmer and Parker do not teach wherein moving one or more portions from the first erase block to the second erase block is performed during a garbage collection operation of the storage system.
However, Sinclair teaches wherein obsolete metablocks 84, 85 are eventually erased and made available again during garbage collection. Combining the updated data sectors 81 with the original sectors may be done when the data is received. Alternatively, sectors of updated data 81 may be written to another location and may be combined with original data at a later time as part of garbage collection (see column 12, lines 15-30).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 13, Palmer and Parker do not teach wherein moving one or more portions from the first erase block to the second erase block is performed during a defragmentation operation of the storage system.
However, Sinclair teaches wherein metablock 1420 becomes full and must be consolidated… uring the first consolidation, only the most recent copy of each sector is copied to new adaptive metablocks 1422-1424. For updated data, the most recent copy comes from adaptive metablock 1420, for data that is not updated the most recent copy comes from adaptive metablock 1410. Consolidation combines data from adaptive metablock 1410 and adaptive metablock 1420 in logical sequence (see column 18, lines 34-46).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 14, Palmer and Parker do not teach wherein the block size is larger than a previous block size.
However, Sinclair teaches wherein adaptive metablock size may be determined based on the nature of the data (control data, data from host) or may be determined based on boundaries within the data, such as boundaries between files (see column 4, lines 45-53)… an adaptive metablock is an example of a metablock that does not have fixed size (i.e., a new block may be larger or smaller than previous one) (see claim 13, lines 13-16 and column 18, lines 34-46).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 15, Palmer teaches wherein the number of planes of the multiplane die used concurrently (see column 3, lines 4-12 and column 27, lines 56-67; plurality of NAND multiple-plane memory arrays, wherein each memory array is configured to process read requests and write requests simultaneously in parallel) for accessing data is increased (see column 12, lines 10-15 and column 13, lines 12-30; a memory controller to arbitrate activation and de-activation of the die of a multiple memory die device to maintain as many active die as possible while still managing power consumption of the memory device to a power budget. In certain examples, the method can be replicated and run in parallel with one or more other similar methods for each active die. At 601, a die can be enabled (i.e., die/planes may be enabled therefore increasing the number of die/planes)).
With respect claim 18, Palmer and Parker do not teach wherein the processing device is further to: move one or more portions from a first erase block to a second erase block, the first erase block having the block size for allocating blocks.
However, Sinclair teaches an adaptive metablock has a variable number of erase blocks. The erase blocks of a metablock may be from fewer than all the planes of the memory array (see column 4, lines 62-65)… where data is relocated, adaptive metablock size may be based on the number of logical groups that contain relocated data (see column 21, lines 31-33). Adaptive logical block 1340 and adaptive metablock 1341 may be formed by copying data from adaptive metablock 1331 in the memory array (i.e., data from erased block in adaptive metablock are moved/copied to another) (see column 17, lines 39-45).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 19, Palmer and Parker do not teach wherein the processing device is further to: identify the one or more portions of the first erase block based on metadata, the metadata indicating live data within the first erase blocks.
However, Sinclair teaches complete original metablock may be considered a fully obsolete original metablock when all valid sectors within it have been copied (see column 41, lines 6-11)… If any partially obsolete original metablocks exist 4743 (complete original metablocks) then reduced size metablocks are allocated 4745 as relocated metablocks and valid sectors are copied 4747 until the original block is fully obsolete 4749 (i.e., block with valid data is moved/copied) (see column 42, lines 62-67).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
With respect claim 20, Palmer and Parker do not teach wherein moving one or more portions from the first erase block to the second erase block is performed during a garbage collection operation of the storage system.
However, Sinclair teaches wherein obsolete metablocks 84, 85 are eventually erased and made available again during garbage collection. Combining the updated data sectors 81 with the original sectors may be done when the data is received. Alternatively, sectors of updated data 81 may be written to another location and may be combined with original data at a later time as part of garbage collection (see column 12, lines 15-30).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Palmer and Parker to include the above mentioned to improve performance of the device (see Sinclair, column 5, lines 2-3 and 13-22).
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 11,194,511) and Parker (US2020/0125294) as applied to claim 1 above, and further in view of Karamcheti et al. (US9,286,002).
With respect claim 8, Palmer and Parker do not teach wherein the processing device is further configured to: write data to a storage device of the plurality of storage devices, wherein different portions of the data are written to different planes of the multiplane dies and wherein a number of different portions is equal to the number of planes.
However, Karamcheti et al. teaches wherein a package is a multi-chip module that includes one or more flash memory dice. Each flash memory die may be composed of flash planes that include constituent blocks of memory cells where data are stored (see column 6, lines 116-19)… the data chunks may be striped across 8 different dice in 8 different packages along with parity encoding to provide the ability to reconstruct the data chunks in the event of the loss of any single die or package (i.e., portion of data is written to different dies) (see column 15, lines 27-30).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Palmer and Parker to include the above mentioned to provide performance improvement and data reliability (see Karamcheti, column 3, lines 43-45 and 56-60).
With respect claim 16, Palmer and Parker do not teach writing data to a storage device of the plurality of storage devices, wherein different portions of the data are written to different planes of the multiplane dies and wherein a number of different portions is equal to the number of planes.
However, Karamcheti et al. teaches wherein a package is a multi-chip module that includes one or more flash memory dice. Each flash memory die may be composed of flash planes that include constituent blocks of memory cells where data are stored (see column 6, lines 116-19)… the data chunks may be striped across 8 different dice in 8 different packages along with parity encoding to provide the ability to reconstruct the data chunks in the event of the loss of any single die or package (i.e., portion of data is written to different dies) (see column 15, lines 27-30).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Parker to include the above mentioned to provide performance improvement and data reliability (see Karamcheti, column 3, lines 43-45 and 56-60).
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection, necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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