Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the preliminary amendment filed on 12/19/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1, 5, 8, 10, and 19 are objected to because of the following informalities: Regarding claim 1, in line 12, “based on the comparison signal,:” appears that it should read as “based on the comparison signal:”.
Regarding claim 5, in line 9, “a second resistor circuit” appears that it should read as “the second resistor circuit”;
in line 11, “the second resister circuit” appears that it should read as “the second resistor circuit”;
in line 14, “wherein the first resistor circuit having one end connected” appears that it should read as “wherein the first resistor circuit has one end connected”.
Regarding claim 8, in line 6-7, “an output terminal of the calibration circuit” appears that it should read as “the output terminal of the calibration circuit”.
Regarding claim 10, in line 3-4, “an output terminal of the first amplifier” appears that it should read as “the output terminal of the first amplifier”.
Regarding claim 19, in line 10, “the calibrating circuit” appears that it should read as “the calibration circuit”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Michal (US Patent US 10,348,185 B1) in view of Zheng et al. (Chinese Patent Application Publication CN 116148744 A, hereinafter “Zheng”). Regarding claim 1, Michal discloses (see Fig. 1 and Fig. 2A-2B) a power circuit (the DC-DC converter and its power management controller) comprising: a voltage conversion circuit (power stage 10 and output filter 20) comprising an inductor (inductor L), the voltage conversion circuit being configured to convert an input voltage (the input voltage VIN) applied to an input node (switching node Nlx) and output an output voltage (Vout) to an output node (output node Nout); a calibration circuit (calibration gain determination circuit 230) comprising a first resistor circuit (first calibration resistor RCAL1) and a second resistor circuit (second calibration resistor RCAL2), the calibration circuit being configured to adjust the first comparison voltage and output a sensing voltage (the gain-adjusted voltage Vsns output by differential amplifier 234); a comparison circuit (comparator 236) configured to generate a comparison signal (the output of comparator 236) based on the sensing voltage (Vsns), a reference voltage (β·VREF), and the output voltage (Vsns being the difference between the gain-adjusted switching voltage VCAL1 and the gain-adjusted output voltage VCAL2, the latter being derived from the output node Nout); and a controller (calibration controller 238) configured to output, based on the comparison signal, a first control signal (the adjustment signal applied to RCAL2) for adjusting a voltage adjustment ratio of the second resistor circuit (incrementing RCAL2) and a second control signal (the adjustment signal applied to RCAL1) for adjusting a resistance of the first resistor circuit (incrementing RCAL1).
Michal does not disclose a sensing circuit configured to output a first comparison voltage corresponding to a direct current (DC) component of an inductor current supplied to the inductor.
However, Zheng teaches (see Fig. 1 and Fig. 5 of Zheng) a sensing circuit (RC-filter inductor-current sensing circuit 2) configured to output a first comparison voltage (actual voltage value VSEN) corresponding to a direct current (DC) component of an inductor current (the inductor current sensed via the DC equivalent resistance DCR) supplied to the inductor (the inductor), see [0002] of Zheng “The RC filter detection method has the advantages of fast detection speed and non-destructive conversion efficiency, but the detected DC gain is equal to the DC equivalent resistance (DCR) of the inductor”.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal to include a sensing circuit configured to output a first comparison voltage corresponding to a DC component of an inductor current supplied to the inductor, as taught by Zheng, because it can help provide lossless inductor-current sensing without a series sense resistor, thereby preserving the conversion efficiency of the DC-DC converter (see [0002] of Zheng) and enabling accurate online current sensing even when the load current fluctuates (see [0014] of Zheng).
Regarding claim 2, Michal discloses (see Fig. 1; output filter 20) the inductor (L) having one end connected to the input node (switching node Nlx), a first resistor (coil parasitic resistor Rcoil) having one end connected to the other end of the inductor and the other end connected to the output node (Nout), and a first capacitor (output capacitor Cout) having one end connected to the output node.
Michal does not explicitly disclose a second resistor having one end connected to the other end of the first capacitor and the other end connected to a ground node, and a current source having one end connected to the output node and the other end connected to the ground node.
However, the output capacitor (output capacitor Cout) of Michal inherently includes a second resistor (the equivalent series resistance of output capacitor Cout) having one end connected to the other end of the first capacitor and the other end connected to a ground node, and the DC-DC converter of Michal inherently includes a current source (the load to which the converter delivers current) having one end connected to the output node and the other end connected to the ground node, as a DC-DC converter necessarily delivers current to a load.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the second resistor and the current source in the voltage conversion circuit of Michal, because the equivalent series resistance of the output capacitor and the load current of the converter are inherent characteristics of the output network of the DC-DC converter of Michal.
Regarding claim 15, Michal discloses (see Fig. 1, Fig. 2A-2B, and Fig. 3) an operating method of a power circuit (the DC-DC converter) comprising: applying an input voltage (the input voltage VIN) to an input node (switching node Nlx); converting the input voltage by using a voltage conversion circuit (power stage 10 and output filter 20) comprising an inductor (inductor L) and outputting an output voltage (Vout) to an output node (output node Nout); outputting a sensing voltage (the gain-adjusted voltage Vsns output by differential amplifier 234) by adjusting the first comparison voltage by using a calibration circuit (calibration gain determination circuit 230) comprising a first resistor circuit (first calibration resistor RCAL1) and a second resistor circuit (second calibration resistor RCAL2) (Vsns via differential amplifier 234); generating a comparison signal (the output of comparator 236) based on the sensing voltage (Vsns), a reference voltage (β·VREF), and the output voltage (via gain-adjusted output voltage VCAL2 derived from output node Nout) by using a comparison circuit (comparator 236); and outputting, by using a controller (calibration controller 238), a first control signal (the adjustment signal applied to RCAL2) for adjusting a voltage adjustment ratio of the second resistor circuit (RCAL2) and a second control signal (the adjustment signal applied to RCAL1) for adjusting a resistance of the first resistor circuit (RCAL1), based on the comparison signal.
Michal does not disclose outputting, by using a sensing circuit, a first comparison voltage corresponding to a direct current (DC) component of an inductor current supplied to the inductor.
However, Zheng teaches (see Fig. 5 of Zheng) outputting, by using a sensing circuit (RC-filter inductor-current sensing circuit 2), a first comparison voltage (VSEN) corresponding to a direct current (DC) component of an inductor current (sensed via the DCR) supplied to the inductor (the inductor), see [0002] of Zheng “the detected DC gain is equal to the DC equivalent resistance (DCR) of the inductor”.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Michal to include outputting, by using a sensing circuit, a first comparison voltage corresponding to a DC component of an inductor current, as taught by Zheng, because it can help provide lossless inductor-current sensing without a series sense resistor, preserving the conversion efficiency of the DC-DC converter (see [0002] of Zheng).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Michal in view of Zheng, and further in view of Jong et al. (US Patent Application Publication US 2022/0376620 A1, hereinafter “Jong”).
Regarding claim 3, Michal does not disclose wherein the sensing circuit comprises: a third resistor having one end connected to one end of the inductor; a second capacitor having one end connected to the other end of the third resistor and the other end connected to the output node; a fourth resistor having one end connected to the other end of the third resistor; and a third capacitor having one end connected to the other end of the fourth resistor and the other end connected to the output node.
However, Jong teaches (see Fig. 5) a sensing circuit (the RC low-pass sensing network of Fig. 5) comprising a third resistor (R1) having one end connected to one end of the inductor, a second capacitor (C1) having one end connected to the other end of the third resistor and the other end connected to the output node, a fourth resistor (R3) having one end connected to the other end of the third resistor, and a third capacitor (C3) having one end connected to the other end of the fourth resistor and the other end connected to the output node, the third resistor and second capacitor and the fourth resistor and third capacitor forming a two-pole low-pass filter (the two cascaded RC sections R1-C1 and R3-C3) that extracts the DC component of the inductor current.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal so that the sensing circuit comprises the third resistor, second capacitor, fourth resistor, and third capacitor arranged as taught by Jong, because it can help provide increased attenuation of the switching ripple and thereby a more accurate representation of the DC component of the inductor current.
Regarding claim 4, Michal does not disclose wherein the sensing circuit outputs a voltage applied to opposite ends of the third capacitor as the first comparison voltage to the calibration circuit.
However, Jong teaches (see Fig. 5) wherein the sensing circuit outputs a voltage applied to opposite ends of the third capacitor (the voltage across C3) as the first comparison voltage (VSEN) to the calibration circuit (the downstream calibration stage).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal to output the voltage across the third capacitor as the first comparison voltage, as taught by Jong, because it can help provide the filtered DC component of the inductor current at the voltage across the second-pole capacitor.
Claims 5, 6, 7, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Michal in view of Zheng, and further in view of Cleveland et al. (US Patent Application Publication US 2012/0133347 A1, hereinafter “Cleveland”).
Regarding claim 5, Michal does not disclose wherein the calibration circuit comprises: a fifth resistor having one end connected to the output node; a first amplifier having a first input terminal connected to the other end of the fifth resistor and a second input terminal connected to a node whose voltage corresponds to a sum of the output voltage and the first comparison voltage, the first amplifier being configured to output a second comparison voltage; a second resistor circuit configured to output the sensing voltage by adjusting a third comparison voltage generated by filtering the second comparison voltage; and a first resistor circuit connected between the first input terminal and the output terminal of the first amplifier.
However, Cleveland teaches (see Fig. 6) a fifth resistor (the input resistor to the gain stage) having one end connected to the output node, a first amplifier (operational transconductance amplifier 522) having a first input terminal (the input of OTA 522 receiving the sensed voltage) connected to the other end of the fifth resistor and a second input terminal (the other input of OTA 522) connected to a node (the summing node at the OTA input) whose voltage corresponds to a sum of the output voltage and the first comparison voltage, the first amplifier being configured to output a second comparison voltage (the output of OTA 522); a second resistor circuit (variable resistor 624 with tuning capacitor 526) configured to output the sensing voltage by adjusting a third comparison voltage (the filtered voltage at the pole node) generated by filtering the second comparison voltage; and a first resistor circuit (variable resistor 630) connected between the first input terminal and the output terminal of the first amplifier.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal so that the calibration circuit comprises the fifth resistor, first amplifier, first resistor circuit, and second resistor circuit as taught by Cleveland, because it can help tune the sensed current signal in-circuit to reduce the effects of component tolerances and to adapt to changing operating conditions, by providing an input gain stage and independently adjustable gain-setting and pole-setting resistors (see [0034] of Cleveland).
Regarding claim 6, Michal does not disclose wherein the first resistor circuit comprises: a plurality of pull-up resistors connected in series between the first input terminal of the first amplifier and the output terminal of the first amplifier; and a plurality of pull-up switches connected in parallel to the plurality of pull-up resistors, respectively, each pull-up switch being configured to be turned on or off in response to the second control signal.
However, Zheng teaches (see Fig. 5) a resistor matrix (second resistor matrix RSEN) comprising a plurality of pull-up resistors connected in series (the series resistors of RSEN) and a plurality of pull-up switches connected in parallel with the resistors (the parallel switches of RSEN), each switch being turned on or off in response to the second control signal (the calibration control code applied to RSEN) (see [0011] of Zheng “the second resistance matrix RSEN is composed of a second initial resistance RK0 and a plurality of second resistance circuits arranged in series, and each of the second resistance circuits includes a switch connected in parallel with the resistors”.)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal so that the first resistor circuit comprises a plurality of series-connected pull-up resistors with respective parallel pull-up switches controlled by the second control signal, as taught by Zheng, because it can help provide a digitally adjustable resistance for online calibration of the current-sense gain to compensate for component tolerances and variation of the inductor DC resistance (see [0002] and [0014] of Zheng).
Regarding claim 7, Michal does not disclose wherein the controller outputs the second control signal for turning on at least one of the plurality of pull-up switches to the first resistor circuit, based on an increase ratio of the first comparison voltage by the first resistor circuit.
However, Zheng teaches (see Fig. 6 and Fig. 7) a controller (inductance current calibration controller module 3) that outputs a control signal (the gain-calibration adjustment signal) for turning on at least one of a plurality of switches (the switches of the gain-setting second resistor matrix RSEN, corresponding to the first resistor circuit) based on an increase ratio of the first comparison voltage (see [0019] of Zheng “By comparing VSEN and the target value, it is known that the DC gain is too large at this time, and K is adjusted by successive approximation”.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the controller of Michal to turn on at least one of the pull-up switches of the first resistor circuit based on an increase ratio of the first comparison voltage, as taught by Zheng, because it can help calibrate the current-sense gain to a target value by adjusting the gain-setting resistance based on the magnitude of the sensed signal (see [0019] of Zheng).
Regarding claim 10, Michal does not disclose wherein the calibration circuit further comprises: a second amplifier having a first input terminal connected to the output terminal of the first amplifier and a second input terminal connected to an output terminal of the second amplifier; a first filter capacitor connected between the output terminal of the first amplifier and a ground node; and a second filter capacitor connected between the output terminal of the second amplifier and the ground node.
However, Cleveland teaches (see Fig. 6) a second amplifier (operational amplifier 628 configured as a unity-gain buffer) having a first input terminal (the input of buffer 628) connected to the output terminal of the first amplifier and a second input terminal (the feedback input of buffer 628) connected to an output terminal of the second amplifier (the output of buffer 628); a first filter capacitor (tuning capacitor 526) connected between the output terminal of the first amplifier and a ground node; and a second filter capacitor (a low-pass filter capacitor at the buffer output) connected between the output terminal of the second amplifier and the ground node.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the second amplifier and the first and second filter capacitors in the calibration circuit of Michal as taught by Cleveland, because it can help decouple the input gain stage from the filter so that the pole frequency and the DC gain can be adjusted independently (see [0033] of Cleveland).
Regarding claim 16, Michal does not disclose wherein the outputting of the sensing voltage comprises: outputting a second comparison voltage by adjusting the first comparison voltage by using the first resistor circuit; and outputting the sensing voltage by adjusting a third comparison voltage by using the second resistor circuit, the third comparison voltage being generated by filtering the second comparison voltage.
However, Cleveland teaches (see Fig. 6) outputting a second comparison voltage (the amplified voltage at the output of OTA 522) by adjusting the first comparison voltage by using a first resistor circuit (variable resistor 630 setting the DC gain of the input gain stage 522); and outputting the sensing voltage by adjusting a third comparison voltage (the filtered voltage at the pole node) by using a second resistor circuit (variable resistor 624), the third comparison voltage being generated by filtering the second comparison voltage (the low-pass filtering at buffer 628 with tuning capacitor 526).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Michal so that the outputting of the sensing voltage comprises adjusting the first comparison voltage with the first resistor circuit and adjusting a filtered third comparison voltage with the second resistor circuit, as taught by Cleveland, because it can help adjust the pole frequency and the DC gain independently to accurately measure the inductor current, by separately adjusting the gain and the filtered output (see [0033] of Cleveland).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Michal in view of Zheng and Cleveland, and further in view of Hughes (US Patent Application Publication US 2008/0252378 A1).
Regarding claim 8, Michal does not disclose wherein the second resistor circuit comprises: a plurality of pull-down resistors connected in series between the output terminal of the first amplifier and a ground node; and a plurality of pull-down switches, each pull-down switch being connected between one end of a corresponding one of the plurality of pull-down resistors and an output terminal of the calibration circuit.
However, Hughes teaches (see Fig. 2) a plurality of pull-down resistors (resistors RS1-RSN) connected in series between a first node and a second node (the output terminal of the first amplifier and a ground node), and a plurality of pull-down switches (switches S1-SN), each pull-down switch being connected between one end of a corresponding one of the plurality of pull-down resistors and an output terminal of the calibration circuit (the tap node coupled to resistor RSPAN), the switches being turned on or off in response to a control signal (GAIN TRIM SETTING).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal so that the second resistor circuit comprises a plurality of series-connected pull-down resistors with respective pull-down switches connecting the resistor string to the output terminal of the calibration circuit, as taught by Hughes, because it can help trim the voltage adjustment ratio of the current-sense path for accurate gain by providing a digitally controlled potentiometer (see [0048] of Hughes).
Regarding claim 9, Michal does not disclose wherein the controller outputs the first control signal for turning on one of the plurality of pull-down switches to the second resistor circuit, based on a reduction ratio of the third comparison voltage by the second resistor circuit.
However, Zheng teaches (see Fig. 6 and Fig. 7) a controller (inductance current calibration controller module 3) that outputs a control signal (the pole-calibration adjustment signal) for turning on one of a plurality of switches (the switches of the pole-setting first resistor matrix RS, corresponding to the second resistor circuit) based on a reduction ratio of the third comparison voltage (the AC slope of VSEN compared to the reference) (see [0019] of Zheng “First calibrate the AC gain, by comparing the slopes of the two, adjust RS to change the pole position”.)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the controller of Michal to turn on one of the pull-down switches of the second resistor circuit based on a reduction ratio of the third comparison voltage, as taught by Zheng, because it can help calibrate the current-sense path by adjusting the pole-setting resistance based on the sensed signal (see [0019] of Zheng).
Claims 11, 12, 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Michal in view of Zheng, and further in view of Hastings et al. (US Patent US 5,600,234, hereinafter “Hastings”).
Regarding claim 11, Michal does not disclose wherein the comparison circuit comprises a comparator configured to receive the sensing voltage through a first input terminal thereof, receive the reference voltage through a second input terminal thereof, receive the output voltage through a third input terminal thereof, and output the comparison signal through an output terminal thereof.
However, Hastings teaches (see Fig. 1 and Fig. 3) a comparison circuit (the summing-comparator-based comparison stage) comprising a comparator (summing comparator 14; summing comparator 76) configured to receive the sensing voltage through a first input terminal thereof (the input terminal coupled to current sense element 98), receive the reference voltage through a second input terminal thereof (the terminal coupled to reference voltage Vref), receive the output voltage through a third input terminal thereof (the terminal coupled to the output port through first feedback circuit 78), and output the comparison signal through an output terminal thereof (the control-signal output terminal).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal so that the comparison circuit comprises a comparator configured to receive the sensing voltage, the reference voltage, and the output voltage through respective input terminals and output the comparison signal, as taught by Hastings, because it can help provide a fast transient response and feedforward correction of line and load variations while maintaining an accurate dc operating point, by combining the current-sense voltage with the output voltage and the reference voltage in a summing comparator.
Regarding claim 12, Michal does not disclose wherein the comparison signal has a first value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0, and a second value when the value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is less than or equal to 0.
However, Hastings teaches (see Fig. 1 and Fig. 3) that the comparison signal (the control signal output by summing comparator 14) has a first value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0 (when the weighted sum at the positive input (the sensing voltage) exceeds the weighted sum at the negative inputs (the reference voltage and the output voltage)), and a second value when the value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is less than or equal to 0 (when the weighted sum at the positive input (the sensing voltage) is less than the weighted sum at the negative inputs (the reference voltage and the output voltage)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the comparison signal of Michal to have a first value when the value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0 and a second value otherwise, as taught by Hastings, because it can help establish the trip point that regulates the converter, by comparing the sensing voltage against the combined reference and output voltages.
Regarding claim 13, Michal does not disclose wherein the controller outputs the first control signal for reducing a voltage adjustment ratio of the second resistor circuit to the second resistor circuit when the comparison signal is the first value, and wherein the controller outputs the second control signal for increasing a resistance of the first resistor circuit to the first resistor circuit when the comparison signal is the second value.
However, Michal teaches (see Fig. 2A) that the calibration controller (238) adjusts the calibration resistors (first calibration resistor RCAL1 and second calibration resistor RCAL2) in the direction that drives the sensing voltage toward the target defined by the reference voltage. Hastings further teaches (see Fig. 1) the comparison signal taking the first value or the second value according to the sign of the difference between the sensing voltage and the sum of the reference voltage and the output voltage.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the controller of Michal to reduce the voltage adjustment ratio of the second resistor circuit when the comparison signal is the first value and to increase the resistance of the first resistor circuit when the comparison signal is the second value, as taught by Michal and Hastings, because it can help null the difference between the sensing voltage and the combined reference and output voltages, thereby calibrating the sensing voltage, by adjusting the resistor circuits in the direction indicated by the comparison signal.
Regarding claim 17, Michal does not disclose wherein the comparison signal has a first value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0, and a second value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is less than 0.
However, Hastings teaches (see Fig. 1 and Fig. 3) that the comparison signal (the control signal output by summing comparator 14) has a first value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0 (when the weighted sum at the positive input (the sensing voltage) exceeds the weighted sum at the negative inputs (the reference voltage and the output voltage)), and a second value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is less than 0 (when the weighted sum at the positive input (the sensing voltage) is less than the weighted sum at the negative inputs (the reference voltage and the output voltage)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Michal so that the comparison signal has a first value when the value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0 and a second value otherwise, as taught by Hastings, because it can help establish the trip point that regulates the converter, by comparing the sensing voltage against the combined reference and output voltages.
Regarding claim 18, Michal does not disclose wherein the outputting of the second control signal to the first resistor circuit and the first control signal to the second resistor circuit comprises: outputting the first control signal for reducing a voltage adjustment ratio of the second resistor circuit to the second resistor circuit when the comparison signal is the first value; and outputting the second control signal for increasing a resistance of the first resistor circuit to the first resistor circuit when the comparison signal is the second value.
However, Michal teaches (see Fig. 2A) that the calibration controller (238) adjusts the calibration resistors (first calibration resistor RCAL1 and second calibration resistor RCAL2) in the direction that drives the sensing voltage toward the target defined by the reference voltage. Hastings further teaches (see Fig. 1) the comparison signal taking the first value or the second value according to the sign of the difference between the sensing voltage and the sum of the reference voltage and the output voltage. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Michal to output the first control signal for reducing the voltage adjustment ratio of the second resistor circuit when the comparison signal is the first value and to output the second control signal for increasing the resistance of the first resistor circuit when the comparison signal is the second value, as taught by Michal and Hastings, because it can help null the difference between the sensing voltage and the combined reference and output voltages, by adjusting the resistor circuits in the direction indicated by the comparison signal.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Michal in view of Jong and Cleveland.
Regarding claim 19, Michal discloses (see Fig. 1 and Fig. 2A-2B) a power circuit (the DC-DC converter and its power management controller) comprising: a voltage conversion circuit (power stage 10 and output filter 20) comprising an inductor (inductor L), a first resistor (coil parasitic resistor Rcoil), a first capacitor (output capacitor Cout), and a second resistor (the equivalent series resistance of output capacitor Cout), the voltage conversion circuit being configured to convert an input voltage (the input voltage VIN) applied to an input node (switching node Nlx) and output an output voltage (Vout) to an output node (output node Nout); a calibration circuit (calibration gain determination circuit 230) being configured to adjust the first comparison voltage (the sensed voltage) and output a sensing voltage (Vsns); a comparison circuit (the comparison stage of circuit 230) comprising a comparator (comparator 236) configured to generate a comparison signal (the output of comparator 236) based on the sensing voltage (Vsns), a reference voltage (β·VREF), and the output voltage (via the gain-adjusted output voltage derived from output node Nout); and a controller (calibration controller 238) configured to output a first control signal (the adjustment signal applied to RCAL2) for adjusting a voltage adjustment ratio of the second resistor circuit (RCAL2) and a second control signal (the adjustment signal applied to RCAL1) for adjusting a resistance of the first resistor circuit (RCAL1), based on the comparison signal.
Michal does not disclose a sensing circuit comprising a third resistor, a second capacitor, a fourth resistor, and a third capacitor, the sensing circuit being configured to output a first comparison voltage corresponding to a direct current (DC) component of an inductor current.
However, Jong teaches (see Fig. 5) a sensing circuit (the RC low-pass sensing network of Fig. 5) comprising a third resistor (R1), a second capacitor (C1), a fourth resistor (R3), and a third capacitor (C3), the sensing circuit being configured to output a first comparison voltage (the voltage across C3) corresponding to a direct current (DC) component of an inductor current (the inductor current of the converter). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal to include a sensing circuit comprising a third resistor, a second capacitor, a fourth resistor, and a third capacitor, the sensing circuit being configured to output a first comparison voltage corresponding to a direct current (DC) component of an inductor current, as taught by Jong, because a two-pole sensing filter can help provide increased attenuation of the switching ripple so as to extract the DC component of the inductor current.
Michal does not disclose a calibration circuit comprising a fifth resistor, a first amplifier, a first resistor circuit, and a second resistor circuit.
However, Cleveland teaches (see Fig. 6) a calibration circuit (the tunable complementary filter and gain-calibration network of Fig. 6) comprising a fifth resistor (the input resistor coupling the sensed voltage to the first amplifier), a first amplifier (operational transconductance amplifier 522 configured as an input gain stage), a first resistor circuit (variable resistor 630 setting the DC gain), and a second resistor circuit (variable resistor 624 setting the pole), the first and second resistor circuits being adjusted by a controller (microcontroller 908).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal to include a calibration circuit comprising a fifth resistor, a first amplifier, a first resistor circuit, and a second resistor circuit, as taught by Cleveland, because it can help adjust the sensed current signal in-circuit to reduce the effects of component tolerances and to adapt to changing operating conditions of the converter (see [0034] of Cleveland).
Claims 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Michal in view of Jong and Cleveland, and further in view of Hastings.
Regarding claim 25, Michal does not disclose wherein the comparator receives the sensing voltage through a first input terminal thereof, receives the reference voltage through a second input terminal thereof, receives the output voltage through a third input terminal thereof, and outputs the comparison signal through an output terminal thereof, wherein the comparison signal has a first value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0, and a second value when the value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is less than 0.
However, Hastings teaches (see Fig. 1 and Fig. 3) a comparator (summing comparator 14; 76) that receives the sensing voltage through a first input terminal thereof (coupled to current sense element 98), receives the reference voltage through a second input terminal thereof (coupled to reference voltage Vref), receives the output voltage through a third input terminal thereof (coupled to the output port through first feedback circuit 78), and outputs the comparison signal through an output terminal thereof (the control-signal output terminal), wherein the comparison signal has a first value when a value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is greater than 0 (when the weighted sum at the positive input (the sensing voltage) exceeds the weighted sum at the negative inputs (the reference and output voltages)), and a second value when the value obtained by subtracting the reference voltage and the output voltage from the sensing voltage is less than 0 (when the weighted sum at the positive input (the sensing voltage) is less than the weighted sum at the negative inputs (the reference and output voltages)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal so that the comparator receives the sensing voltage, the reference voltage, and the output voltage through respective input terminals and outputs the comparison signal having the first value or the second value according to the sign of the difference between the sensing voltage and the sum of the reference voltage and the output voltage, as taught by Hastings, because it can help provide a fast transient response and feedforward correction while maintaining an accurate dc operating point.
Regarding claim 26, Michal does not disclose wherein the controller is configured to output the first control signal for reducing a voltage adjustment ratio of the second resistor circuit to the second resistor circuit when the comparison signal is the first value, and the second control signal for increasing a resistance of the first resistor circuit to the first resistor circuit when the comparison signal is the second value.
However, Michal teaches (see Fig. 2A) that the calibration controller (238) adjusts the calibration resistors (first calibration resistor RCAL1 and second calibration resistor RCAL2) in the direction that drives the sensing voltage toward the target defined by the reference voltage. Hastings further teaches (see Fig. 1) the comparison signal taking the first value or the second value according to the sign of the difference between the sensing voltage and the sum of the reference voltage and the output voltage. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power circuit of Michal to output the first control signal for reducing the voltage adjustment ratio of the second resistor circuit when the comparison signal is the first value and to output the second control signal for increasing the resistance of the first resistor circuit when the comparison signal is the second value, as taught by Michal and Hastings, because it can help null the difference between the sensing voltage and the combined reference and output voltages, by adjusting the resistor circuits in the direction indicated by the comparison signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0313380 A1 discloses current sensing in a DC/DC converter including a calibration to reduce variations in inductor DC Resistance (DCR).
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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