DETAILED ACTION
This action is in response to the amendments and remarks filed 04/06/2026, in which claims 1 and 29 have been amended, and claims 1-6, 8-22 and 28-29 are pending and ready for examination.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02 FEBRUARY 2026, 15 MAY 2026, 17 JUNE 2026 is/are in compliance with the provisions of 37 CFR 1.97 and has/have been considered. An initialed copy of Form 1449 is enclosed herewith.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0076728 A1 (hereinafter “Prakash”) in view of US 2017/0030890 A1 (hereinafter “Holweg”).
Regarding Claim 12 Prakash discloses a method of separating one or more ions from a solution using an electrically charged conductive membrane filter, the method comprising:
providing a conductive membrane filter 110/210; [0034]-[0036], [0046].
feeding the mixture solution through the conductive membrane filter; and
separating the one or more ions from the mixture solution into a permeate solution [0034], [0043], [0050], Examples; Figs. 1A-4.
Prakash does not disclose wherein the conductive membrane filter is formed by: etching holes into a surface of a silicon wafer, wherein the holes do not extend the entire thickness of the membrane; and etching pores to extend from the holes to an opposite surface of the wafer, producing a selective membrane layer between the end of the holes and an opposite surface of the wafer, wherein the pores in the selective membrane layer have a diameter of about 1 nm to 500 nm and are smaller than the size of the holes in the silicon wafer.
However, with regard to the membrane Prakash discloses the membrane used may be “reverse osmosis (RO) membranes, nanofiltration (NF) membranes, ultrafiltration (UF) membranes, and microfiltration (MF) membranes”, and may be “formed from metals” [0049]. Further, Holweg discloses similar membrane filtration system for electrically conductive membrane separation [0138]-[0141], including a method of making a conductive membrane filter, the method comprising:
etching holes 120 into a conductive surface (which may be of a silicon wafer [0053]-[0055]), wherein the holes do not extend the entire thickness of the membrane; and
etching pores 152 to extend from the holes to an opposite surface of the wafer, producing a selective membrane layer 150 between the end of the holes and an opposite surface of the wafer,
wherein the pores in the selective membrane layer are smaller than the size of the holes in the silicon wafer; Figs. 10A-11, [0109]-[0117], multiple holes shown in Fig. 27-29.
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the process of Prakash by substituting for the conductive membrane filter an etched-pore monolithic silicon conductive membrane as made by the method disclosed by Holweg because this involves the simple substitution of known conductive membranes used in fluid separation to obtain the predictable result of forming a successful conductive membrane separation system.
Thus in the combined invention, one would use the method and materials of Holweg (monolithic wafer silicon that is etched) to form a membrane suitable for the appatus and processes of Prakash, i.e. having the pore size(s) of the membrane disclosed by Prakash, using etching means known in the art, so the system can achieve the filtration separations as disclosed. Thus it is obvious for the membrane of the combined invention to have pore sizes for microfiltration (pores greater than 0.1 micron), ultrafiltration (pores between 2-100 nm), nanofiltration (pores between 1-2 nm) or reverse osmosis filtration (pores less than 1 nm), Prakash [0034], [0046]-[0048]; i.e. which have pore size ranges which overlap those claimed. While Holweg discloses a membrane for microfiltration, and would thus be obvious to have “pores greater than 0.1 micron” as disclosed by Prakash, the pore size of Holweg not seen to be limiting to the combined invention, since it is not Holweg’s overall apparatus or process that is being modified and there is no teaching away from the pore sizes being in the ranges used by Prakash.
Since the range(s) disclosed overlaps the range(s) claimed, the range(s) recited in the claim is/are considered prima facie obvious. Overlapping ranges are prima facie evidence of obviousness. It would have been obvious to one having ordinary skill in the art to have selected the portion of the disclosed range(s) that corresponds to the claimed range. See MPEP 2144.05(I).
Regarding Claim 2 Prakash in view of Holweg discloses the method of claim 1, wherein the holes in the silicon wafer are etched using deep reactive ion etching; Holweg [0113].
Regarding Claim 3 Prakash in view of Holweg discloses the method of claim 2, further comprising using an etching mask in the deep reactive ion etching to control a geometry (and therefore also the density) of the holes in the silicon wafer Holweg [0113], wherein the masking layer may be SiO2 Holweg [0095].
Regarding Claim 4 Prakash in view of Holweg discloses the method of claim 3, wherein no gap is disclosed between the SiO2 etching mask and the silicon wafer range, and is thus inherently 0 μm; Holweg Figs. 10A-11, [0109]-[0117].
Regarding Claim 16 Prakash in view of Holweg discloses the method of claim 1, wherein the holes in the silicon wafer are discleod to be rectangular and have a length from 10-1000 microns; Holweg [0152]. Though circular holes (i.e. with a diameter) are not specially disclosed, this would involve a simple change in shape which would have been obvious for use in applications requiring circular membranes such as in order to fit circular membrane holders.
Regarding Claim 17 Prakash in view of Holweg discloses the method of claim 1, wherein the holes in the silicon wafer have a depth (H2) of 100 nm to 20 micron Holweg [0152].
Regarding Claim 18 Prakash in view of Holweg discloses the method of claim 1, wherein the substrate/silicon wafer has a thickness of 30-1000 micron Holweg [0079].
Since the range disclosed overlaps the range claimed, the range recited in the claim is considered prima facie obvious. Overlapping ranges are prima facie evidence of obviousness. It would have been obvious to one having ordinary skill in the art to have selected the portion of the disclosed range that corresponds to the claimed range. See MPEP 2144.05(I).
Regarding Claim 19 Prakash in view of Holweg discloses the method of claim 1, wherein the silicon wafer is conductive or semiconductive Holweg [0055],[0065], and thus may inherently have a resistivity in the range claimed, as semiconductors are well-known to have a resistivity range from 10-4 to 108 cm-ohm.
Since the range disclosed overlaps the range claimed, the range recited in the claim is considered prima facie obvious. Overlapping ranges are prima facie evidence of obviousness. It would have been obvious to one having ordinary skill in the art to have selected the portion of the disclosed range that corresponds to the claimed range. See MPEP 2144.05(I).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Prakash in view of Holweg in view of F. Laerme, et al, "Bosch deep silicon etching: improving uniformity and etch rate for advanced MEMS applications," Technical Digest. IEEE International MEMS 99 Conference. Twelfth IEEE International Conference on Micro Electro Mechanical Systems (Cat. No.99CH36291), Orlando, FL, USA, 1999, pp. 211-216, doi: 10.1109/MEMSYS.1999.746812. (hereinafter “Laerme”).
Regarding Claim 5 Prakash in view of Holweg discloses the method of claim 2, wherein a conventional Bosch process is used to perform a fast, anisotropic etch at rates ranging from about 1 μm/min to 30 μm/min.
However Laerme discloses Bosch deep silicon etching using reactive ions is a known means for anisotropic etching silicon in MEMS applications achieving high etch rates of 6 microns/min and improved etch uniformity; Abstract, Results, Conclusions
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the method of Prakash in view of Holweg by using to form the holes the Bosch deep silicon etching process disclosed by Laerme because involves the simple substitution of known deep reactive ion etching processes used for silicon to obtain the predictable result of forming deep cavities in silicon, and because the Bosch process results in high etch rates and improved etch uniformity.
Claims 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash in view of Holweg further in view of US 2019/0312112 A1 (hereinafter “Smith”).
Regarding Claims 6 and 8 Prakash in view of Holweg discloses the method of claim 1, but does not disclose (claim 6) wherein the pores in the selective membrane layer are etched using MACE, or (claim 8) further comprising sputtering the silicon wafer with metal catalyst nanoparticles.
However Smith discloses a method of forming pores in a semiconductor (silicon) material using metal-assisted chemical etching (MACE), wherein the semiconductor (such as a silicon wafer) is sputtered with metal catalyst nanoparticles in order to direct etching of pores from the nanoparticles [0131]-[0132], [0141], [0145], [0163]-[0168].
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the method of Prakash in view of Holweg by forming the pores in the membrane via the MACE process of Smith which involves sputtering the silicon wafer with metal catalyst nanoparticles, because this involves the simple substitution of known means for forming pores in a silicon membrane via etching to obtain the predictable result of forming pores in silicon to create a membrane.
Regarding Claim 9 Prakash in view of Holweg and Smith discloses the method of claim 8, wherein the metal catalyst nanoparticles comprise silver (Ag), gold (Au), or platinum (Pt); Smith [0135].
Regarding Claim 10 Prakash in view of Holweg and Smith discloses the method of claim 8, wherein the metal catalyst nanoparticles have a diameter of about 2 nm or 4.4 nm Smith [0168].
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash in view of Holweg and Smith and further in view of Rickard Gunnarsson, Iris Pilch, Robert D. Boyd, Nils Brenning, Ulf Helmersson; The influence of pressure and gas flow on size and morphology of titanium oxide nanoparticles synthesized by hollow cathode sputtering. J. Appl. Phys. 28 July 2016; 120 (4): 044308. (hereinafter “Gunnarsson”)
Regarding Claim 11-13 Prakash in view of Holweg and Smith discloses the method of claim 8, but does not disclose (claim 11) wherein the sputtering occurs in a chamber at a base pressure of about 6 x 10-4 Torr, (Claim 12) wherein Argon (Ar) gas is introduced into the chamber after approximately 5 minutes of vacuum pump-down, then increased from about 5 to 12 seem, or (claim 13) wherein the chamber is then maintained at a pressure of about 5 mTorr to 30 mTorr.
However Gunnarsson discloses the pressure and gas flow used during sputtering effect the formed nanoparticles morphology and size (at least Title, Abstract, Conclusions).
Sputtering chamber base pressure, sputtering argon pressure and argon flow, as well as pump down pressure, are thus variables which achieve a recognized result, and it would therefore have been obvious for one of skill in the art to optimize these variables through routine experimentation, by using values including those within the scope of the present claims, so as to produce desired end results. See MPEP § 2144.05 (B).
Regarding Claim 14 Prakash in view of Holweg, Smith and Gunnarsson discloses the method of claim 13, wherein a power applied to the silicon wafer during sputtering may be 15 W, 30 W, 45 W (Smith Table 1, [0208]-[0209]) or 150 W, [0165].
Regarding Claim 15 Prakash in view of Holweg, Smith and Gunnarsson discloses the method of claim 14, wherein sputter deposition times may be 2 or 4 seconds; Table 1, [0208]-[0209].
Claims 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash in view of Holweg further in view of US 2016/0158706 A1 (hereinafter “Wang”).
Regarding Claims 20-22 Prakash in view of Holweg discloses the method of claim 1, but does not disclose further comprising depositing a layer comprising a metal oxide on the selective membrane layer of the silicon wafer through atomic layer deposition (ALO).
However Wang discloses a method for forming a membrane having a silicon substrate formed via etching, wherein the membrane’s pores are coated in a material via atomic layer deposition (ALD), which may be 1 nm to 10 microns thick and comprise the metal oxides TiO2 or Al2O3, in order to control the pore size of the membrane via narrowing the pores by the metal oxide coating “in order to adjust the size of pores according to the application” [0027]-[0028], [0045].
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the method of Prakash in view of Holweg by including a 1 nm to 10 microns thick TiO2 or Al2O3 layer deposited on the membrane via ALD as disclosed by Wang in order to adjust the size of pores according to the application.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Prakash in view of Holweg, and US 2012/0234694 Al (hereinafter “Vecitis”).
Regarding Claim 28 Prakash in view of Holweg discloses the method of claim 1, but does not disclose wherein the solution separated is an acidic solution.
With regard to the solution being separated is an acidic solution, Vecitis discloses a similar membrane filtration system for electrically conductive membrane separation, Abstract, [0003], [0008], [0029], [0097], [0214], [0221], [0222]; including a method of conductive membrane separation wherein one or more ions are separated from a solution, wherein that solution may include formic acid, acetic acid, or be an aqueous fluid including an electrolyte where the electrolyte may be an acid [0225]-[0241], and discloses at least one example of filtering an solution with a pH of 6.3, i.e. an acidic solution [0045], [0374], [0380], and includes adjusting pH of the solution [0207].
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the method of Prakash in view of Holweg by separating an acidic solution as disclosed by Vecitis because similar electrically conductive membrane separation methods are used to treat acidic solutions and thus this involves the simple substitution of known solutions which are separated by similar electrically conductive membrane separation methods to obtain the predictable result of performing a successful separation.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Prakash in view of Holweg, Smith, and Vecitis.
Regarding Claim 29 Prakash discloses a method of separating one or more ions from a solution using an electrically charged conductive membrane filter, the method comprising:
providing a conductive membrane filter 110/210; [0034]-[0036], [0046].
feeding the mixture solution through the conductive membrane filter; and
separating the one or more ions from the mixture solution into a permeate solution [0034], [0043], [0050], Examples; Figs. 1A-4.
Prakash does not disclose (1) wherein the conductive membrane filter is formed by: etching holes into a surface of a silicon wafer, wherein the holes do not extend the entire thickness of the membrane; and etching pores using metal-assisted chemical etching to extend from the holes to an opposite surface of the wafer, producing a selective membrane layer between the end of the holes and an opposite surface of the wafer, wherein the pores in the selective membrane layer have a diameter of about 1 nm to 500 nm and are smaller than the size of the holes in the silicon wafer, or (2) wherein the solution is an acidic solution.
However, with regard to (1) the membrane, Prakash discloses the membrane used may be “reverse osmosis (RO) membranes, nanofiltration (NF) membranes, ultrafiltration (UF) membranes, and microfiltration (MF) membranes”, and may be “formed from metals” [0049]. Further, Holweg discloses a similar membrane filtration system for electrically conductive membrane separation [0138]-[0141], including a method of making a conductive membrane filter, the method comprising:
etching holes 120 into a conductive surface (which may be of a silicon wafer [0053]-[0055]), wherein the holes do not extend the entire thickness of the membrane; and
etching pores 152 to extend from the holes to an opposite surface of the wafer, producing a selective membrane layer 150 between the end of the holes and an opposite surface of the wafer,
wherein the pores in the selective membrane layer are smaller than the size of the holes in the silicon wafer; Figs. 10A-11, [0109]-[0117], multiple holes shown in Fig. 27-29.
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the process of Prakash by substituting for the conductive membrane filter an etched-pore monolithic silicon conductive membrane as made by the method disclosed by Holweg because this involves the simple substitution of known conductive membranes used in fluid separation to obtain the predictable result of forming a successful conductive membrane separation system.
Thus in the combined invention, one would use the method and materials of Holweg (monolithic wafer silicon that is etched) to form a membrane suitable for the appatus and processes of Prakash, i.e. having the pore size(s) of the membrane disclosed by Prakash, using etching means known in the art, so the system can achieve the filtration separations as disclosed. Thus it is obvious for the membrane of the combined invention to have pore sizes for microfiltration (pores greater than 0.1 micron), ultrafiltration (pores between 2-100 nm), nanofiltration (pores between 1-2 nm) or reverse osmosis filtration (pores less than 1 nm), Prakash [0034], [0046]-[0048]; i.e. which have pore size ranges which overlap those claimed. While Holweg discloses a membrane for microfiltration, and would thus be obvious to have “pores greater than 0.1 micron” as disclosed by Prakash, the pore size of Holweg not seen to be limiting to the combined invention, since it is not Holweg’s overall apparatus or process that is being modified and there is no teaching away from the pore sizes being in the ranges used by Prakash.
Since the range(s) disclosed overlaps the range(s) claimed, the range(s) recited in the claim is/are considered prima facie obvious. Overlapping ranges are prima facie evidence of obviousness. It would have been obvious to one having ordinary skill in the art to have selected the portion of the disclosed range(s) that corresponds to the claimed range. See MPEP 2144.05(I).
Prakash in view of Holweg does not disclose (1a) the etching of the pores is by metal-assisted chemical etching, or (2) wherein the solution is an acidic solution.
However, with regard to (1a) metal-assisted chemical etching, Smith discloses a method of forming pores in a semiconductor (silicon) material using metal-assisted chemical etching (MACE), wherein the semiconductor (such as a silicon wafer) is sputtered with metal catalyst nanoparticles in order to direct etching of pores from the nanoparticles, in order to form pores less than 15 nm [0131]-[0132], [0141], [0145], [0163]-[0168].
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the method of Prakash in view of Holweg by forming pores in the membrane via the MACE process of Smith which involves sputtering the silicon wafer with metal catalyst nanoparticles, because this involves the simple substitution of known means for forming pores in a silicon membrane via etching to obtain the predictable result of forming pores in silicon to create a membrane. Since Smith discloses the pores formed are less than 15 nm it would therefore have been obvious to use pore ranges of from 5-15 nm, i.e. a smaller subset of the ranges disclosed by Prakash.
With regard to (2) the solution being separated is an acidic solution, Vecitis discloses a similar membrane filtration system for electrically conductive membrane separation, Abstract, [0003], [0008], [0029], [0097], [0214], [0221], [0222]; including a method of conductive membrane separation wherein one or more ions are separated from a solution, wherein that solution may include formic acid, acetic acid, or be an aqueous fluid including an electrolyte where the electrolyte may be an acid [0225]-[0241], and discloses at least one example of filtering an solution with a pH of 6.3, i.e. an acidic solution [0045], [0374], [0380], and includes adjusting pH of the solution [0207].
Therefore, before the effective filing date, it would have been prima facie obvious to one of ordinary skill in the art to modify the method of Prakash in view of Holweg and Smith by separating an acidic solution as disclosed by Vecitis because similar electrically conductive membrane separation methods are used to treat acidic solutions and thus this involves the simple substitution of known solutions which are separated by similar electrically conductive membrane separation methods to obtain the predictable result of performing a successful separation.
Response to Arguments
Applicant's arguments filed 04/06/2026 have been fully considered, but they are now largely moot because they are directed to grounds of rejection which are no longer cited in the current action and the new limitations of the amended claims which had not been previously addressed. See the updated rejection above citing a new combination of references to address the amended claims.
In response to Applicants’ argument that Holweg is non-analogous art; the Examiner disagrees. Applicants’ argue that Holweg is directed to blood separation, which is “a fundamentally different mechanism” from the “charge-selective electrochemical transport” filtration process disclosed by Applicants, however Holweg is not limited to blood filtration [0138]. Further, MPEP 2141.01(a), states that “a reference is analogous art to the claimed invention if: (1) the reference is from the same field of endeavor as the claimed invention (even if it addresses a different problem); OR (2) the reference is reasonably pertinent to the problem faced by the inventor (even if it is not in the same field of endeavor as the claimed invention)”. Holweg and Applicants’ invention are all related as to the same field of endeavor, etched silicone membranes for fluid separations, they need not be related further to more specific problems addressed by Applicants'.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC J MCCULLOUGH/ Examiner, Art Unit 1773
/BENJAMIN L LEBRON/ Supervisory Patent Examiner, Art Unit 1773
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