DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 14 and 16-17 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagarajan et al. (US 20190097640).
PNG
media_image1.png
548
795
media_image1.png
Greyscale
PNG
media_image2.png
785
902
media_image2.png
Greyscale
With respect to claim 1, Nagarajan et al. (US 20190097640) discloses a charge pump, applied in a phase-locked loop (fig. 1 element 101), wherein the phase-locked loop has a locked state, the charge pump comprises: a discharging circuit (234) and a charging circuit (233), both the discharging circuit and the charging circuit are connected to an output terminal of the charge pump (235), the discharging circuit decreases a current of the output terminal under control of a first control signal (281), the charging circuit increases the current of the output terminal under control of a second control signal (280), the first control signal and the second control signal correspond to error signals between the two clock signals (REF and PLLoutput), and the charge pump further comprises a voltage control circuit (240), wherein: the voltage control circuit is connected to a first node (235 and or ground) in the discharging circuit and/or a second node in the charging circuit (235 and or Vsup) to maintain the locked state of the phase-locked loop by controlling a voltage of a corresponding node (VDC voltage node); wherein both the first node and the second node are connected to the output terminal (terminal going into 254).
With respect to claim 2, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 1, wherein the discharging circuit comprises the first node (at switch 234), and a first switch transistor (234) positioned between the first node and the output terminal (254); and the voltage control circuit (203) comprises a first control circuit (291) connected to the first node, and the first control circuit controls a turned-on speed of the first switch transistor (234) by adjusting a voltage of the first node when the discharging circuit does not decrease the current of the output terminal (constant current source).
With respect to claim 3, Nagarajan et al. (US 20190097640) discloses charge pump according to claim 1, wherein the charging circuit comprises the second node (connected to switch 233), and a second switch transistor (233) positioned between the second node and the output terminal (254); and the voltage control circuit (203) comprises a second control circuit (290) connected to the second node, and the second control circuit controls a turned-on speed of the second switch transistor (233) by adjusting a voltage of the second node when the charging circuit does not increase the current of the output terminal (constant current source).
With respect to claim 4, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 3, wherein the first control circuit comprises a first charge buffer (241 or 242 can be considered first charge buffer) and a first control transistor in series, the first charge buffer stores charges, an input terminal of the first control transistor (233 or 234) is connected to an output terminal of the first charge buffer (241 or 242 considered charge buffer with output terminal at 254), an output terminal of the first control transistor (234) is connected to the first node (at switch 234), a control terminal of the first control transistor is configured to receive the first control signal (from 281), and the first control transistor (234) acts as a switch to discharge the charges stored in the first charge buffer (241 or 242 considered charge buffer with output terminal at 254) to the first node; and the second control circuit comprises a second charge buffer (250 or 242) and a second control transistor in series (234 in series with 233), the second charge buffer (241 or 242 considered charge buffer with output terminal at 254) stores charges, an input terminal of the second control transistor (231) is connected to an output terminal of the second charge buffer (241 or 242 considered charge buffer with output terminal at 254), an output terminal of the second control transistor (231) is connected to the second node (connected to switch 233), a control terminal of the second control transistor (231) is configured to receive the second control signal, and the second control transistor (231) acts as a switch to discharge the charges stored in the second charge buffer (241 or 242 can be considered first charge buffer) to the second node.
With respect to claim 6, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 1, wherein the voltage control circuit comprises a charge buffer (241) and a control transistor in series (234), the charge buffer stores charges, and an input terminal of the control transistor is connected to an output terminal of the charge buffer (241 or 242 considered charge buffer with output terminal at 254); an output terminal of the control transistor is connected to the first node (at 234) , a control terminal of the control transistor is configured to receive the first control signal (from 291), and the control transistor acts as a switch to discharge the charges stored in the charge buffer to the first node; or an output terminal of the control transistor is connected to the second node, a control terminal of the control transistoris configured to receive the second control signal, and the control transistor acts as a switch to discharge the charges stored in the charge buffer to the second node. (Here, the conditions following or need not be met as the first conditions are deemed to be met.)
With respect to claim 14, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 2, wherein the charging circuit comprises the second node, and a second switch transistor (233) positioned between the second node and the output terminal (254); and the voltage control circuit (203) comprises a second control circuit (290) connected to the second node, and the second control circuit (290) controls a turned-on speed of the second switch transistor by adjusting a voltage of the second node (at switch 233 ) when the charging circuit does not increase the current of the output terminal.
With respect to claim 16, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 4, wherein the first charge buffer is an amplifier (250 can be considered first charge buffer) or a capacitor (241 or 242 can be considered first charge buffer), and the second charge buffer is an amplifier (250 can be considered second charge buffer) or a capacitor.
With respect to claim 17, N discloses the charge pump according to claim 3, wherein the charge pump further comprises a comparator (250), a first input terminal of the comparator is connected to the output terminal of the charge pump (at 254), and an output terminal of the comparator is connected to a control terminal (Vsup is also considered a control terminal of the second switch transistor. Here Vsup connected via R2 through 218, 219 and 217 is considered the same Vsup connected to 233 through 231) of the second switch transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8-9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagarajan et al. (US 20190097640).
With respect to claim 8, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 1, wherein net charges output by the charge pump during a locked period of the phase-locked loop are 0 or approximately 0. (Here, the charge lock can be 0 and is within the scope of the invention). (See [0031], “in the art. In alternative embodiments, the charge pump 230 may be any configuration which outputs current pulses based on the input.”)
With respect to claim 9, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 1, wherein the voltage control circuit (203) adjusts turned-on speeds of the charging (233) circuit and/or the discharging circuit (234) such that the charging circuit and the discharging circuit are simultaneously turned on (See [0031], “in the art. In alternative embodiments, the charge pump 230 may be any configuration which outputs current pulses based on the input.”).
With respect to claim 15, Nagarajan et al. (US 20190097640) discloses the charge pump according to claim 14, wherein a transistor type of the first switch transistor is different from that of the second switch transistor. (Here, it is within the scope to vary the switch transistor types. (See [0031] “It is to be appreciated that there are many charge pump configurations known in the art. In alternative embodiments, the charge pump 230 may be any configuration which outputs current pulses based on the input.” )
Allowable Subject Matter
Claims 5, 7, 10-13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, the prior art of record fails to suggest or disclose the charge pump according to claim 4, wherein the first control circuit further comprises a first current source (232) and a first adjustable resistor in series, an input terminal of the first current source is connected to a power supply voltage terminal, an output terminal of the first current source is connected to a first terminal of the first adjustable resistor, a second terminal of the first adjustable resistor is connected to a ground terminal, a third terminal of the first adjustable resistor is connected to a first input terminal of the first charge buffer, a second input terminal of the first charge buffer is connected to the output terminal of the first charge buffer, and the output terminal of the first charge buffer is connected to the input terminal of the first control transistor; and the second control circuit further comprises a second current source and a second adjustable resistor in series, an input terminal of the second current source is connected to a power supply voltage terminal, an output terminal of the second current source is connected to a first terminal of the second adjustable resistor, a second terminal of the second adjustable resistor is connected to the ground terminal, a third terminal of the second adjustable resistor is connected to a first input terminal of the second charge buffer, a second input terminal of the second charge buffer is connected to the output terminal of the second charge buffer, and the output terminal of the second charge buffer is connected to the input terminal of the second control transistor.
Here, the configuration and connections associated with the adjustable resistor is not present in the prior art.
With respect to claim 7, the prior art of record fails to suggest or disclose the charge pump according to claim 6, wherein the voltage control circuit further comprises a current source and an adjustable resistor in series, an input terminal of the current source is connected to a power supply voltage terminal, an output terminal of the current source is connected to a first terminal of the adjustable resistor, a second terminal of the adjustable resistor is connected to a ground terminal, a third terminal of the adjustable resistor is connected to a first input terminal of the charge buffer, and a second input terminal of the charge buffer is connected to the output terminal of the charge buffer.
Here, the configuration and connections associated with the adjustable resistor is not present in the prior art.
With respect to claim 10, the prior art of record fails to suggest or disclose a phase-locked loop, comprising a phase frequency detector, a charge pump, a loop filter, an oscillator and a; wherein: the phase frequency detector is respectively connected to an input terminal of the phase-locked loop an output terminal of the divider to receive two clock signals , and an output terminal of the phase frequency detector is connected to an input terminal of the charge pump; an output terminal of the charge pump is connected to an input terminal of the loop filter, an output terminal of the loop filter is connected to an input terminal of the oscillator, and an output terminal of the oscillator is connected to an input terminal of the divider; wherein the charge pump comprises the charge pump according to claim 1.
Here, the configuration and connections associated with the loop filter is not present in the prior art.
With respect to claims 11-13 and 18, these claims are allowable based on their dependence on claim 10．
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAREEM E ALMO/Examiner, Art Unit 2849