DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2024 is/are compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim(s) 11 and 19 is/are objected to because of the following informalities:
In claim(s) 11 and 19, line 2, “[…] based on MIPI Display Serial Interface” should read “[…] based on MIPI (Mobile Industry Processor Interface) Display Serial Interface”.
Appropriate correction is required.
Office Action Summary
Claim(s) 21-40 is/are canceled.
Claim(s) 2-11 and 13-20 is/are rejected under 35 U.S.C. 112(b).
Claim(s) 1-8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1).
Claim(s) 9, 13-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1), further in view of Morin (US 2009/0225189 A1).
Claim(s) 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1), further in view of Canini et al (US 2025/0097572 A1).
Claim(s) 11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1), further in view of Lee et al (US 2016/0328882 A1).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2-11 and 13-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 2-11 recites the limitation "the main image sensor" in claim 1, from which claim(s) 2-11 directly or indirectly depend, does not provide antecedent basis for “the main image sensor”. Claim 1 instead recites “a first image sensor”. Thus, it is unclear whether “the main image sensor” recited in claim(s) 2-11 refers to the “first image sensor” of claim 1 or to a different image sensor.
Similarly, Claim(s) 13-20 recites the limitation "the main image sensor" in claim 12, from which claim(s) 13-20 directly or indirectly depend, does not provide antecedent basis for “the main image sensor”. Claim 12 instead recites “a first image sensor”. Thus, it is unclear whether “the main image sensor” recited in claim(s) 13-20 refers to the “first image sensor” of claim 12 or to a different image sensor. For purposes of examination, the Examiner interprets “the main image sensor” recited in claim(s) 2-11 and 13-20 as referring to the respective “first image sensor” recited in claims 1 and 12.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1).
Regarding claim(s) 1, Lee teaches a first image sensor comprising:
a first interface configured to receive first parameter information from a processor (Paragraph [0086]: “The first image sensor 230-1 may include the I2C channel 231 connected with the processor 120, a first GPIO 232 connected with the processor 120, and a second GPIO 233 connected with the second image sensor 230-2. The first image sensor 230-1 may receive the first parameter information from the processor 120 through the I2C channel 231”);
a second interface configured to transmit (Paragraph [0086]: “The first image sensor 230-1 may include the I2C channel 231 connected with the processor 120, a first GPIO 232 connected with the processor 120, and a second GPIO 233 connected with the second image sensor 230-2”; and Paragraph [0087]: “The first image sensor 230-1 may further include a micro controller unit (MCU) which is not shown, and the MCU may determine a time to transmit the reflection signal to the second image sensor 230-2”),
wherein the first image sensor is configured to provide a first field of view (FOV) and the second image sensor is configured to provide a second FOV (Paragraph [0053]: “the plurality of lens assemblies 210 may have the same lens attribute (e.g., view angle, focal length, auto-focusing, f number, or optical zoom), or at least one lens assembly may have one or more lens attributes different from those of another lens assembly. The lens assembly 210 may include, for example, a wide-angle lens or a telephoto lens”; and Paragraph [0059]: “the electronic device 101 may include two or more camera modules 180 having different attributes or functions. In such a case, at least one camera module may be, for example, a wide-angle camera or a front camera and at least another camera module may be a telephoto camera or a rear camera”).
Lee fails to teach an encoder configured to encode the first parameter information; and a second interface configured to transmit the encoded first parameter information to a second image sensor; wherein the processor is included in a first chip and the second image sensor is included in a second chip.
However, Crook teaches teach an encoder configured to encode the first parameter information (Figure 4A-4B; Paragraph [0051] – Paragraph [0052]: “The transfer of information from master camera module 12A to slave camera module 12B may use an interface such as a uni-directional interface (UDI) that uses a serial protocol to transfer information […] The per-frame data transferred from a master camera module 12A to a slave camera module 12B may include many bytes encoded in this way […] In FIG. 4B, an illustrative encoding for transferring a UDI data byte is shown. The UDI data byte may have a start bit set to logic zero, an event bit set to logic zero to identify the byte as a data byte, and data bits b0-b7 containing eight bits of information to be transferred”; and Paragraph [0020]: “The image processing circuitry 16 in each camera module 12 may calculate algorithm values (e.g., by using algorithm metrics). Algorithm values may sometimes be referred to herein as image capture parameters and may include, as examples, an exposure setting, a gain setting, a color temperature setting, a framerate setting, an ambient brightness value, and a color correction setting”); and
a second interface configured to transmit the encoded first parameter information to a second image sensor (Paragraph [0021]: “Camera modules 12 that are operated for stereoscopic vision applications may be programmed to transfer information such as the algorithm values from image processing circuitry 16 in a particular camera module (e.g., image processing circuitry 16A in camera module 12A) to other camera modules (e.g., image processing circuitry 16B in camera module 12B). Camera modules 12 may transfer information to other camera modules 12 and may receive information from other camera module 12 via paths 40”),
wherein the processor is included in a first chip and the second image sensor is included in a second chip (Figure 6B; Paragraph [0019]: “In a typical arrangement, which is sometimes referred to as a system on chip or SOC arrangement, camera sensor 14 and image processing and data formatting circuitry 16 are implemented on a common integrated circuit. The use of a single integrated circuit to implement camera sensor 14 and image processing and data formatting circuitry 16 can help to minimize costs”; and Paragraph [0066]: “In FIG. 6B, SOC 60A may be configured as a master camera module […] and a single SOC 60B may be configured as a slave camera module [...] the master camera module may use the UDI protocol to communicate with the slave camera module over path 40”).
Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Lee to include an encoder configured to encode the first parameter information and to transmit the encoded first parameter information from the first image sensor to the second image sensor, as taught by Crook. The motivation for this combination of references would have been to use a single set of algorithm values to configure settings for each sensor module of camera modules (Crook, Paragraph [0020]). This motivation for the combination of Lee and Crook is/are supported by KSR exemplary rationale (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. MPEP 2141 (III).
Regarding claim(s) 2, Lee as modified by Crook teaches the main image sensor of claim 1, where Lee teaches wherein the second interface is further configured to transmit a synchronization signal (Paragraph [0168] – Paragraph [0171]: “The processor 120 may transmit the reflection signal instructing to reflect the first parameter information to the first image sensor 230-1 through the signal line 127. The first image sensor 230-1 may receive the reflection signal instructing to reflect the first parameter information from the processor 120 through the first GPIO 232 […] The first image sensor 230-1 may determine a time to transmit the reflection signal, based on a delay time at which the second parameter information is transmitted to the second image sensor 230-2 […] In operation 1307, the first image sensor 230-1 of the electronic device 101 may transmit the reflection signal to the second image sensor 230-2 […] That is, when the first image sensor 230-1 and the second image sensor 230-2 receive the parameter information, respectively, at different times, the times to reflect the parameter may be synchronized with each other […] by the reflection signal transmitted from the processor 120”), and Crook further teaches wherein the second interface is further configured to transmit a synchronization signal together with the encoded first parameter information to the second image sensor (Paragraph [0050] – Paragraph [0051]: “To assist in synchronization between master camera module 12A and slave camera module 12B, master camera module 12A may prioritize the transfer of event information over the transfer of other data […] The transfer of information from master camera module 12A to slave camera module 12B may use an interface such as a uni-directional interface (UDI) that uses a serial protocol to transfer information […] The per-frame data transferred from a master camera module 12A to a slave camera module 12B may include many bytes encoded in this way”; and Paragraph [0053]: “The UDI event byte may have an event bit set to logic one […] Data bits b0-b3 of the UDI event byte may contain a holdoff count representing the delay between the occurrence of an event and the transfer of the UDI event byte corresponding to the event. Data bits b4-b7 of the UDI event byte may contain information describing the type of event that occurred”).
Regarding claim(s) 3, Lee as modified by Crook teaches the main image sensor of claim 2, wherein the second interface is further configured to transmit the synchronization signal to the second image sensor at each reference time (where Lee teaches in Figure 7; Paragraph [0129]: “in operation 701, the first image sensor 230-1 of the electronic device 101 may receive parameter information (for example, first parameter information) from the processor 120 at the N-th frame. The first image sensor 230-1 may receive the first parameter information through the I2C channel 231 at the N-th frame”; and Paragraph [0133]: “In operation 705, the first image sensor 230-1 of the electronic device 101 may transmit a reflection signal including the reflection time to the slave image sensor (for example, the second image sensor 230-2) at the N+1-th frame […] The first image sensor 230-1 may receive the first parameter information at the N-th frame and may transmit the reflection signal at the N+1-th frame”; and where Crook further teaches in Paragraph [0070] – Paragraph [0071]: “The master camera module may calculate algorithm values for use with the next frame (e.g., frame N+1) during the operations of step 102 (e.g., after the internal frame start for frame N) […] During the operations of step 104, the calculated algorithm values may be transferred from the master camera module to the slave camera module using the UDI protocol. If an event occurs during the operations of step 104 (e.g., a delay-sensitive internal start of exposure signal), the operations of step 106 may be performed. Once the transfer of all calculated algorithm values for the next frame is complete, the master may move to the next frame (e.g., N=N+1, as shown by step 114)”; and Paragraph [0073]: “During the operations of step 108, the master camera module may transmit an event byte at the start of the next byte transmission that corresponds to the event that occurred”).
Regarding claim(s) 4, Lee as modified by Crook teaches the main image sensor of claim 2, wherein the second interface is further configured to transmit the synchronization signal and the encoded first parameter information to the second image sensor at each reference time (where Lee teaches in Paragraph [0169] – Paragraph [0171]: “The first image sensor 230-1 may determine a time to transmit the reflection signal, based on a delay time at which the second parameter information is transmitted to the second image sensor 230-2 […] In operation 1307, the first image sensor 230-1 of the electronic device 101 may transmit the reflection signal to the second image sensor 230-2 […] That is, when the first image sensor 230-1 and the second image sensor 230-2 receive the parameter information, respectively, at different times, the times to reflect the parameter may be synchronized with each other […] by the reflection signal transmitted from the processor 120”; and where Crook further teaches in (Paragraph [0050] – Paragraph [0053]: “To assist in synchronization between master camera module 12A and slave camera module 12B, master camera module 12A may prioritize the transfer of event information over the transfer of other data […] The transfer of information from master camera module 12A to slave camera module 12B may use an interface such as a uni-directional interface (UDI) that uses a serial protocol to transfer information […] The per-frame data transferred from a master camera module 12A to a slave camera module 12B may include many bytes encoded in this way […] In FIG. 4B, an illustrative encoding for transferring a UDI data byte is shown. The UDI data byte may have a start bit set to logic zero, an event bit set to logic zero to identify the byte as a data byte, and data bits b0-b7 containing eight bits of information to be transferred […] The UDI event byte may have an event bit set to logic one […] Data bits b0-b3 of the UDI event byte may contain a holdoff count representing the delay between the occurrence of an event and the transfer of the UDI event byte corresponding to the event. Data bits b4-b7 of the UDI event byte may contain information describing the type of event that occurred”).
Regarding claim(s) 5, Lee as modified by Crook teaches the main image sensor of claim 2, where Crook teaches wherein the second interface is further configured to transmit the synchronization signal and the encoded first parameter information to a third image sensor (Figure 6B-6C; Figure 7; Paragraph [0066]: “The arrangement of FIG. 6B may be extended to accommodate additional slave cameras configured and controlled in topology where there UDI circuitry is connected in a daisy-chain topology”; Paragraph [0067]: “In FIG. 6C, SOC 60A may be configured as a master camera module […] and two or more SOCs 60B may be configured as slave camera modules […] The master camera module may use the UDI protocol to communicate with the slave camera modules over path 40”; and Paragraph [0069]: “The flow chart of FIG. 7 illustrates a process by which a master camera module may calculate algorithm values, transfer the algorithm values to one or more slave camera modules, and transfer information describing events that occur during the transfer of algorithm values”).
Regarding claim(s) 6, Lee as modified by Crook teaches the main image sensor of claim 2, where Crook teaches further comprising:
a third interface configured to transmit the synchronization signal and the encoded first parameter information to a third image sensor (Paragraph [0063]: “System on chips (SOCs) with UDI circuitry similar to that described may be used in various configurations. In the examples of FIG. 6A-6D, each system on chip (SOC) 60 may contain respective UDI circuitry 62. The UDI circuitry 62 may be used to implement a UDI protocol”; and Paragraph [0067]: “In FIG. 6C, SOC 60A may be configured as a master camera module […] and two or more SOCs 60B may be configured as slave camera modules […] The master camera module may use the UDI protocol to communicate with the slave camera modules over path 40”).
Regarding claim(s) 7, Lee as modified by Crook teaches the main image sensor of claim 1, where Crook teaches wherein the first parameter information comprises at least one of a frame size, a frame line length, a frame rate, exposure time, or readout time (Paragraph [0020]: “Algorithm values may sometimes be referred to herein as image capture parameters and may include, as examples, an exposure setting, a gain setting, a color temperature setting, a framerate setting, an ambient brightness value, and a color correction setting”).
Regarding claim(s) 8, Lee as modified by Crook teaches the main image sensor of claim 1, where Lee teaches wherein the first FOV is greater than the second FOV (Figure 2; Paragraph [0053]: “The lens assembly 210 may include, for example, a wide-angle lens or a telephoto lens”; and Paragraph [0059]: “According to an embodiment, the electronic device 101 may include two or more camera modules 180 having different attributes or functions. In such a case, at least one camera module may be, for example, a wide-angle camera or a front camera and at least another camera module may be a telephoto camera or a rear camera”).
Regarding claim(s) 12, Lee teaches a first image sensor comprising:
a first interface configured to receive first parameter information at a first time and receive second parameter information from a processor at a second time different from the first time (Figure 7; and Paragraph [0129]: “Referring to FIG. 7, in operation 701, the first image sensor 230-1 of the electronic device 101 may receive parameter information (for example, first parameter information) from the processor 120 at the N-th frame. The first image sensor 230-1 may receive the first parameter information through the I2C channel 231 at the N-th frame”); and
a second interface configured to transmit the first parameter information or information on the first parameter information at a third time and transmit the second parameter information or information on the second parameter information at a fourth time different from the third time to a second image sensor (Figure 7; Paragraph [0133]: “In operation 705, the first image sensor 230-1 of the electronic device 101 may transmit a reflection signal including the reflection time to the slave image sensor (for example, the second image sensor 230-2) at the N+1-th frame. The reflection signal may be generated at the first image sensor 230-1 or may be received from the processor 120. The first image sensor 230-1 may receive the first parameter information at the N-th frame and may transmit the reflection signal at the N+1-th frame”; and Paragraph [0126]: “In operation 605, the first image sensor 230-1 of the electronic device 101 may transmit the reflection signal including the reflection time to a slave image sensor (for example, the second image sensor 230-2). The reflection signal may be generated at the first image sensor 230-1 or may be received from the processor 120. The first image sensor may transmit the reflection signal through the GPIO 233 physically connected with the second image sensor 230-2”), and
wherein the first image sensor is configured to provide a first field of view (FOV) and the second image sensor is configured to provide a second FOV (Paragraph [0003]: “The two or more lenses may be configured to have the same viewing angle/aperture, or may be configured to have different viewing angles/apertures”; and Paragraph [0059]: “According to an embodiment, the electronic device 101 may include two or more camera modules 180 having different attributes or functions. In such a case, at least one camera module may be, for example, a wide-angle camera or a front camera and at least another camera module may be a telephoto camera or a rear camera”).
Lee fails to teach wherein the processor is included in a first chip and the second image sensor is included in a second chip. However, Crook further teaches a second interface configured to transmit the first parameter information or information on the first parameter information at a third time and transmit the second parameter information or information on the second parameter information at a fourth time different from the third time to a second image sensor (Paragraph [0044]: “The master camera module 12A of a master-slave pair used for a 3D video imaging application may transfer algorithm values to the slave camera module 12B of the master-slave pair for each frame generated”; and Paragraph [0047]: “At time t4 […] master camera module 12A may begin to calculate algorithm values (e.g. auto algorithm values) for use with the next frame (n+1) […] At time t5, master camera module 12A may complete calculation of algorithm values and initiate transfer of the calculated algorithm values to slave module 12B […] At time t8, master camera module 12A may complete the transfer of calculated algorithm values and slave camera module 12B may begin to deploy the transferred algorithm values for the next frame (n+1)”), and
wherein the processor is included in a first chip and the second image sensor is included in a second chip (Figure 6B; Paragraph [0019]: “In a typical arrangement, which is sometimes referred to as a system on chip or SOC arrangement, camera sensor 14 and image processing and data formatting circuitry 16 are implemented on a common integrated circuit. The use of a single integrated circuit to implement camera sensor 14 and image processing and data formatting circuitry 16 can help to minimize costs”; and Paragraph [0066]: “In FIG. 6B, SOC 60A may be configured as a master camera module […] and a single SOC 60B may be configured as a slave camera module [...] the master camera module may use the UDI protocol to communicate with the slave camera module over path 40”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee in view of Crook such that parameter information received from a processor at different times is transmitted to a second image sensor at different times, and the processor and the second image sensor are implemented in respective chips, because Crook teaches transferring algorithm values between master and slave camera modules on a frame-by-frame basis and implementing the camera modules in separate SOCs. The motivation for this combination of references would have been to synchronize operating parameters between multiple image sensors on a frame-by-frame basis while providing an integrated multi-camera implementation using separate SOCs. This motivation for the combination of Lee and Crook is/are supported by KSR exemplary rationale (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. MPEP 2141 (III).
Claim(s) 9, 13-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1), further in view of Morin (US 2009/0225189 A1).
Regarding claim(s) 9, Lee as modified by Crook teaches the main image sensor of claim 1, but do not specifically teach wherein the first parameter information relates to a region of interest of the main image sensor. However, Morin teaches wherein the first parameter information relates to a region of interest of the main image sensor (Paragraph [0020]: “In one embodiment image sensor 105 has a sensor controller 110 that includes a region of interest (ROI) configuration controller 112. The ROI configuration controller 112 is responsible for setting image sensor parameters such as pixel exposure time, gain, and resolution of the pixels within each ROI […] In one embodiment, two or more different ROIs can each have image sensor parameters independently set to improve image recognition reliability […]”; and Paragraph [0022]: “In one embodiment, image processor 150 includes an image analyzer 155 to analyze image data received from image sensor 105. A ROI analyzer 160 identifies ROIs within an image and generates control parameters for each ROI that are sent to sensor controller 110 via bus 135 to adjust sensor parameters in ROIs in subsequent frames”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee as modified by Crook in view of Morin such that the first parameter information relates to a region of interest of the first image sensor, because Morin teaches independently controlling image sensor parameters, including resolution, exposure time, and gain, for identified regions for interest. The motivation for this combination of references would have been to improve image recognition reliability while reducing the amount of pixel data generated and associated processing requirements by selectively controlling image sensor parameters within regions of interest. This motivation for the combination of Lee, Crook, and Morin is/are supported by KSR exemplary rationale (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. MPEP 2141 (III).
Regarding claim(s) 13, Lee as modified by Crook teaches the main image sensor of claim 12, but do not specifically teach wherein the second interface is configured to transmit information on a region of interest of the main image sensor based on the first parameter information to the second image sensor. However, Morin teaches wherein the second interface is configured to transmit information on a region of interest of the main image sensor based on the first parameter information to the second image sensor (Paragraph [0020]: “In one embodiment image sensor 105 has a sensor controller 110 that includes a region of interest (ROI) configuration controller 112. The ROI configuration controller 112 is responsible for setting image sensor parameters such as pixel exposure time, gain, and resolution of the pixels within each ROI […] In one embodiment, two or more different ROIs can each have image sensor parameters independently set to improve image recognition reliability […]; and Paragraph [0022]: “In one embodiment, image processor 150 includes an image analyzer 155 to analyze image data received from image sensor 105. A ROI analyzer 160 identifies ROIs within an image and generates control parameters for each ROI that are sent to sensor controller 110 via bus 135 to adjust sensor parameters in ROIs in subsequent frames”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee as modified by Crook in view of Morin such that information on a region of interest of the first image sensor, based on the first parameter information, is transmitted to the second image sensor, because Morin teaches identifying regions of interest and generating control parameters associated with the identified regions of interest for adjusting image sensor parameters in subsequent frames. The motivation for this combination of references would have been to provide region-specific control of image sensor parameters to improve image recognition reliability by selectively adjusting image sensor operation for identified regions of interest. This motivation for the combination of Lee, Crook, and Morin is/are supported by KSR exemplary rationale (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. MPEP 2141 (III).
Regarding claim(s) 14, Lee as modified by Crook and Morin teaches main image sensor of claim 13, where Crook teaches wherein the second interface is configured to transmit a synchronization signal together with the information on the region of interest to the second image sensor (Paragraph [0050]: “Delay-sensitive events may occur during transfer of data from master camera module 12A and slave camera module 12B. An internal start of exposure signal may be asserted at time t7 while master camera module 12A is transferring calculated algorithm values to slave camera module 12B (as an example). To assist in synchronization between master camera module 12A and slave camera module 12B, master camera module 12A may prioritize the transfer of event information over the transfer of other data […]”; and Paragraph [0051]: “The transfer of information from master camera module 12A to slave camera module 12B may use an interface such as a uni-directional interface (UDI) that uses a serial protocol to transfer information […] The per-frame data transferred from a master camera module 12A to a slave camera module 12B may include many bytes encoded in this way”).
Regarding claim(s) 15, Lee as modified by Crook and Morin teaches the main image sensor of claim 14, where Crook teaches wherein the first parameter information comprises a frame rate of the first image sensor (Paragraph [0020]: “The image processing circuitry 16 in each camera module 12 may calculate algorithm values (e.g., by using algorithm metrics). Algorithm values may sometimes be referred to herein as image capture parameters and may include, as examples, an exposure setting, a gain setting, a color temperature setting, a framerate setting, an ambient brightness value, and a color correction setting. The calculated algorithm values may configure settings for a respective sensor module 14 (e.g., an exposure setting, a gain setting, a color temperature setting, a framerate setting, an ambient brightness value, and a color correction setting)”).
Regarding claim(s) 16, Lee as modified by Crook and Morin teaches the main image sensor of claim 15, where Crook teaches wherein the second interface is configured to transmit the synchronization signal to the second image sensor at each reference time corresponding to the frame rate (Paragraph [0044]: “Captured image frames from each camera module 12 may be generated at fixed time intervals. Camera modules 12 used for a 3D video imaging application may generate captured image frames every 1/30th or 1/60th of a second (as examples). The master camera module 12A of a master-slave pair used for a 3D video imaging application may transfer algorithm values to the slave camera module 12B of the master-slave pair for each frame generated (e.g., the master camera module 12A may transfer a brightness metric to the slave camera module 12B every 1/30 or 1/60 of a second). The number of frames captured by each camera module 12 per second may be referred to as the capture framerate (e.g., 30 frames per second or 60 frames per second)”; Paragraph [0045]: “In the diagram of FIG. 3, the internal start of frame (sometimes referred to herein as ISOF) signal may reflect the start of each frame. In the example of FIG. 3, frame n starts at the ISOF signal at time t2, and frame n+1 starts at the ISOF signal at time t10”; and Paragraph [0049]: “The internal start of exposure signal may reflect the start of exposure for the next frame. For example, the internal start of exposure signal at time t1 during frame n-1 may identify the time at which camera sensor 14A must begin exposure for frame n, the internal start of exposure signal at time t7 during frame n may identify the time at which camera sensor 14A must begin exposure for frame n+1, and the internal start of exposure signal at time t11 may identify the time at which camera sensor 14A must begin exposure for frame n+2 […] To assist in synchronizing master camera module 12A with slave camera module 12B, master camera module 12A may transfer (time-sensitive) event information such as the internal start of exposure signal to slave camera module 12B immediately after the event occurs”).
Regarding claim(s) 17, Lee as modified by Crook and Morin teaches the main image sensor of claim 15, where Lee teaches wherein the first parameter information further comprises a length of a frame line (Paragraph [0081]: “For example, when the first parameter information arrives at the output queue of the I2C channel (for example, the first I2C channel 125, the second I2C channel 126) at the same time without a time gap, and image sensors each requiring only one line in setting an integration time, a frame length line, an analog gain without a waiting time in the transmission queue of the I2C channel are connected to separate I2C channels (for example, the I2C channel 231, the I2C 235) having their respective transmission queues, and are driven, a minimum time required for the parameter information to arrive at the image sensor may be 45.83 ms”).
Regarding claim(s) 20, Lee as modified by Crook and Morin teaches the main image sensor of claim 17, where Morin teaches further comprising:
an encoder configured to identify the region of interest based on the first parameter information and generate the information on the region of interest that indicates the region of the interest (Paragraph [0025]: “FIG. 2 is a high-level flow chart illustrating an exemplary process. An image is analyzed in step 205. ROIs are identified and control signals are generated for the ROIs in step 210. In the image sensor the resolution, exposure time, and gain is adjusted for each ROI in step 215”; and Paragraph [0026]: “Each of the image recognition sub-modules 310, 315, 320, 325, 330, and 335 may, for example, generate an initial determination of a ROI such as a potential license plate, a potential headlight, a potential pedestrian, a potential road sign, a potential stop light, a potential traffic lane, or a potential brake light based on shape and/or other image recognition considerations”).
Claim(s) 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1), further in view of Canini et al (US 2025/0097572 A1).
Regarding claim(s) 10 and 18, Lee as modified by Crook teaches the main image sensor of claim 1, but do not specifically teach wherein the first interface and the second interface are configured to transmit signals based on inter-integrated circuit (I2C). However, Canini teaches wherein the first interface and the second interface are configured to transmit signals based on inter-integrated circuit (I2C) (Paragraph [0022]: “Multiple image sensors 208 may be serially connected using a data bus 219 used for configuring and controlling the sensors 208. The data bus 219 may be an I2C bus that is a standard bidirectional interface that uses a controller or master device, in this case an image sensor 208n, to communicate with slave devices, in this case image sensors 208a-208n-1 […]”; and Paragraph [0023]: “the image sensors 208 may be configured to work in a chain and optionally as master/slave configuration. In this example, image sensor 208n may be configured as master device via I2C/I3C or SPI data bus 219 (i.e., communications channel) and may be responsible for synchronizing the chain of image sensors 208a-208n-1 by generating a system clock (e.g., LVDS system clock) 228 to control timing of the other image sensors 208a-208n-1 that are configured as slave devices”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee as modified by Crook in view of Canini such that the first interface and the second interface are configured to transmit signals based on inter-integrated circuit (I2C), because Canini teaches using an I2C bus as a bidirectional communication interface for configuring, controlling, and communicating between multiple image sensors. The motivation for this combination of references would have been to provide a standardized bidirectional communication interface for efficiently configuring, controlling, and communicating between the interconnected image sensors. This motivation for the combination of Lee, Crook, and Canini is/are supported by KSR exemplary rationale (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. MPEP 2141 (III).
Claim(s) 11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0267295 A1) in view of Crook et al (US 2012/0194712 A1), further in view of Lee et al (US 2016/0328882 A1).
Regarding claim(s) 11 and 19, Lee (“295”) as modified by Crook teaches the main image sensor of claim 1, but do not specifically teach wherein the first interface and the second interface are configured to transmit signals based on MIPI Display Serial Interface. However, Lee (“882”) teaches wherein the first interface and the second interface are configured to transmit signals based on MIPI Display Serial Interface (Paragraph [0046]: “Accordingly, in one implementation, the imaging sensor 114 could output pixel rows in the MIPI DSI format, or, alternatively the display 108 could be configured to accept pixel data in the MIPI CSI format”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee (“295”) as modified by Crook in view of Lee (“882”) such that the first interface and the second interface are configured to transmit signals based on MIPI Display Serial Interface (DSI), because Lee (“882”) teaches configuring an imaging sensor to output pixel data in the MIPI DSI format. The motivation for this combination of references would have been to provide a standardized serial-interface format that enables image-sensor data to be transmitted in a format compatible with downstream devices using the MIPI DSI protocol. This motivation for the combination of Lee (“295”), Crook, and Lee (“882”) is/are supported by KSR exemplary rationale (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention. MPEP 2141 (III).
Relevant Prior Art Directed to State of Art
Kim et al (US 2017/0187928 A1) are relevant prior art not applied in the rejection(s) above. Kim discloses an electronic device comprising: a first image sensor: a second image sensor: and a processor functionally connected to the first image sensor and the second image sensor, the processor being configured to: identify a first operation characteristic of the first image sensor and a second operation characteristic of the second image sensor, change at least one of a first access period of a first row of the first image sensor and a second access period of a second row of the second image sensor, based on a difference between the first operation characteristic and the second operation characteristic, to synchronize the first access period and the second access period, wherein the second row corresponds to the first row, acquire image data corresponding to the first row through the first image sensor based on the synchronized first access period, and acquire image data corresponding to the second row through the second image sensor based on the synchronized second access period.
Zhang et al (US 2024/0403257 A1) are relevant prior art not applied in the rejection(s) above. Zhang discloses a display subsystem comprising: a first physical layer interface configured in accordance with Mobile Industry Processor Interface (MIPI) Alliance display serial interface (DSI) specifications; a second physical layer interface configured in accordance with the MIPI Alliance DSI specifications; and a switch configured to selectively couple a serial data link to the first physical layer interface or to the second physical layer interface as directed by a controller, wherein the controller is configured to: cause first datagrams to be transmitted over the serial data link using the first physical layer interface using a first frequency of operation; configure the second physical layer interface for a second frequency of operation different from the first frequency of operation while the first datagrams are transmitted over the serial data link; cause the first physical layer interface to transmit configuration information over the serial data link using the first frequency of operation after the second physical layer interface has been configured for the second frequency of operation; after the configuration information has been transmitted, idle the serial data link by causing the first physical layer interface to terminate transmissions over the serial data link, cause the switch to decouple the first physical layer interface from the serial data link, and cause the switch to couple the second physical layer interface to the serial data link; and cause second datagrams to be transmitted over the serial data link using the second physical layer interface using the second frequency of operation.
Conclusion
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/JONGBONG NAH/Examiner, Art Unit 2674
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