Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 objected to because of the following informalities: “Accessing” a typo, should be lowercase. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Regarding claim 1, it recite(s) 1. An apparatus comprising: circuitry configured to: access a first operation in a queue; and responsive to the first operation being of a first type, convey, to a processing circuit, a request to complete the first operation using quantized data.
MPEP 2106 III provide a flowchart for the subject matter eligibility test for product and processes. The analysis following the flowchart is as follows:
Step 1: Is the claim to a process, machine, manufacture or composition of matter?
Yes. It recites a device, which is a machine.
Step 2A, Prong One: Does the claim recite an abstract idea, law of nature, or nature phenomenon?
Yes. It recites “An apparatus comprising: circuitry configured to: access a first operation in a queue; and responsive to the first operation being of a first type, convey, to a processing circuit, a request to complete the first operation using quantized data.” One can mentally carry out accessing a first operation in a queue on paper or in ones mind. Therefore, it still recites the mental process as the abstract idea. MPEP 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. Here, using circuitry or a processing circuit for carrying out claim 1 (a generic computer component) the previous mentioned limitations, an operation being a first operation of a particular type and a request to complete an operation using quantized data (mental process).
Step 2A, Prong Two: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No. The claim does not recite any additional elements except the limitations identified as abstract idea (mental process) in Step 2A Prong One.
Therefore, this judicial exception is not integrated into a practical application because no additional elements other than the abstract idea limitations.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No. The claim does not recite any additional elements other than the limitations identified as abstract idea (mental process) in Step 2A Prong One.
Therefore, the claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception because no additional elements other than the abstract idea limitations.
Therefore, claim 1 is not eligible subject matter under 35 USC 101.
Regarding claim 2, it depends from claim 1 wherein the circuitry is configured to: access a second operation in the queue; and responsive to the second operation being of a second type different from the first type, execute the second operation using non-pre-filtered data.
2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 2 using circuitry or a processing circuit for carrying out claim 2 is a generic computer component. Accessing a second operation in the queue can be carried out mentally or on paper. This can be carried out by observing a queue in person or on paper and determine a second operation in the queue. The second operation being a second type executed using non-pre-filter data, can be carried out mentally or on paper. A person can observe and determine a second type by their mind and avoid data that is prefilter (using non-pre-filtered).
Therefore, claim 2 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 2 is not eligible subject matter under 35 USC 101.
Regarding claim 3, it depends from claim 2 wherein the first type is a ray tracing pre-filtering operation.
A first type being ray tracing pre-filtering operation can be carried out mentally and done with calculations. A ray tracing pre-filtering operation can be mentally deciding to not use a ray tracing by pencil and paper.
Therefore, claim 3 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 3 is not eligible subject matter under 35 USC 101.
Regarding claim 4, it depends from claim 1 wherein the processing circuit is an accelerator circuit configured to execute a machine learning model.
2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 4 using circuitry, a processing circuit, an accelerator circuit for carrying out claim 4 is a generic computer component. A machine learning model can be considered to be mathematical functions or mapping. A math function or mapping can be carried out mentally or using pencil and paper.
Regarding claim 5, it depends from claim 1 wherein the processing circuit comprises a larger number of a computational resource than the apparatus. 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 5 using circuitry, a processing circuit or accelerator circuit for carrying out claim 5 is a generic computer component. A large computational resource can be a well-rested person with fresh mental capacity.
Therefore, claim 5 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 5 is not eligible subject matter under 35 USC 101.
Regarding claim 6, it depends from claim 5 wherein the hardware resource is an integer arithmetic logic unit. 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 6 using circuitry, a processing circuit, integer arithmetic logic unit or accelerator circuit for carrying out claim 6 is a generic computer component. An integer ALU can be a mind carrying out integer math. A hardware resource can be considered a mind carrying out a task.
Therefore, claim 6 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 6 is not eligible subject matter under 35 USC 101.
Regarding claim 7, it depends from claim 1 wherein the circuitry is configured to generate ray data based on image data. 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 7 using circuitry, a processing circuit, integer arithmetic logic unit or accelerator circuit for carrying out claim 6 is a generic computer component. Generating ray data based on image data can be a person calculating mentally or on paper a ray based on the image intended to produce.
Therefore, claim 7 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 7 is not eligible subject matter under 35 USC 101.
Regarding claim 8 it recite(s). 8. A method, comprising: accessing, by a first processing circuit, a first operation in a queue; and responsive to the first operation being of a first type, conveying, by the first processing circuit to a second processing circuit, a request to complete the first operation using quantized data.
MPEP 2106 III provide a flowchart for the subject matter eligibility test for product and processes. The analysis following the flowchart is as follows:
Step 1: Is the claim to a process, machine, manufacture or composition of matter?
Yes. It recites a method, which is a process.
Step 2A, Prong One: Does the claim recite an abstract idea, law of nature, or nature phenomenon?
Yes. It recites “A method, comprising: accessing, by a first processing circuit, a first operation in a queue; and responsive to the first operation being of a first type, conveying, by the first processing circuit to a second processing circuit, a request to complete the first operation using quantized data.” One can mentally carry out accessing a first operation in a queue on paper or in ones mind. Therefore, it still recites the mental process as the abstract idea. MPEP 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. Here, using a first/second processing circuit for carrying out claim 1 (a generic computer component) of the previous mentioned limitations, an operation being a first operation of a particular type and a request to complete an operation using quantized data can be a mental process.
Step 2A, Prong Two: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No. The claim does not recite any additional elements except the limitations identified as abstract idea (mental process) in Step 2A Prong One.
Therefore, this judicial exception is not integrated into a practical application because no additional elements other than the abstract idea limitations.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No. The claim does not recite any additional elements other than the limitations identified as abstract idea (mental process) in Step 2A Prong One.
Therefore, the claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception because no additional elements other than the abstract idea limitations.
Therefore, claim 8 is not eligible subject matter under 35 USC 101.
Regarding claim 9, it depends from claim 8, further comprising: Accessing, by the first processing circuit, a second operation in the queue; and responsive to the second operation being of a second type different from the first type, executing, by the first processing circuit, the second operation using non-pre-filtered data.
2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 2 using circuitry or a processing circuit for carrying out claim 2 is a generic computer component. Accessing a second operation in the queue can be carried out mentally or on paper. This can be carried out by observing a queue in person or on paper and determine a second operation in the queue. The second operation being a second type executed using non-pre-filter data, can be carried out mentally or on paper. A person can observe and determine a second type by their mind and avoid data that is prefilter (using non-pre-filtered).
Therefore, claim 9 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 9 is not eligible subject matter under 35 USC 101.
Regarding claim 10 it depends from claim 8 and recites wherein the first type is a ray tracing pre-filtering operation.
A first type being ray tracing pre-filtering operation can be carried out mentally and done with calculations. A ray tracing pre-filtering operation can be mentally deciding to not use a ray tracing by pencil and paper.
Therefore, claim 10 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 10 is not eligible subject matter under 35 USC 101.
Regarding claim 11 it depends from claim 8 and recites wherein the processing circuit is an accelerator circuit configured to execute a machine learning model
2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 11 using circuitry, a processing circuit, an accelerator circuit for carrying out claim 11 is a generic computer component. A machine learning model can be considered to be mathematical functions or mapping. A math function or mapping can be carried out mentally or using pencil and paper.
Therefore, claim 11 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 11 is not eligible subject matter under 35 USC 101.
Regarding claim 12 it depends from claim 8, wherein the processing circuit comprises a larger number of a computational resources than the apparatus. As per claim 12 using circuitry, a processing circuit or accelerator circuit for carrying out claim 12 is a generic computer component. A large computational resource can be a well-rested person with fresh mental capacity.
Therefore, claim 12 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 12 is not eligible subject matter under 35 USC 101.
Regarding claim 13 it depends from claim 12, wherein the hardware resource is an integer arithmetic logic unit. 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 13 using circuitry, a processing circuit, integer arithmetic logic unit or accelerator circuit for carrying out claim 13 is a generic computer component. An integer ALU can be a mind carrying out integer math. A hardware resource can be considered a mind carrying out a task.
Therefore, claim 13 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 13 is not eligible subject matter under 35 USC 101.
Regarding claim 14 it depends from claim 8 and recites, further comprising generating, by the first processing circuit, ray data based on image data. 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 7 using circuitry, a processing circuit, integer arithmetic logic unit or accelerator circuit for carrying out claim 6 is a generic computer component. Generating ray data based on image data can be a person calculating mentally or on paper a ray based on the image intended to produce.
Therefore, claim 14 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 14 is not eligible subject matter under 35 USC 101.
Regarding claim 15 it recite(s). 15. A computing system comprising: a cache memory subsystem; a first processing circuit; and a second processing circuit; and wherein the first processing circuit is configured to: access a first operation in a queue; and responsive to the first operation being of a first type, convey, to the second processing circuit, a request to complete the first operation using quantized data stored in the cache memory subsystem.
MPEP 2106 III provide a flowchart for the subject matter eligibility test for product and processes. The analysis following the flowchart is as follows:
Step 1: Is the claim to a process, machine, manufacture or composition of matter?
Yes. It recites a computing system, which is a machine.
Step 2A, Prong One: Does the claim recite an abstract idea, law of nature, or nature phenomenon?
Yes. It recites, “A computing system comprising: a cache memory subsystem; a first processing circuit; and a second processing circuit; and wherein the first processing circuit is configured to: access a first operation in a queue; and responsive to the first operation being of a first type, convey, to the second processing circuit, a request to complete the first operation using quantized data stored in the cache memory subsystem.”
MPEP 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. Here, using circuitry, a computing system or a first/second processing circuit for carrying out claim 1 (a generic computer component). A cache memory subsystem can be interpreted as a human memory or written down. One can mentally carry out accessing a first operation in a queue on paper or in ones mind. Therefore, it still recites the mental process as the abstract idea. MPEP 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. Here, using circuitry or a processing circuit for carrying out claim 1 (a generic computer component) the previous mentioned limitations, an operation being a first operation of a particular type and a request to complete an operation using quantized data (mental process).
Step 2A, Prong Two: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No. The claim does not recite any additional elements except the limitations identified as abstract idea (mental process) in Step 2A Prong One.
Therefore, this judicial exception is not integrated into a practical application because no additional elements other than the abstract idea limitations.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No. The claim does not recite any additional elements other than the limitations identified as abstract idea (mental process) in Step 2A Prong One.
Therefore, the claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception because no additional elements other than the abstract idea limitations.
Therefore, claim 15 is not eligible subject matter under 35 USC 101.
Regarding claim 16 it depends from claim 15, it recites, wherein the first processing circuit is configured to: access a second operation in the queue; and responsive to the second operation being of a second type different from the first type, execute the second operation using non-pre-filtered data stored in the cache memory subsystem.
2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 16 using circuitry or a processing circuit for carrying out claim 16is a generic computer component. Accessing a second operation in the queue can be carried out mentally or on paper. This can be carried out by observing a queue in person or on paper and determine a second operation in the queue. The second operation being a second type executed using non-pre-filter data, can be carried out mentally or on paper. A person can observe and determine a second type by their mind and avoid data that is prefilter (using non-pre-filtered).
Therefore, claim 16 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 16 is not eligible subject matter under 35 USC 101.
Regarding claim 17 it depends from claim 16 and it recites, wherein the first type is a ray tracing pre-filtering operation.
A first type being ray tracing pre-filtering operation can be carried out mentally and done with calculations. A ray tracing pre-filtering operation can be mentally deciding to not use a ray tracing by pencil and paper.
Therefore, claim 17 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 17 is not eligible subject matter under 35 USC 101.
Regarding claim 18 it depends from claim 15 wherein the processing circuit is an accelerator circuit configured to execute a machine learning model.
2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 18 using circuitry, a processing circuit, an accelerator circuit for carrying out claim 18 is a generic computer component. A machine learning model can be considered to be mathematical functions or mapping. A math function or mapping can be carried out mentally or using pencil and paper.
Therefore, claim 18 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 18 is not eligible subject matter under 35 USC 101.
Regarding claim 19 it depends from claim 15 it recites, wherein the second processing circuit comprises a larger number of a hardware resource than the first processing circuit. 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 19 using circuitry, a processing circuit or accelerator circuit for carrying out claim 19 is a generic computer component. A large computational resource can be a well-rested person with fresh mental capacity. A hardware resource can be considered a mind carrying out a task.
Therefore, claim 19 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 19 is not eligible subject matter under 35 USC 101.
Regarding claim 20 it depends from claim 19 it recites, wherein the hardware resource is an integer arithmetic logic unit. 2106.04(a)(2).III.C states a claim that requires a computer may still recite a mental process. As per claim 20 using circuitry, a processing circuit, integer arithmetic logic unit or accelerator circuit for carrying out claim 20 is a generic computer component. An integer ALU can be a mind carrying out integer math. A hardware resource can be considered a mind carrying out a task.
Therefore, claim 20 does not recite any additional elements that can integrate the abstract idea into practical application or amount to significantly more than the judicial exception (the answers to step 2A prong two and step 2B are no.). Claim 20 is not eligible subject matter under 35 USC 101.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5, 11, 12, 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 excites the limitation "the hardware resource” in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the processing circuit" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the processing circuit" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the hardware resource” in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the apparatus” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 3, 5, 7, 8, 9, 10 , 12, 14, 15, 16, 17, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lacewell et al. (Raytracing Prefiltered Occlusion for Aggregate Geometry) in view of Hubo et al. (The Quantized kd-Tree: Efficient Ray Tracing of Compressed Point Clouds).
Regarding claim 1, Lacewell teaches an apparatus comprising (See page 7 5 Conclusion, “It would probably be faster to project multiple nodes in parallel on the GPU.”):
circuitry configured to (See page 7 5 Conclusion, “It would probably be faster to project multiple nodes in parallel on the GPU.” The GPU is considered to be the circuitry.):
access a first operation in a queue (See page 1, 1 Introduction, col. 2, “During rendering, we terminate shadow rays at some level of the BVH, dependent on the differential [10] of each ray, and return the stored opacity at the node. The combined opacity of the ray is computed by compositing the opacities of one or more nodes that the ray intersects, in any order. This early termination eliminates many ray-triangle intersections, and makes intersection cost independent of geometric complexity for rays with large enough differentials.
In addition, prefiltering also reduces the variance of occlusion estimates
on aggregate geometry, which in turn reduces noise artifacts
for a given number of shadow rays.” The examiner notes BVH operations uses queues.); and but doesn’t explicitly disclose
responsive to the first operation being of a first type, convey, to a processing circuit, a request to complete the first operation using quantized data.
The examiner notes, Lacewell, already teaches a processing circuit (See page 7 5 Conclusion, “It would probably be faster to project multiple nodes in parallel on the GPU.”).
Hubo teaches responsive to the first operation being of a first type, convey, to a processing circuit, a request to complete the first operation using quantized data (See abstract, “Both ray tracing and point-based representations provide means to
efficiently display very complex 3D models. Computational efficiency
has been the main focus of previous work on ray tracing
point-sampled surfaces. For very complex models efficient storage
in the form of compression becomes necessary in order to avoid
costly disk access. However, as ray tracing requires neighborhood
queries, existing compression schemes cannot be applied because
of their sequential nature. This paper introduces a novel acceleration
structure called the Quantized kd-tree, which offers both efficient
traversal and storage. The gist of our new representation lies
in quantizing the kd-tree splitting plane coordinates. We show that
the Quantized kd-tree reduces the memory footprint up to 18 times,
not compromising performance. Moreover, the technique can also
be employed to provide LOD (Level-Of-Detail) to reduce aliasing
problems, with little additional storage cost.”. See page 105 1. Introduction col. 2, “Our main contribution is a novel variant of the kd-tree, dubbed
the Quantized kd-Tree, which compresses both the spatial data
structure and the data set through quantization of the split plane
positions. It aggressively decreases the memory footprint at the expense
of reduced precision. Even though the loss of information
seems high, the error decreases when storing more points. Since
we are mainly interested in dealing with very large datasets, the
precision problem is alleviated.” See page 106 2 Related Work col. 2 “This scheme is highly efficient and can be decoded using graphics hardware. Gumhold et al. [ 12] and later Merry et al. [21] use an approach based on spanning trees to sequentially encode points in an optimal fashion.”).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lacewell in view of Hubo because Hubo’s “scheme is highly efficient and can be decoded
using graphics hardware. “ Therefore increasing the efficiency in the overall when combined with Lacewell.
Regarding claim 2, Lacewell in view of Hubo teaches the apparatus as recited in claim 1, wherein the circuitry is configured to:
access a second operation in the queue (See Lacewell page 105 Figure 1 description, “Computing shadows using a prefiltered BVH is more efficient than using an ordinary BVH. (a) Using an ordinary BVH
with 4 shadow rays per shading point requires 112 seconds for shadow rays, and produces significant visible noise. (b) Using
a prefiltered BVH with 9 shadow rays requires 74 seconds, and visible noise is decreased. (c) Reducing noise to a similar level
with an ordinary BVH requires 25 shadow rays and 704 seconds (about 9.5× slower). All images use 5×5 samples per pixel.
The scene consists of about 2M triangles, each of which is semi-opaque (a = 0.85) to shadow rays.” The examiner notes BVH is a queue.); and
responsive to the second operation being of a second type different from the first type, execute the second operation using non-pre-filtered data (See Lacewell page 105 Figure 1 description, “Computing shadows using a prefiltered BVH is more efficient than using an ordinary BVH. (a) Using an ordinary BVH
with 4 shadow rays per shading point requires 112 seconds for shadow rays, and produces significant visible noise. (b) Using
a prefiltered BVH with 9 shadow rays requires 74 seconds, and visible noise is decreased. (c) Reducing noise to a similar level
with an ordinary BVH requires 25 shadow rays and 704 seconds (about 9.5× slower). All images use 5×5 samples per pixel.
The scene consists of about 2M triangles, each of which is semi-opaque (a = 0.85) to shadow rays.” The second type being ordinary BVH which would be non-prefiltered).
Regarding claim 3, Lacewell in view of Hubo teaches the apparatus as recited in claim 2, wherein the first type is a ray tracing pre-filtering operation (See page 1, 1 Introduction, col. 2, “During rendering, we terminate shadow rays at some level of the BVH, dependent on the differential [10] of each ray, and return the stored opacity at the node. The combined opacity of the ray is computed by compositing the opacities of one or more nodes that the ray intersects, in any order. This early termination eliminates many ray-triangle intersections, and makes intersection cost independent of geometric complexity for rays with large enough differentials.
In addition, prefiltering also reduces the variance of occlusion estimates
on aggregate geometry, which in turn reduces noise artifacts
for a given number of shadow rays.”).
Regarding claim 5, Lacewell in view of Hubo teaches the apparatus as recited in claim 1, wherein the processing circuit comprises a larger number of a computational resource than the apparatus (See Lacewell See page 7 5 Conclusion, “It would probably be faster to project multiple nodes in parallel on the GPU.” A GPU has a larger number of computational resource than other processors/circuits of Lacwell.).
Regarding claim 7 Lacewell in view of Hubo teaches the apparatus as recited in claim 1, wherein the circuitry is configured to generate ray data based on image data (See Lacewell page 3 3.3 Computing Directional Opacity, the last paragraph up to 4 Results. The examiner notes any of the values used for ray data is considered to be based on image data since the result is for an image.).
Claim 8 recites similar limitations to that of claim 1 but doesn’t explicitly disclose a method comprising; a first processing circuit; and conveying, by the first processing circuit to a second processing circuit
Lacewell teaches a method comprising (See Lacewell page 4 col. 1 “The combined opacity computation for the BVH using this hybrid method is O(NT ), with storage requirements
O(NT ).” Also page 3 col. 2 Algorithm 1, the whole algorithm is a method.); a first processing circuit; and conveying, by the first processing circuit to a second processing circuit (See Lacewell page 4 4.3 Performance “We rendered each model using identical camera and light parameters, using 4 parallel threads over image tiles, on a machine with 4 Intel Xeon 2.66 GHz cores and 8 GB of memory.” See page 7 5 Conclusion, “It would probably be faster to project multiple nodes in parallel on the GPU.” One of the Intel Xeons is considered to be a first circuit. The Second processing circuit can be the second through fourth Xeon, or the GPU. CPUs communicate to GPUs and doing so is considered to be conveying to a first processing circuit and a second processing circuit.).
Therefore claim 8 recites similar limitations to that of claim 1 and thus is rejected under similar rationale.
Claims 9, 10, 12, 14 , recite similar limitations to that of claims 2, 3, 5, 7 and thus is rejected under similar rationale.
Claim 15 recites similar limitations to that of claim 1 and 8 but doesn’t explicitly disclose a computing system comprising:
a cache memory subsystem;
wherein the first processing circuit is configured to:
[…] stored in the cache memory subsystem.
Lacewell teaches a computing system comprising (See Lacewell page 4 4.3 Performance “We rendered each model using identical camera and light parameters, using 4 parallel threads over image tiles, on a machine with 4 Intel Xeon 2.66 GHz cores and 8 GB of memory.”); a cache memory subsystem (See Lacewell page 4 4.3 Performance “We rendered each model using identical camera and light parameters, using 4 parallel threads over image tiles, on a machine with 4 Intel Xeon 2.66 GHz cores and 8 GB of memory.” The 8GB of memory is interpreted as a cache memory subsystem.);
wherein the first processing circuit is configured to (See Lacewell page 4 4.3 Performance “We rendered each model using identical camera and light parameters, using 4 parallel threads over image tiles, on a machine with 4 Intel Xeon 2.66 GHz cores and 8 GB of memory.”) […] stored in the cache memory subsystem (See Lacewell page 4 4.3 Performance “We rendered each model using identical camera and light parameters, using 4 parallel threads over image tiles, on a machine with 4 Intel Xeon 2.66 GHz cores and 8 GB of memory.”).
Therefore claim 15 recites similar limitations to that of claim 1 and 8 and thus is rejected under similar
Claim(s) 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lacewell et al. (Raytracing Prefiltered Occlusion for Aggregate Geometry) in view of Hubo et al. (The Quantized kd-Tree: Efficient Ray Tracing of Compressed Point Clouds) in further view of Perry et al. (US 20220319096 A1)
Regarding claim 4, Lacewell in view of Hubo teaches the apparatus as recited in claim 1, wherein the processing circuit is an accelerator circuit (See page 7 5 Conclusion, “It would probably be faster to project multiple nodes in parallel on the GPU.” The GPU is considered to be the circuitry) but doesn’t explicitly disclose configured to execute a machine learning model.
Perry teaches to execute a machine learning model (See ¶58: GPU and ML model/tasks. ¶14: shows using a machine learning model on BVH).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lacewell in view of Hubo in further view of Perry as it allows rendering and collision steps to avoid computationally intense algorithms and instead use fast, neural network based hierarchy algorithms, thus increasing the efficiency available.
Claim(s) 6, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lacewell et al. (Raytracing Prefiltered Occlusion for Aggregate Geometry) in view of Hubo et al. (The Quantized kd-Tree: Efficient Ray Tracing of Compressed Point Clouds) in further view of Asperheim al. (US Patent No. 10,691,392 B2).
Regarding claim 6, Lacewell in view of Hubo teaches the apparatus as recited in claim 5, wherein the hardware resource but doesn’t explicitly disclose is an integer arithmetic logic unit.
Asperheim teaches wherein the hardware resource is an integer arithmetic logic unit.
(See col. 10 lines 31-36, “The GPGPU cores 262 can be similar in architecture or can differ in architecture, according to embodiments. For example and in one embodiment, a first portion of the GPGPU cores 262 include a single precision FPU and an integer ALU while a second portion of the GPGPU cores include a double precision FPU.”).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Lacewell in view of Hubo in further view Asperheim as using an integer ALU would lower the power usage required for quantized values, reduce memory storage and bandwidth requirements, thus increasing the overall efficiency of the system.
Claims 13 and 20 recite similar limitations of that of claim 6 and thus is rejected under similar rationale as detailed above.
Conclusion
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/ROBERT J CRADDOCK/Primary Examiner, Art Unit 2618
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