DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: there is a missing article in the limitation “circuitry” page 1 line 4. The examiner suggests to add the limitation as “a circuitry”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s cited reference US 2022/0231029 (Hwang et al herein after Hwang) and in view of the applicant’s cited reference US 203/0389284 (Simsek-Ege).
Regarding claims 1 and 16, Hwang discloses a dynamic random access memory (DRAM) (para. [0015]) comprising: a first memory array (fig. 4c, array-1, 202a, para. [0050]) comprising an arrangement of memory cells (fig. 1, 204, MC, para. [0015]); a second memory array (fig. 4c, array-2, 202b, para. [0050]) comprising a complementary metal-oxide-semiconductor (CMOS) layer (figs. 3A, 3B, 4A-4C, CMOS region 100, para. [0032]) comprising circuitry for operating the first memory array and the second memory array (para. [0036]), wherein the CMOS layer is arranged, along a first axis (fig. 2, A2), between the first memory array and the second memory array, wherein the circuitry of the CMOS layer comprises one or more word line drivers (para. [0036], item 16) configured to drive word lines (implicit) associated with respectively the first memory array and the second memory array (fig. 4C), and wherein the circuitry of the CMOS layer comprises one or more sense amplifiers (para. [0036]) configured to sense charge on bit lines respectively associated with the first memory array and the second memory array.
Hwang does not explicitly disclose a three-dimensional (3D) arrangement of memory cells.
However, a three-dimensional (3D) arrangement of memory cells is notorious old and well known.
For instance, in the related field of the invention, Simsek-Ege teaches a three-dimensional (3D) arrangement of memory cells (para. [0003] “…..The memory cells may be electrically accessed through digit lines (e.g., hit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of the memory cells of the memory arrays. Memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells.” and fig. 6A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teaching by Simsek-Ege in Hwang for a particular application.
Regarding claims 2 and 17, Hwang also shows wherein in the first memory array and the second memory array, respectively, the word lines extend along a second axis, which is perpendicular to the first axis, and the bit lines extend along the first axis (fig. 1).
Regarding claims 13 and 14, Hwang and Simsek-Ege do not explicitly disclose
wherein a width of each of the first memory array and the second memory array along a second axis is larger than its height along the first axis and wherein a width of each of the first memory array and the second memory array along a second axis is smaller than its height along the first axis.
However, Hwang does not limit to a specific dimension of components (para. [0076]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Hwang to a specific dimension as claimed above for a particular memory application. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955).
Regarding claim 15, Simsek-Ege also teaches wherein the memory cells in each of the first memory array and the second memory array are organized in a plurality of planes, which are stacked along the first axis, and are organized in each plane in a plurality of rows extending along a second axis, and in a plurality of columns extending along a third axis (see figs. 2A, 2B, para. [0016], [0051], [0109], [0126], [0138]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teaching by Simsek-Ege in Hwang for a particular application.
Allowable Subject Matter
Claims 3-12 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art of record fails to teach the limitations of claim 3 “wherein: the CMOS layer protrudes along a second axis from between the first memory array and the second memory array, a first subset of the word lines is associated with the first memory array and is connected via an exposed first surface of the CMOS layer to the one or more word line drivers, and a second subset of the word lines is associated with the second memory array and is connected via an exposed second surface of the CMOS layer to the one or more word line drivers, wherein the second surface is opposite to the first surface.“; the limitations of claim 6 “further comprising a plurality of global bit lines, wherein a first subset of the global bit lines is associated with the first memory array and a second subset of the global bit lines is associated with the second memory array, wherein each bit line is connected to one of the global bit lines, and wherein each global bit line is connected to one sense amplifier of the CMOS layer.“; the limitations of claim 18 “wherein: the CMOS layer protrudes along a second axis from between the first memory array and the second memory array, a first subset of the word lines is associated with the first memory array and is connected via an exposed first surface of the CMOS layer to the one or more word line drivers, and a second subset of the word lines is associated with the second memory array and is connected via an exposed second surface of the CMOS layer to the one or more word line drivers, wherein the second surface is opposite to the first surface.“ and the limitations of claim 19 “wherein the initial DRAM further comprises a plurality of global bit lines, wherein a first subset of the global bit lines is associated with the first memory array and a second subset of the global bit lines is associated with the second memory array, wherein each bit line is connected to one of the global bit lines, and wherein each global bit line is connected to one sense amplifier of the CMOS layer.”. Therefore, the prior art teachings are neither anticipate nor render obvious the allowable subject matter in combination with the other claimed limitations.
Conclusion
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/TUAN D NGUYEN/Primary Examiner, Art Unit 2824
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