Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on July 14th, 2026. Claims 2-21 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-21 are rejected under 35 U.S.C. 103 as being unpatentable over Rajan et al. (USPGPUB No. 2014/0192583 A1, hereinafter referred to as Rajan) in view of Leone et al. (USPGPUB No. 2019/0042451 A1, hereinafter referred to as Leone) and further in view of Bhargava et al. (USPGPUB No. 2019/0325959 A1, hereinafter referred to as Bhargava).
Referring to claim 2, Rajan discloses a method performed by a memory system, the method comprising:
operating a first memory subsystem as a non-volatile memory subsystem {flash stack 12424, see Fig. 124b, [1281];
communicating, via a first interface {“standard fast memory bus”, see Fig. 124b, [1280]} that is coupled with a non-volatile memory system {“number of subassemblies or Substacks 12422”, see Fig. 124b, [1281]}, first information between the first memory subsystem and a host system {a host system comprising “various attached flash devices”, see Fig. 139, [1386]}, the first information associated with the first memory subsystem {first information associated with “different memories are managed by logic”, see Fig. 124b, [1281]};
switching from operating the first memory subsystem as the non-volatile memory subsystem {“mapping logic 12448”, see Fig. 124b, [1286]} to operating the first memory subsystem as a volatile memory subsystem based at least in part on receipt of an indication {indication via “ paging system is modified to allow access to the mixed-technology memory module 12400”, see Fig. 124b, [1309] on the receipt of searching/inquiring “lookup Translation Lookaside Buffer (TLB) and/or Page Table functions can be modified to accommodate a mixed-technology DIMM” ([1311], 1st sentence} to operate the first memory subsystem as the volatile memory subsystem {“standard DRAM”, see Fig. 133, [1328]};
and communicating second information associated {“plane size field”, see Fig. 139, [1389]} with the first memory subsystem via a second interface {“standard DRAM” via a second interface as claimed, see Fig. 133, [1328]} that is coupled with a volatile memory system {write operation arrives at the DRAM at t1, [0348], see Fig. 12.}.
Rajan does not appear to explicitly disclose and communicating second information associated with the first memory subsystem via a second interface that is coupled with a volatile memory system based at least in part on operating the first memory subsystem as the volatile memory subsystem;
However, Leone discloses communicating second information associated with the first memory subsystem {“Primary Memory media 210”, see Fig. 2a [0048], 2nd sentence} via a second interface that is coupled {second interface “primary memory resource and the cache memory resource memory”, see Fig. 3 [0034]} with a volatile memory system based {“cache memory “DRAM” cells ([0034]} at least in part on operating {operating as “communication [host] interface 304,”, see Fig. 3 [0053]} the first memory subsystem as the volatile memory subsystem {operating with respect to first memory subsystem and second memory types “primary memory resource and the cache memory resource memory”, see Fig. 3 [0034] that includes first type “NAND flash memory is used as a primary memory resource” ([0029], 2nd sentence) and cache memory “DRAM” cells ([0034])};
Rajan and Leone are analogous art because they are from the same problem-solving area, method and systems for managing memory devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rajan and Leone before him or her, to modify Rajan’s non-transparent bridge incorporating Leone’s “integrated memory controller 252” and corresponding interconnect circuitry (see Figs. 2 and 3).
The suggestion/motivation for doing so would have been to implement improvements in memory technology may reduce the performance difference between the primary storage resource and the cache memory resource while taking into account when a cache is saturated by a certain number of data requests (Leone [0002] paraphrased).
Therefore, it would have been obvious to combine Leone with Rajan to obtain the invention as specified in the instant claim(s).
Neither Rajan nor Leone appears to explicitly disclose operating a set of memory cells of a first memory subsystem as non-volatile memory;
switching from operating the set of memory cells of the first memory subsystem as non-volatile memory to operating the set of memory cells as volatile memory based at least in part on receipt of an indication to operate the first memory subsystem as a volatile memory subsystem instead of as a non-volatile memory subsystem; and
communicating second information associated with the first memory subsystem via a second interface that is coupled with a volatile memory system based at least in part on switching to operating the set of memory cells of the first memory subsystem as volatile memory.
However, Bhargava discloses operating a set of memory cells {such “memory 108” comprising/operating set of memory cells “among volatile memory bitcells and non-volatile memory bitcells”, see Fig. 2 [0035], 1st sentence} of a first memory subsystem as non-volatile memory {first memory subsystem “memory 108” (see Fig. 1, [0034], last sentence)};
switching from operating the set of memory cells of the first memory subsystem as non-volatile memory {“copying states or [switching] transferring stored values between or among volatile memory bitcells and non-volatile memory bitcells” (see Fig. 2 [0035], 1st sentence) switching further explained in [0091], 1st sentence} to operating the set of memory cells as volatile memory {“a volatile memory state maintained in bitcell circuit 1320 by PFETs P1 and P2”, see Fig. 13E [0091], 2nd sentence} based at least in part on receipt of an indication to operate {“comprise shared control signals such as a shared clock signal clk” that indicate to operate as claimed, see Fig. 3, [0037], last two sentences} the first memory subsystem as a volatile memory subsystem {“to either volatile memory bitcells 302 or [instead of/otherwise selecting] non-volatile memory bitcells, or both.”, see Fig. 3, [0037], last sentence} instead of as a non-volatile memory subsystem {“may control memory cycles (e.g., for read operations and/or write operations) applied”, see Fig. 3 [0037], last sentence}; and
communicating second information associated with the first memory subsystem {“Integrated circuit device 300 may further comprise signaling pins 322 and 324 to at least in part form a single data port that is configurable to transfer data between an [first memory] external device”, see Fig. 2 [0037], last two sentences} via a second interface {“external data port 332”, see Fig. 2 [0039], last two sentences} that is coupled with a volatile memory system {“memory states may be copied or stored values may be transferred between or among volatile memory bitcells 302 and non-volatile memory bitcells 304 over memory busses”, see Fig. 3A, [0035], 2ND sentence} based at least in part on switching to operating the set of memory cells {“bitcell circuit 1310 may be switchable between operation in a volatile memory mode by lowering a voltage of signal power-on-reset (POR) and operation in a non-volatile memory mode”, see Fig. 13B [0084], last sentence} of the first memory subsystem as volatile memory {“may control memory cycles (e.g., for read operations and/or write operations) applied”, see Fig. 3 [0037], last sentence}.
Rajan/Leone and Bhargava are analogous art because they are from the same problem-solving area, method and systems for managing memory devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rajan/Leone and Bhargava before him or her, to modify Rajan/Leone’s system incorporating Bhargava’s “specific implementation of bitcell circuit 1300 shown as bitcell circuit 1310 in which multiplexer 1302” (see Fig. 13b, [0084] 1st sentence).
The suggestion/motivation for doing so would have been to implement a commercial memory device permitting a memory state is changed many times, a difference in resistance between a conducting state and an insulative state may change significantly (Bhargava [0007], last two sentences) while improving flash memory limitations to keep random access (erase/write single bits) was sacrificed for speed and higher bit density (Bhargava [0004] last sentence).
Therefore, it would have been obvious to combine Bhargava with Rajan/Leone to obtain the invention as specified in the instant claim(s).
As per claim 3, the rejection of claim 2 is incorporated and Rajan discloses further comprising:
communicating the first information via a first port {“Each Super-Stack 12402 has an [first port] interface 12412”, see Fig. 124b [1285], 2nd sentence} of the first memory subsystem based at least in part on operating the first memory subsystem {“comprises a Super-Controller 12416 and at least one Sub-Stack” operating in part as claimed, see Fig. 124B [1285] last two sentences} as the non-volatile memory subsystem {“plurality of flash memory components 12424 1-12424 n (also referred to herein as flash memory components 12424”, see Fig. 124b [1286], 1st sentence};
and communicating the second information via a second port {second port “providing 8 bits to the DIMM interface 12410”, see Fig. 124b, [1285], 2nd sentence} of the first memory subsystem based at least in part on operating the first memory subsystem as the volatile memory subsystem {“nine 8-bit wide Super-Stacks 12402 may provide the 72 data bits of a [volatile memory] DDR3 R-DIMM with ECC”, see Fig. 124B [1285], 3rd sentence}.
As per claim 4, the rejection of claim 2 is incorporated and Rajan discloses wherein the first memory subsystem comprises a first portion {“slow memory portion in the Sub-Stack 12422 may use NAND flash, but, in alternative embodiments, could also use NOR flash”, see Fig. 124b [1282], 1st sentence} and a second portion {“comprises an SRAM 12444, but could be comprised of DRAM, or embedded DRAM, or any other relatively fast (relative to flash) memory etc”, see Fig. 124B, [1282], 3rd sentence}, the method further comprising:
volatile portion to operating the second portion {“nine 8-bit wide Super-Stacks 12402 may provide the 72 data bits of a [volatile memory] DDR3 R-DIMM with ECC”, see Fig. 124B [1285], 3rd sentence} of the first memory subsystem as a non-volatile portion {“plurality of flash memory components 12424 1-12424 n (also referred to herein as flash memory components 12424”, see Fig. 124b [1286], 1st sentence}.
As per claim 5, the rejection of claim 4 is incorporated and Rajan discloses further comprising:
communicating third information associated with the first portion via the first interface {first information associated with “different memories are managed by logic”, see Fig. 124b, [1281]};
Leone discloses and communicating, concurrently with communicating the third information {“determine whether or not a cache table entry for a copy of the data associated with the read request”, see Fig. 124b [0042]} and based at least in part on switching to operating the second portion as the non-volatile portion {operating with respect to first memory subsystem and second memory types “primary memory resource and the cache memory resource memory”, see Fig. 3 [0034] that includes first type “NAND flash memory is used as a primary memory resource” ([0029], 2nd sentence) and cache memory “DRAM” cells ([0034])}, fourth information associated with the second portion via the second interface {“[fourth information] cache table lookup returns a hit, the data path processor 110 can determine whether the copy of the read data in the cache memory resource 208 has been altered, or in other words, is dirty, compared to the read data in the primary memory resource 206”, see Fig. 1 [0042]}.
As per claim 6, the rejection of claim 4 is incorporated and Leone discloses further comprising:
coupling the first portion {“memory controller 204”, see Fig. 2a or 2b [0048], 1st sentence} and the second portion with a first port {“saturation determination can be made using information and/or data available at the memory controller 204 or obtained by the memory controller 204”, see Fig. 2a, [0049]} of the first memory subsystem based at least in part on operating the first memory subsystem as the volatile memory subsystem {“interconnect 234 can be a separate bus, such as an out of band (oob) channel, PECI (Platform Environment Control Interface), system management bus (SMBus), Host Embedded Controller Interface (HECI)”, see Fig. 2a [0049], last sentence};
and coupling the second portion with a second port {writing/coupling to a port for “write-in-place NVM such as three-dimensional (3D) cross-point memory, for example, can operate as write-in-place memory similar to dynamic random-access memory (DRAM), or as block-addressable memory similar to NAND flash”, see Figs. 2a or 2b, [0035} of the first memory subsystem based at least in part on operating the second port as the non-volatile portion {operating with respect to first memory subsystem and second memory types “primary memory resource and the cache memory resource memory”, see Fig. 3 [0034] that includes first type “NAND flash memory is used as a primary memory resource” ([0029], 2nd sentence) and cache memory “DRAM” cells ([0034])}.
As per claim 7, the rejection of claim 2 is incorporated and Leone discloses further comprising:
communicating third information {“determine whether or not a cache table entry for a copy of the data associated with the read request”, see Fig. 124b [0042]} associated with the non-volatile memory system via the first interface {“the cache table lookup returns a miss, or in other words, where an entry for a copy of the read data is not present in the cache memory resource 208, the read request is [associated with] directed through the command generator 118 to the [non-volatile] primary memory resource 206”, see Fig. 2a [0043], last three sentences};
and communicating fourth information associated {“determine whether or not a cache table entry for a copy of the data associated with the read request”, see Fig. 124b [0042]} with the volatile memory system via the second interface {“dirty bit detector 114 determines that the copy of the read data is altered, the data path processor 110 can direct the read request to the [volatile memory] cache memory resource 208”, see Fig. 2a [0043]}.
As per claim 8, the rejection of claim 2 is incorporated and Leone discloses further comprising:
coupling the first memory subsystem with the first interface based {“memory controller 204”, see Fig. 2a or 2b [0048], 1st sentence} at least in part on operating the first memory subsystem as the non-volatile memory subsystem {“the primary memory device can include NAND flash memory, including 2D NAND, 3D NAND, or a combination thereof”, see Fig. 2a [0046]};
and coupling the first memory subsystem with the second interface {“memory controller 204” (see Fig. 2a or 2b [0048], 1st sentence) for coupling “[first memory subsystem] cache memory resource can be a cache memory resource device, such as a rotational media device, a [second interface] SSD, a DIMM device, or the like”, [0047], 1st sentence} based at least in part on switching the first memory subsystem to operate as the volatile memory subsystem {operating with respect to first memory subsystem and second memory types “primary memory resource and the cache memory resource memory”, see Fig. 3 [0034] that includes first type “NAND flash memory is used as a primary memory resource” ([0029], 2nd sentence) and cache memory “DRAM” cells ([0034])}.
As per claim 9, the rejection of claim 8 is incorporated and Leone discloses wherein coupling the first memory subsystem with the first interface comprises:
coupling the first interface with a first port of the first memory subsystem “[first memory subsystem] primary memory resource can be a primary memory resource device, such as a rotational media device, a [first interface] SSD, a DIMM device, or the like”, [0046], 2nd sentence};
and wherein coupling the first memory subsystem with the second interface comprises:
coupling the second interface with a second port {“memory controller 204” (see Fig. 2a or 2b [0048], 1st sentence) for coupling “cache memory resource can be a cache memory resource device, such as a rotational media device, a [second port/interface] SSD, a DIMM device, or the like”, [0047], 1st sentence} of the first memory subsystem.
Referring to claims 10-17 are method claims reciting claim functionality corresponding to the method claim of claims 1-9, respectively, where the roles/memory types volatile and non-volatile are swapped, thereby rejected under the same rationale as claims 1-9 recited above.
Referring to claims 18-21 are apparatus claims reciting claim functionality corresponding to the method claim of claims 10-17, respectively, where the roles/memory types volatile and non-volatile are swapped, thereby rejected under the same rationale as claims 10-17 recited above.
Response to Arguments
Applicant’s arguments filed on 07/22/2026 have been considered but deemed moot in view of the new ground of rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “PCIE”, “downstream port”, or “at least one or more PCIe endpoints”: US 20230325330 A1, US 20230291412 A1, US 20230266917 A1, US 11726835 B2, US 20230205719 A1, US 20230161721 A1, and US 20230115629 A1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
