DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 5/11/2026. Claims 1-20 are pending and are under examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, the recitation of “the first PMOS transistor” (line 10) is indefinite because it is incorrect. Did the applicant mean “the second PMOS transistor”? (i.e., the PMOS transistor P3, figure 3, since “conducting the second current (I2) through a first PMOS transistor (p4) in a PMOS current mirror responsive to a conduction of the first current (I1) through a second PMOS transistor (P3) in the PMOS current mirror”, thus, the recited the first PMOS transistor should be the second PMOS transistor). The metes and bounds cannot be determined renders the claim indefinite.
Further, the recitation of “a second resistor” (line 17) is indefinite because it is unclear as to whether this second resistor is the same as or is an additional resistor to the second resistor recited in line 10. The metes and bounds cannot be determined renders the claim indefinite.
In claim 14, the recitation of “the first resistor” (line 2) lacks proper antecedent basis, thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
Claims 15-16 are indefinite because of the technical deficiencies of claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (CN104615184A) in view of Garcia (USP 2007/0075766).
Regarding claim 1, Zou et al.’s figure 6a shows A constant-transconductance bias circuit, comprising: a p-type metal-oxide (PMOS) current mirror (P62, P63) configured to mirror a first current (current flows through P62) into a second current (current flows through P63), the PMOS current mirror including a first PMOS transistor (P63) and a second PMOS transistor (P62); an n-type metal-oxide semiconductor (NMOS) current mirror (N66, N67) configured to mirror the second current (current flows through N67) into the first current (current flows through N66), the NMOS current mirror including a first NMOS transistor (N66) and a second NMOS transistor (N67); a first resistor (N65) having a first terminal coupled to a drain of the second NMOS transistor (N67); a third PMOS transistor (P65)coupled between a drain of the first PMOS transistor (P63)and a second terminal of the first resistor; and a second resistor (R61)having a first terminal coupled to a drain of the second PMOS transistor (P62) and having a second terminal coupled to a drain of the first NMOS transistor (N66) and coupled to a gate of the third PMOS transistor (P65).
The difference seen between Zou et al. reference and the present invention is that Zou et al. shows the transistor N65 connected/functioned as a resistor instead of being a discrete first resistor as called for in claim 1.
Garcia’s figure 1 and figure 3 teaches that the transistor MN3 functions/performs as a resistor and can be replaced with a discrete resistor (R, figure 1) without altering the circuit operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace Zou et al.’s transistor connected as resistor (N65) with a resistor as taught by Garcia reference.
Regarding claim 2, Zou et al.’s figure 6a shows a third NMOS transistor (N64) having a gate coupled to a gate of the second NMOS transistor, wherein the second terminal of the second resistor is coupled to the drain of the first NMOS transistor through the third NMOS transistor.
Regarding claim 5, wherein the first PMOS transistor (P62) is diode connected.
Regarding claim 12, the constant-transconductance bias circuit can be used within an integrated circuit of a cellular telephone.
Regarding claim 13, Zou et al.’s figure 6a shows a bias circuit having A method of generating a bias voltage (gate voltage of the transistor P65) from a constant-transconductance bias circuit, comprising: conducting a first current through a first NMOS transistor (N66) in an NMOS current mirror (N66, N67) responsive to a conduction of a second current through a second NMOS transistor (N67) in the NMOS current mirror; conducting the second current through a first PMOS transistor (P63) in a PMOS current mirror (P62, P63) responsive to a conduction of the first current through a second PMOS transistor (P62) in the PMOS current mirror; generating a bias voltage by conducting the second current through a first resistor (R61) coupled to a drain of the first PMOS transistor (construed to be transistor P62); varying a power supply voltage (VDD can be varied in response to DVFS) that powers the constant-transconductance bias circuit in response to a dynamic voltage frequency scaling (construed to be no further adding or modifying structural limitations of the bias circuit; see Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & inter. 1987); and biasing a gate of a third PMOS transistor (P65) coupled to a drain of the second PMOS transistor (P63) with the bias voltage to reduce a channel length modulation of the second PMOS transistor (N67) resulting from the varying of the power supply voltage; and coupling the drain of the second NMOS transistor (N67) to a drain of the third PMOS transistor (P65) through a transistor (N65).
The difference seen between Zou et al. reference and the present invention is that Zou et al. shows the transistor N65 connected/functioned as a resistor instead of being a discrete second resistor as called for in claim 1.
Garcia’s figure 1 and figure 3 teaches that the transistor MN3 functions/performs as a resistor and can be replaced with a discrete resistor (R, figure 1) without altering the circuit operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace Zou et al.’s transistor connected as resistor (N65) with a resistor as taught by Garcia reference.
Regarding claim 14, biasing a gate of a third NMOS transistor (N64) coupled between the first resistor and a drain of the first NMOS transistor (N66) with a drain voltage of the third PMOS transistor (P65) to reduce a channel length modulation of the first NMOS transistor resulting from the varying of the power supply voltage (“to reduce a channel length modulation of the first NMOS transistor resulting from the varying of the power supply voltage” construed to be no further adding or modifying structural limitations of the bias circuit; see Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & inter. 1987). Therefore, the limitations of claim 14 are also met.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (CN104615184A) in view of Garcia (USP 2007/0075766) and further in view of Chang et al. (US 2026/0016846).
Regarding claim 3, the combination of Zou et al. and Garcia references discloses all the aspects of the present invention as noted above except for a fourth PMOS transistor having a source coupled to a power supply node for a power supply voltage and having a drain coupled to a source of the second PMOS transistor; and a fifth PMOS transistor having a source coupled to the power supply node and having a drain coupled to a source of the first PMOS transistor, wherein the fourth PMOS transistor and the fifth PMOS transistor are both configured to switch on and off responsive to a complement of an enable signal for the constant-transconductance bias circuit as called for in claim 3.
Chang et al.’s figure 2 shows PMOS transistors (M6 and M8) coupled between a PMOS current mirror circuit (M3, M4). The PMOS transistors are controlled by a power saving signal (PWR) to perform power saving. Therefore, it would have been obvious to person skilled in the art before the effectively filing date of the invention to include Chang et al.’s PMOS transistors (M6 and M8) in Zou et al.’s circuit arrangement for the purpose of saving power as taught by Chang et al. reference.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (CN104615184A), Garcia (USP 2007/0075766), Chang et al. (US 2026/0016846) and further in view of Draxelmayr (US 2018/0081386).
Regarding claim 6, the combination of Zou et al., Garcia, Chang et al. references discloses all the aspects of the present invention as noted above except for a first transmission gate coupled between a gate of the first NMOS transistor and the drain of the second NMOS transistor, wherein the first transmission gate is configured to open and close responsive to a buffered version of the enable signal and to a buffered version of the complement of the enable signal as called for in claim 6.
Draxelmayr’s figure 4a shows a transmission gate (P0, N1) coupled in between gate electrodes of transistors P12 and P11. It is known that a current mirror is in a constant consuming power. By placing a transmission gate between gate electrodes of a current mirror circuit, the power consumption can be cut off when needed. Therefore, outside of any non-obvious results, the obviousness of using a transmission gate in order to cut off power consumption in a current mirror circuit arrangement will not be patentable under 35USC 103.
Claim(s) 4, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (CN104615184A), Garcia (USP 2007/0075766), Chang et al. (US 2026/0016846) and in further view of Zou (US 2022/0035506).
Regarding claim 4, the combination of Zou et al., Garcia, Chang et al. reference discloses a bias circuit comprising all the aspects of the present invention except for a fourth NMOS transistor having a source coupled to ground, a drain coupled to a gate of the first PMOS transistor and to a gate of the second PMOS transistor, and a gate coupled to a gate of the fourth PMOS transistor and to a gate of the fifth PMOS transistor.
Zou’s figure 3A shows a fourth NMOS transistor (NMOS within 302) having a source coupled to ground to pull the gate of PMOS transistors to a known state to prevent erroneous operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Zou’s NMOS transistor in Zou et al.’s circuit arrangement for the purpose of preventing erroneous operation.
Regarding claim 7, the combination of Zou et al., Garcia, Chang et al. reference discloses a bias circuit comprising all the aspects of the present invention except for a sixth PMOS transistor having a source coupled to the power supply node and a drain coupled to the gate of the first NMOS transistor, wherein the sixth PMOS transistor is configured to switch on and off responsive to the buffered version of the enable signal as called for in claim 7.
Zou’s figure 3A shows a PMOS transistor (PMOS within 304) having a source coupled to the power supply node and a drain coupled to the gate of the first NMOS transistor (N1) in order to pull the gate of the NMOS transistor (N1) to a known state to prevent erroneous operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Zou’s PMOS transistor in Zou et al.’s circuit arrangement for the purpose of preventing erroneous operation.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (CN104615184A) in view of Chang et al. (US 2026/0016846).
Regarding claim 15, Zou et al. reference discloses all the aspects of the present invention as noted above except for a fourth PMOS transistor having a source coupled to a power supply node for a power supply voltage and having a drain coupled to a source of the second PMOS transistor; and a fifth PMOS transistor having a source coupled to the power supply node and having a drain coupled to a source of the first PMOS transistor, wherein the fourth PMOS transistor and the fifth PMOS transistor are both configured to switch on and off responsive to a complement of an enable signal for the constant-transconductance bias circuit as called for in claim 15.
Chang et al.’s figure 2 shows PMOS transistors (M6 and M8) coupled between a PMOS current mirror circuit (M3, M4). The PMOS transistors are controlled by a power saving signal (PWR) to perform power saving. Therefore, it would have been obvious to person skilled in the art before the effectively filing date of the invention to include Chang et al.’s PMOS transistors (M6 and M8) in Zou et al.’s circuit arrangement for the purpose of saving power as taught by Chang et al. reference.
Regarding claim 16, generating a calibrated current (Iref) responsive to a generation of the bias voltage (gate voltage of the transistor P65).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holloway et al. (USP 7,015,744) in view of Zou et al. (CN104615184A).
Regarding claim 18, Holloway et al.’s figure 6 shows a bias circuit comprising all the aspects of the present invention as noted above except a third PMOS transistor coupled between the first resistor and a drain of the first PMOS transistor as called for in claim 18.
Zou et al.’s figure 6a shows a bias circuit further comprising a PMOS transistor (P65) coupled between the first resistor (N65 transistor connected as resistor)and a drain of the first PMOS transistor (P63) to control a pathway of the second current flows. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Zou’s PMOS transistor in Holloway et al.’s circuit arrangement for the purpose of controlling the mirrored current as taught by Zou et al. reference.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holloway et al. (USP 7,015,744) in view of Draxelmayr (US 2018/0081386).
Regarding claim 19, the Holloway et al. reference discloses all the aspects of the present invention as noted above except for a first transmission gate coupled between a gate of the first NMOS transistor and the drain of the second NMOS transistor as called for in claim 19.
Draxelmayr’s figure 4a shows a transmission gate (P0, N1) coupled in between gate electrodes of transistors P12 and P11. It is known that a current mirror is in constant consuming power. By placing a transmission gate between gate electrodes of a current mirror circuit, the power consumption can be cut off when needed. Therefore, outside of any non-obvious results, the obviousness of using a transmission gate in order to cut off power consumption in a current mirror circuit arrangement will not be patentable under 35USC 103.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Holloway et al. (USP 7.015,744).
Regarding claim 17, Holloway et al.’s figure 6 shows A bias circuit, comprising: a PMOS current mirror (M4, M5) configured to mirror a first current (IR) into a second current (IL), the PMOS current mirror including a first PMOS transistor (M5)and a second PMOS transistor (M4); an NMOS current mirror (M1, M2) configured to mirror the second current into the first current, the NMOS current mirror including a first NMOS transistor (M2) and a second NMOS transistor (M1); a first resistor (R1) coupled between a gate of the second NMOS transistor and a drain of the second NMOS transistor; and a third NMOS transistor (M3) coupled between a drain of the first NMOS transistor and a drain and a gate of the second PMOS transistor, wherein a gate of the third NMOS transistor is coupled to the gate of the second NMOS transistor as called for in claim 17.
Response to Arguments
Applicant's arguments filed 5/11/2026 have been fully considered but they are not persuasive.
Regarding the rejection of claim 13 as being indefinite under 35USC 112, second paragraph, applicant argues that “a first/second resistor’ is (R3 of figure 3) and “the first PMOS transistor” is (P3 of figure 3). This is inconsistent with the recited language in claim 13. The method claim 13 calls for “conducting the second current (I2) through a first PMOS transistor (p4) in a PMOS current mirror responsive to a conduction of the first current (I1) through a second PMOS transistor (P3) in the PMOS current mirror”, thus, the recited first PMOS transistor should be the second PMOS transistor. The rejection is deemed proper.
Claims 13-16 remains rejected under 35USC 112, second paragraph.
Regarding the rejection of claims 1, 2, 5 and 12 as being unpatentable under 35USC 103 over China Pat. Pub. No. 104 615 184 to Zou et al. (hereinafter referred to as "Zou") in view of U.S. Pat. Pub. No. 2007/00 75 766 to Garcia et al. (hereinafter referred to as "Garcia"), applicant argues that the asserted "current flows through N66" (as stated in the rejection above to be the first current) does not meet Claim 1 which states "mirror the second current into the first current." found not persuasive. As per the reading of the reference onto the current from P63 of Zou is the second current (I2) and it is mirrored the first current (I1) which flows through the PMOS transistor (P62) by the current mirror (P62, P63). The output of the PMOS current mirror (the second current I2 also flows through the transistor N65) is mirrored back into the first current (I1 flows through N64) by the NMOS current mirror (N65, N64). The recited languages are met, thus, the rejection is deemed proper.
Noted that, figure 3 of the present invention, the PMOS mirror circuit (P3, P4) mirrors the first current (I1) from the second PMOS transistor P3 into the second current (I2) flows through the first PMOS transistor P4. The NNOS mirror circuit (M6, M7) mirrors the second current (I2) from the second NMOS transistor M7 into the first current (I) flows through the first NMOS transistor M6. Zou’s figure 6a shows the PMOS mirror circuit (P62, P63), NMOS mirror circuit (N66, N67) are constructed in the similar fashion of the present invention. Zou’s first current is the current flows on the second PMOS transistor P62 and first NMOS N66; Zou’s second current flows on the first PMOS transistor P63 and the second NMOS 67.
With regard to the secondary reference Garcia, applicant argues that it would not be obvious to replace a transistor of a cascode with a resistor. To do so would fundamentally change the circuit and eliminate the cascode operation of Zou found not persuasive. Garcia’s figure 1 and figure 3 teaches that the transistor MN3 functions/performs as a resistor and can be replaced/interchanged with a discrete resistor (R, figure 1) without altering the circuit operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace Zou et al.’s transistor connected as resistor (N65) with a resistor as taught by Garcia reference. The rejection is deemed proper.
With regards claims 13-16, new grounds of rejection are made in view of the amended languages as being unpatentable under 35USC 103 as being obvious over Zou and Garcia references as noted above.
Regarding the rejection of claim as being anticipated under 35 U.S.C. §102 by U.S. Pat. No. 7,015,744 to Holloway et al. (hereinafter referred to as "Holloway"), applicant argues that Holloway et al. fails to show "a first resistor coupled between a gate of the second NMOS transistor and a drain of the second NMOS transistor”, i.e., Holloway et al.’s resistor (R1) is not coupled between these two points but is a common node for these two points, found not persuasive. Hollaway et al.’s first resistor (R1) coupled between a gate of the second NMOS transistor (M1) and a drain of the second NMOS transistor (M1) ; and a third NMOS transistor (M3) coupled between a drain of the first NMOS transistor (M2) and a drain and a gate of the second PMOS transistor (M4), wherein a gate of the third NMOS transistor (M3) is coupled to the gate of the second NMOS transistor (M1). Holloway shows each and every element of Claim 17 and the rejection is deemed proper.
Dependent claims 18-19 remains rejected for the same reasons set forth above.
Allowable Subject Matter
Claims 8-11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T LAM/Primary Examiner, Art Unit 2842 6/13/2026
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