DETAILED ACTION
Status of Application
Claims 1-18, 22, and 25 are pending in the present application.
The Preliminary Amendment filed 12/19/2024 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/26/2025 and 12/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copies have been filed on 01/30/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 18, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer, US 20130279276 A1, in view of Pyeon, US 20130070540 A1.
Referring to claim 1, Schaefer discloses a semiconductor device comprising:
a logic die comprising a memory controller [fig. 2, 210 comprising 212], an interface circuit [fig. 4A, 422, 424, 426, 428], and a plurality of through silicon vias (TSVs) arranged in a TSV region [fig. 2, element 205]; and
a plurality of memory dies [fig. 2, 220] stacked vertically on the logic die, and connected to the plurality of TSVs [fig. 2, 205],
wherein the interface circuit comprises a plurality of TSV circuit blocks [fig. 4A, 422, 424, 426, 428] being in the TSV region and connected to the plurality of TSVs [fig. 2, 205].
Schaefer does not explicitly disclose wherein the memory controller is configured to operate in a first voltage domain;
wherein the plurality of memory dies is configured to operate in a second voltage domain,
wherein each of the plurality of TSV circuit blocks is configured to convert a voltage level of a signal transmitted via a corresponding TSV among the plurality of TSVs, the voltage level being configured to be converted between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain.
However, Pyeon discloses wherein the memory controller is configured to operate in a first voltage domain [fig. 4, see VDD of 38];
wherein the plurality of memory dies is configured to operate in a second voltage domain [fig. 4, see generation of VPP_S]
wherein each of the plurality of TSV circuit blocks is configured to convert a voltage level of a signal transmitted via a corresponding TSV among the plurality of TSVs [fig. 4, TSVs 204], the voltage level being configured to be converted between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain [fig. 4, see conversion of VDD to VPP_S via generator; paragraph 73, “shows the transmission of VPP_S (i.e. VPP_S current) from the master chip 38 up through the TSVs 24”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Pyeon in the device of Schaefer to implement, wherein the memory controller is configured to operate in a first voltage domain; wherein the plurality of memory dies is configured to operate in a second voltage domain, wherein each of the plurality of TSV circuit blocks is configured to convert a voltage level of a signal transmitted via a corresponding TSV among the plurality of TSVs, the voltage level being configured to be converted between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain, in order to effectively regulate power among slave chips in a 3D stacked multichip package and to get proper voltage levels no matter what the process voltage temperature (PVT) conditions, or any other conditions affecting performance, may be [Pyeon, paragraph 10].
Referring to claim 2, the modified Schaefer discloses the semiconductor device of claim 1, wherein each of the plurality of TSV circuit blocks comprises a TSV macro comprising a hard macro, and the interface circuit comprises a TSV macro array comprising a plurality of TSV macros arranged in an array form [Schaefer, fig. 4A, 422, 426, 428, 424 in array form].
Referring to claim 4, the modified Schaefer discloses the semiconductor device of claim 1, wherein each of the plurality of TSV circuit blocks comprises:
a level shifter configured to change the first voltage level of the signal transmitted via the corresponding TSV to the second voltage level [Pyeon, fig. 4, VPP generator]; and
at least one of a receiver or a transmitter, the receive being configured to receive the signal having the second voltage level via the corresponding TSV [Pyeon, fig. 4, see receiver of 39 depicted as a darkened circle], and the transmitter being configured to transmit the signal having the second voltage level to the plurality of memory dies via the corresponding TSV [Pyeon, fig. 4, see transmitter of 25].
Referring to claim 18, the modified Schaefer discloses the semiconductor device of claim 1, wherein each of the plurality of TSV circuit blocks is connected to one TSV of the plurality of TSVs [Schaefer, fig. 4A, 422, 426, 428, 424 connected to TSVs shown as black vertical lines].
Referring to claim 25, Schaefer discloses a logic die comprising:
a memory controller [fig. 2, 212]
a plurality of through silicon vias (TSVs) arranged in a TSV region [fig. 2, element 205] and electrically connected to a plurality of memory dies [fig. 2, 220]; and
an interface circuit [fig. 4A, 422, 426, 428, 424] between the memory controller and the plurality of TSVs,
wherein the interface circuit comprises a plurality of TSV macros arranged, in the TSV region, in an array form and connected to the plurality of TSVs [fig. 4A, 422, 426, 428, 424 in array form and connected to TSVs 205].
Schaefer does not explicitly disclose the memory controller configured to operate in a first voltage domain;
the plurality of memory dies configured to operate in a second voltage domain;
wherein each of the plurality of TSV macros is configured to convert a voltage level of a signal, transmitted via a corresponding TSV among the plurality of TSVs, to a converted level between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain.
Schaefer does not explicitly disclose the memory controller configured to operate in a first voltage domain;
the plurality of memory dies configured to operate in a second voltage domain;
a signal, transmitted via a corresponding TSV among the plurality of TSVs, to a converted level between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain.
However, Pyeon discloses the memory controller configured to operate in a first voltage domain [fig. 4, see VDD of 38];
the plurality of memory dies configured to operate in a second voltage domain [fig. 4, see generation of VPP_S];
a signal, transmitted via a corresponding TSV among the plurality of TSVs, to a converted level between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain [fig. 4, see conversion of VDD to VPP_S via generator; paragraph 73, “shows the transmission of VPP_S (i.e. VPP_S current) from the master chip 38 up through the TSVs 24”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Pyeon in the logic die of Schaefer to implement, the memory controller configured to operate in a first voltage domain; the plurality of memory dies configured to operate in a second voltage domain; a signal, transmitted via a corresponding TSV among the plurality of TSVs, to a converted level between a first voltage level in the first voltage domain and a second voltage level in the second voltage domain, in order to effectively regulate power among slave chips in a 3D stacked multichip package and to get proper voltage levels no matter what the process voltage temperature (PVT) conditions, or any other conditions affecting performance, may be [Pyeon, paragraph 10].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer, in view of Pyeon, as applied to claim 1 above, and further in view of Kirby, US 20220028789 A1.
Referring to claim 3, the modified Schaefer does not explicitly disclose the semiconductor device of claim 1, wherein the logic die further comprises a metal layer configured to electrically connect components in the logic die to each other.
However, Kirby discloses wherein the logic die further comprises a metal layer configured to electrically connect components in the logic die to each other [paragraph 15, The controller die 105 may also include a layer 108 with conductive traces, such as multiple levels of metal layers and vias (which may also be referred to as interconnects) embedded in a dielectric layer, such that the active components of the controller die 105 may be coupled with the stack of memory dies 125 and conductive components 115 of the controller die 105. In some embodiments, the conductive components 115 may include connection pads including copper (Cu), thin-film metal layer stack configured for conductive pillars and/or under-bump metallization, or the like].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kirby in the device of the modified Schaefer to implement, wherein the logic die further comprises a metal layer configured to electrically connect components in the logic die to each other, in order to provide the shortest possible route for connecting a semiconductor memory stack [Kirby, paragraph 11].
Claim(s) 5 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer, US 20130279276 A1, in view of Pyeon, US 20130070540 A1, and further in view of Kondo, US 20120250387 A1.
Referring to claim 5, the modified Schaefer discloses the semiconductor device of claim 1, wherein the memory controller is configured to operate in a first clock domain [Pyeon, fig. 4, see VDD of 38],
wherein the plurality of memory dies is configured to operate in a second clock domain [Pyeon, fig. 4, see generation of VPP_S].
The modified Schaefer does not explicitly disclose wherein each of the plurality of TSV circuit blocks is configured to:
synchronize signals received from the plurality of memory dies with a controller clock in the first clock domain; or
synchronize a signal received from the memory controller with a memory clock in the second clock domain.
However, Kondo discloses synchronize signals received from the plurality of memory dies with a controller clock in the first clock domain [fig. 7, paragraph 76, “Accordingly, in the core chip CC0, the output circuits RBUFO0 and RBUFO1 in the data FIFO 79a are activated synchronously with the read clock signals RCLKDD0 and RCLKDD1, respectively. As a result, the read data are supplied to the through silicon via TSV1 for data at timings synchronized with the read clock signals RCLKDD0 and RCLKDD1”]; or
synchronize a signal received from the memory controller with a memory clock in the second clock domain.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kondo in the device of the modified Schaefer to implement, wherein each of the plurality of TSV circuit blocks is configured to: synchronize signals received from the plurality of memory dies with a controller clock in the first clock domain; or synchronize a signal received from the memory controller with a memory clock in the second clock domain, in order to provide a high-speed semiconductor memory device having extremely large capacity as a whole [Kondo, paragraph 4].
Referring to claim 22, Schaefer discloses a logic die comprising:
a memory controller [fig. 2, 212];
a plurality of through silicon vias (TSVs) [fig. 2, element 205] arranged in a TSV region and electrically connected to a plurality of memory dies [fig. 2, 220]; and
an interface circuit [fig. 4A, 422, 426, 428, 424] between the memory controller and the plurality of TSVs,
wherein the interface circuit comprises a plurality of TSV macros arranged, in the TSV region, in an array form and connected to the plurality of TSVs [fig. 4A, 422, 426, 428, 424 in array form and connected to TSVs 205].
Schaefer does not explicitly disclose the memory controller configured to operate in a first clock domain;
the plurality of memory dies configured to operate in a second clock domain.
However, Pyeon discloses the memory controller configured to operate in a first clock domain [fig. 4, see VDD of 38];
the plurality of memory dies configured to operate in a second clock domain [fig. 4, see generation of VPP_S];
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Pyeon in the logic die of Schaefer to implement, the memory controller configured to operate in a first clock domain; the plurality of memory dies configured to operate in a second clock domain, in order to effectively regulate power among slave chips in a 3D stacked multichip package and to get proper voltage levels no matter what the process voltage temperature (PVT) conditions, or any other conditions affecting performance, may be [Pyeon, paragraph 10].
The modified Schaefer does not explicitly disclose wherein each of the plurality of TSV macros is configured to:
synchronize signals received from the plurality of memory dies with a controller clock in the first clock domain, or
synchronize a signal received from the memory controller with a memory clock in the second clock domain.
However, Kondo discloses wherein each of the plurality of TSV macros is configured to:
synchronize signals received from the plurality of memory dies with a controller clock in the first clock domain [fig. 7, paragraph 76, “Accordingly, in the core chip CC0, the output circuits RBUFO0 and RBUFO1 in the data FIFO 79a are activated synchronously with the read clock signals RCLKDD0 and RCLKDD1, respectively. As a result, the read data are supplied to the through silicon via TSV1 for data at timings synchronized with the read clock signals RCLKDD0 and RCLKDD1”], or
synchronize a signal received from the memory controller with a memory clock in the second clock domain.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kondo in the logic die of the modified Schaefer to implement, wherein each of the plurality of TSV macros is configured to: synchronize signals received from the plurality of memory dies with a controller clock in the first clock domain, or synchronize a signal received from the memory controller with a memory clock in the second clock domain, in order to provide a high-speed semiconductor memory device having extremely large capacity as a whole [Kondo, paragraph 4].
Allowable Subject Matter
Claims 6-8 and 9-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the plurality of TSV circuit blocks comprise a first TSV macro connected to a first TSV among the plurality of TSVs, and the first TSV macro comprises: a synchronization circuit configured to generate, from a first signal received from the memory controller, a synchronized signal synchronized with the memory clock; and a level shifter configured to change a voltage level of the synchronized signal from the first voltage level to the second voltage level, in combination with other recited limitations in claim 6.
Claims 7-8 are objected to by virtue of their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the plurality of TSV circuit blocks comprise a second TSV macro connected to a second TSV among the plurality of TSVs, and wherein the second TSV macro comprises: a write path configured to generate, from write data received from the memory controller, first synchronized data synchronized with the memory clock; and a level shifter configured to change a voltage level of the first synchronized data from the first voltage level to the second voltage level, in combination with other recited limitations in claim 9.
Claims 10-13 are objected to by virtue of their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the plurality of TSV circuit blocks comprise a third TSV macro connected to a third TSV among the plurality of TSVs, and the third TSV macro comprises: a serializer circuit configured to generate, from first write data and second write data received in parallel from the memory controller, a clock signal synchronized with the memory clock; and a level shifter configured to change a voltage level of the clock signal from the first voltage level to the second voltage level, in combination with other recited limitations in claim 14.
Claims 15-16 are objected to by virtue of their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the plurality of TSV circuit blocks comprise a fourth TSV macro connected to a fourth TSV among the plurality of TSVs, and the fourth TSV macro comprises: a receiver configured to receive a read clock signal in the second clock domain from the plurality of memory dies; and a delay control logic configured to generate a memory read clock signal by delaying the read clock signal for a certain period of time, in combination with other recited limitations in claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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/Farley Abad/Primary Examiner, Art Unit 2181