DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 23 January 2026 is in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. Accordingly, the IDS is being considered by this Examiner.
Claim Objections
Claims 1-20 are objected to because of the following informalities (the following suggested changes were agreed to by the attorney of record Mr. James Bennin [Reg.No.60692] in a telephonic conversation on 23 January 2026):
Per claim 1, line 11, “MLC” should be replaced by “multi-level cell (MLC)” as this is the first recitation of the acronym in the claims.
Per claim 4, line 6, “MLC data buffer” appears to be a typographical error and should be replaced by “data traffic”.
Per claim 5, line 6, “MLC data buffer” appears to be a typographical error and should be replaced by “data traffic”.
Per claim 9, line 2, it would be more appropriate to insert “configured” before “to” so that the various steps performed by the controller will not be interpreted as a intended uses of the claimed invention. Line 5, insert “MLC” before “data traffic”. Line 7, insert “MLC” before “data traffic”. Line 12, insert “MLC” before “data traffic”.
Per claim 10, line 1, insert “configured” before “to”.
Per claim 11, line 1, insert “configured” before “to”. Lind 2, insert “MLC” before “data traffic”. Line 4, insert “MLC” before “data traffic”. Line 6, replace “MLC data buffer” with “data traffic”. Line 8, insert “, when” after “wherein”. Line 9, replace “comprises writing” with “, the controller is configured to write”. Line 10, insert “MLC” before “data traffic”.
Per claim 12, line 1, insert “configured” before “to”. Line 2, insert “MLC” before “data traffic”. Line 4, insert “MLC” before “data traffic”. Line 6, replace “MLC data buffer” with “data traffic”. Line 8, insert “, when” after “wherein”. Line 9, replace “comprises writing” with “, the controller is configured to write”. Line 10, insert “MLC” before “data traffic”.
Per claim 13, line 1, insert “configured” before “to”. Line 2, insert “MLC” before “data traffic”. Line 3, insert “MLC” before “data traffic”.
Per claim 16, line 7, insert “MLC” before “data traffic”. Line 10, insert “MLC” before “data traffic”. Line 12, insert “MLC” before “data traffic”. Line 14, insert “MLC” before “data traffic”. Line 15, insert “MLC” before “data traffic”. Line 18, insert “MLC” before “data traffic”. Line 19, insert “MLC” before “data traffic”.
Per claim 17, line 3, insert “MLC” before “data traffic”.
Per claim 18, line 2, insert “MLC” before “data traffic”.
Per claim 19, line 1, delete “wherein the program instructions comprise:”. Lines 2-7, delete the lines. Line 8, replace “writing” with “the program instructions to write”. Line 9, replace “comprises writing” with “comprise program instructions to write”. Line 10, insert “MLC” before “data traffic”.
Per claim 20, line 2, insert “MLC” before “data traffic”. Line 3, insert “MLC” before “data traffic”.
All dependent claims are objected to as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 16-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to a computer program product comprising one or more computer readable storage medium without the specification providing a definition for the claimed “Computer Readable Storage media” (CRSM). A broadest reasonable interpretation for the term “CRSM” would include both statutory embodiments and non-statutory embodiments such as signals. The words "storage" and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claims are drawn to a form of energy. Energy is not one of the four categories of invention and therefore these claims are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter. The Examiner suggests amending the claims to read as a “non-transitory Computer-readable storage medium” (the specification describes a non-transitory computer-readable medium in paragraph [0056], and the suggested changes were agreed to by the attorney of record Mr. James Bennin [Reg.No.60692] in a conversation on 23 January 2026).
All dependent claims are rejected as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-10 and 13-15 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Avila et al. [Pub.No. 20150012684 A1] (hereinafter “Avila”).
Independent Claims:
Per independent claim 1, Avila teaches:
A method performed by a storage device (see Fig. 1, memory system 90; also see Fig. 11, memory system 141), comprising:
receiving a first page of data traffic (see paragraph [0088] and Fig. 17, step 223, receiving lower page LP and buffering at one or more on-chip latches) at a first buffer of a storage medium (see Fig. 11 for on-chip latches 147 of 3-D memory array 143);
writing, from the first buffer, the first page of the data traffic to a first block having a first cell level (see paragraph [0088] and Fig. 17, step 225, LP data buffered in on-chip latches is stored in one or more blocks of SLC memory; further see Fig. 10 for SLC blocks in 3-D memory array);
receiving, during the writing of the first page, a second page of the data traffic at a second buffer of the storage medium (see paragraph [0088] and Fig. 17, in step 227 an upper page is transferred in parallel with programming of the LP data in SLC in step 225, the upper page is buffered in one or more on-chip latches of 3-D memory array 143);
writing, from the second buffer, the second page of the data traffic to a second block having the first cell level (see paragraph [0088] and Fig. 17, upper page buffered in one or more on-chip latches is programmed in one or more SLC memory blocks in step 229); and
writing, from the first buffer and the second buffer without an additional transfer to the storage medium of the data traffic, the first page and the second page of the data traffic to an MLC block having a second cell level that is greater than the first cell level (see paragraph [0088] and Fig. 17, in step 233, lower and upper page data buffered in on-chip latches are programmed in MLC memory blocks of 3-D memory array 143 without any additional external data transfer to 3-D memory array 143; further see Fig. 10 for MLC blocks in 3-D memory array).
Per independent claim 9, the claim is directed to a system (see Fig. 1, memory system 90; also see Fig. 11, memory system 141) comprising a controller of a non-volatile memory device (see Fig. 11, controller 155 of memory die 145) performing substantially identical steps performed by claim 1’s method. As such the claim is rejected on the same ground as claim 1 in view of Avila mutatis mutandis. Avila further teaches the claimed data traffic is multi-level cell (MLC) data traffic (see Fig. 11, the storage medium for storing data is a 3-D memory array 143 in which data is programmed in MLC format; see paragraphs [0068], [0074], and [0087], the data is programmed in MLC and consists of more than one bit per cell).
Dependent Claims:
Per claim 2, Avila further teaches performing an error check for the MLC block based at least in part on the data traffic stored on the first block and the second block (see paragraph [0090], lines 22-25, performing error checking on the high error rate portion/MLC block by comparing sampled data from a MLC block with corresponding data in the low error rate portion/SLC blocks to determine the number of errors).
Per claim 3, Avila further teaches programming the data traffic on the MLC block after performing the error check (see paragraph [0090], lines 33-37, when a high error rate block does not meet the standard (after the error check), copy/program data read from the low error rate portion to a new block in the high error rate portion/MLC block).
Per claim 6, Avila further teaches erasing the data traffic from the first block and second block after writing the first page and the second page of the data traffic to the MLC block (see Avila’s claim 8, “subsequently erasing the first and second portions of data in the SLC portion only after .. the MLC portion of the memory array contains an accurate copy of the first and second portions of data”).
Per claim 7, Avila further teaches the second cell level comprises: a two-level cell, a triple-level cell (TLC), a quad-level cell (QLC), or a penta-level cell (PLC) (see paragraphs [0067]-[0068] and [0078], higher MLC portion including two, three or four bits per cell).
Per claim 8, Avila further teaches the first cell level comprises: a single-level cell (SLC), a two-level cell, a triple-level cell (TLC), or a quad-level cell (QLC) (see paragraphs [0067]-[0068] and [0078], the lower density portion may be SLC with one bit per cell, or a MLC with two or three bits per cell).
Per claim 10, the claim is the system claim corresponding to the method claim 2, as such it is rejected on the same grounds mutatis mutandis.
Per claim 13, the claim is the system claim corresponding to the method claim 6, as such it is rejected on the same grounds mutatis mutandis.
Per claim 14, Avila further teaches the second cell level comprises: a triple-level cell (TLC), a quad-level cell (QLC), or a penta-level cell (PLC) (see paragraphs [0067]-[0068] and [0078], higher density MLC portion can include three or four bits per cell).
Per claim 15, Avila further teaches the first cell level comprises: a single-level cell (SLC), a triple-level cell (TLC), or a quad-level cell (QLC) (see paragraphs [0067]-[0068] and [0078], the lower density portion may be SLC with one bit per cell, or a MLC with three bits per cell).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 11-12 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Avila, in further view of Khakifirooz et al. [Pub.No.: US 20190006016 A1] (hereinafter “Khakifirooz”).
Independent Claim:
Per claim 16, Avila teaches:
A method performed by a storage device (see Fig. 1, memory system 90; also see Fig. 11, memory system 141), comprising:
receiving a first page of data traffic (see paragraph [0088] and Fig. 17, step 223, receiving lower page LP and buffering at one or more on-chip latches) at a first buffer of a storage medium (see Fig. 11 for on-chip latches 147 of 3-D memory array 143);
writing, from the first buffer, the first page of the data traffic to a first block having a first cell level (see paragraph [0088] and Fig. 17, step 225, LP data buffered in on-chip latches is stored in one or more blocks of SLC memory; further see Fig. 10 for SLC blocks in 3-D memory array);
receiving, during the writing of the first page, a second page of the data traffic at a second buffer of the storage medium (see paragraph [0088] and Fig. 17, in step 227 an upper page is transferred in parallel with programming of the LP data in SLC in step 225, the upper page is buffered in one or more on-chip latches of 3-D memory array 143);
writing, from the second buffer, the second page of the data traffic to a second block having the first cell level (see paragraph [0088] and Fig. 17, upper page buffered in one or more on-chip latches is programmed in one or more SLC memory blocks in step 229); and
writing, from the first buffer and the second buffer without an additional transfer to the storage medium of the data traffic, the first page and the second page of the data traffic to an MLC block having a second cell level that is greater than the first cell level (see paragraph [0088] and Fig. 17, in step 233, lower and upper page data buffered in on-chip latches are programmed in MLC memory blocks of 3-D memory array 143 without any additional external data transfer to 3-D memory array 143; further see Fig. 10 for MLC blocks in 3-D memory array).
Avila does not specifically recite:
to receive, during the writing of the second page, a third page of the data traffic at a third buffer of the storage medium;
to write, from the third buffer, the third page of the data traffic to a third block having the first cell level; and
to write, from the third buffer without an additional transfer to the storage medium of the data traffic, the third page of the data traffic to an MLC block having a second cell level that is greater than the first cell level.
Avila’s inventive objective is to reduce data storage and access latency in a 3-D memory array by separating multi-level cell data into logical pages to be individually buffered in on-chip latches, from where the logical pages are programmed together into MLC memory portion (see entire paragraph [0088]). The embodiment shown in Avila’s Fig. 17 and paragraph [0088] is related to two bits per cell two-level MLC memory data, therefore the embodiment discloses two logical pages (lower and upper pages) received and buffered in overlapping fashion, and later programmed simultaneously into a MLC portion. Avila further teaches an embodiment of storing more than two bits per cell and use of middle page data (see paragraph [0074], lines 8-11). Avila also teaches various MLC formats such as TLC and QLC (see paragraph [0068], lines 8-16). Given Avila’s inventive objective, in a situation where the data comprises three bits per cell (TLC), it would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to modify Avila’s teachings in paragraph [0088] and Fig. 17, to separate the data into three logical pages (lower, middle and upper pages) to be received and buffered in overlapping fashion and later to be simultaneously programmed in TLC memory portion in order to reduce programming latency. One of the three logical pages (lower, middle and upper pages) is mapped to the claimed third page of the data traffic. The one or more on-chip latches storing the third page is mapped to the claimed third buffer, and this third page is programmed to a MLC/TLC block together with the claimed first and second pages without an additional external transfer as it is internally transferred to the TLC from an on-chip latch.
Avila does not specifically teach a computer program product comprising one or more computer readable storage media storing program instructions for performing the steps of claim 16 set forth above. Avila teaches the controller 100 includes a processor 120 (see paragraph [0037] and Fig. 1). It is well known in the art that software implementation of a memory controller’s functions provides benefits such as adaptability and reduced hardware cost. Khakifirooz teaches an analogous MLC memory device comprising a controller executing software control application (see Khakifirooz, entire paragraph [0019]). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to implement Avila’s controller using software or firmware for the benefits of adaptability and reduced hardware cost.
Dependent Claims:
Per claim 4, the claim’s receiving and both writing steps on lines 2-7 are similarly taught in claim 16 as set forth above and are rejected using the same rationale. Avila further teaches writing the first page, the second page, and the third page to the MLC block comprises writing the first page, the second page, and the third page to the MLC block after writing the third page of the data traffic to the third block having the first cell level (as explained in the rejection of claim 16 set forth above, the first, second and third pages are first programmed to separate SLC blocks before written together to MLC blocks).
Per claim 5, the claimed steps of receiving a fourth page during the writing of the third page at a fourth buffer, writing the fourth page from the fourth buffer to a fourth block with the first cell level, and writing the fourth page to the MLC block without additional transfer to the storage medium can be made obvious using similar rationale set forth in the rejection of claim 16 above. The instant claim describes a situation where the MLC is a QLC (four bits per cell). As Avila teaches a QLC (see paragraph [0068], lines 8-16), and given Avila’s inventive objective, it would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to modify Avila’s teachings in paragraph [0088] and Fig. 17, to separate the data into four logical pages to be received and buffered in overlapping fashion and later to be simultaneously programmed in QLC memory portion in order to reduce programming latency. One of the four logical pages is mapped to the claimed fourth page of the data traffic. The one or more on-chip latches storing the fourth page is mapped to the claimed fourth buffer, and this fourth page is programmed to a QLC block together with the claimed first, second and third pages without an additional external transfer as it is internally transferred to the QLC from an on-chip latch. Furthermore, the writing of the first, second, third and fourth pages to the MLC block occurs after writing the fourth page to the fourth block (the logical pages are first programmed to separate SLC blocks before written together to MLC blocks).
Per claim 11, the claim is the system claim corresponding to the method claim 4, as such it is rejected on the same grounds mutatis mutandis.
Per claim 12, the claim is the system claim corresponding to the method claim 5, as such it is rejected on the same grounds mutatis mutandis.
Per claim 17, Avila further teaches program instructions to perform an error check for the MLC block based at least in part on the data traffic stored on the first block and the second block (see paragraph [0090], lines 22-25, performing error checking on the high error rate portion/MLC block by comparing sampled data from a MLC block with corresponding data in the low error rate portion/SLC blocks to determine the number of errors).
Per claim 18, Avila further teaches program instructions to program the data traffic on the MLC block after performing the error check (see paragraph [0090], lines 33-37, when a high error rate block does not meet the standard (after the error check), copy/program data read from the low error rate portion to a new block in the high error rate portion/MLC block).
Per claim 19, the limitations on lines 2-7 should be deleted as set forth above in the objection of the instant claim, as they are limitations already recited in claim 16. Avila further teaches writing the first page, the second page, and the third page to the MLC block comprises writing the first page, the second page, and the third page to the MLC block after writing the third page of the data traffic to the third block having the first cell level (as explained in the rejection of claim 16 set forth above, the first, second and third pages are first programmed to separate SLC blocks before written together to MLC blocks).
Per claim 20, Avila further teaches program instructions to erase the data traffic from the first block and the second block after writing the first page and the second page of the data traffic to the MLC block (see Avila’s claim 8, “subsequently erasing the first and second portions of data in the SLC portion only after .. the MLC portion of the memory array contains an accurate copy of the first and second portions of data”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shawn Gu whose telephone number is (571) 272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
24 January 2026