Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/23/206 is considered.
Response to Amendment
The office action is responding to the arguments filed on 04/07/2026. Claims 1-20 are pending. Applicant’s amendments for 35 U.S.C. 101 rejection is considered and accepted. The rejection of 35 U.S.C. 101 is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-5, 8-10, 12-13 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over IONIN et al. (US 20230162808 A1) in view of Yang et al. (US 20170062069 A1) hereinafter IONIN and Yang.
Regarding claim 1, IONIN teaches A method performed by A storage device, the
method comprising: (See Fig 3, paragraph [0041], illustrates a flow diagram of a method 300 where controller manages data written to flash memory during the program and erase operation in different cell level to the memory blocks)
performing an erase operation, using a first cell level, on a block, wherein the block is configured for write operations using a second cell level that is less than the first cell level; and (See Fig 2B, paragraph [0036], illustrates a voltage distribution curve with TLC erase and SLC programming. In other words, a block of NVM (Fig 2) is erased in TLC mode which is triple bit cell level and programmed in SLC which is single bit cell level)
IONIN teaches non volatile memory cell level erase and program above. However, IONIN does not explicitly teach performing write operation, using the second cell level, on the block after performing the erase operation, wherein the write operation, using the second cell level, is performed on the block in an erase state associated with the first cell level, and
wherein the erase operation, using the first level cell, is performed and the write operation, using the second cell level, is performed after performing the erase operation to reduce errors associated with a partial block write operation
On the other hand, Yang which also relates to non volatile memory cell level erase and program teaches and performing write operation, using the second cell level, on the block after performing the erase operation, wherein the write operation, using the second cell level, is performed on the block in an erase state associated with the first cell level, and (See Fig 5, paragraph [0042], illustrates multiple bit per cell memory can be programmed in SLC mode after fresh erase which is done based on multiple bit erase. In other words, second cell level or SLC level programming operation is performed after first cell level or multi bit cell level erase)
wherein the erase operation, using the first level cell, is performed and the write operation, using the second cell level, is performed after performing the erase operation to reduce errors associated with a partial block write operation (See Fig 6, paragraph [0044], illustrates SLC programming after multi bit cell erase increases read margin and reduces error)
Both IONIN and Yang relate to non volatile memory cell level erase and program
(see IONIN, abstract, and see Yang, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Yang by memory cell level erase
and program, as taught by Yang, to enable multiple bit per cell memory can be programmed in SLC mode after fresh erase which is done based on multiple bit erase and SLC programming after multi bit cell erase increases read margin and reduces error. The combined system of IONIN – Yang allows smart management of the data written to the flash memory during the program and erase operation to the memory blocks and by doing so, the erase counts to the memory may be effectively reduced while the performance of the write can be enhanced as mentioned in paragraph [0015]. Therefore, the combination of IONIN - Yang improves endurance and faster programming. See Yang, paragraph [0001].
Regarding claim 2, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 1. However, IONIN – Yang combination does not explicitly teach The method of claim 1, wherein the first cell level is associated with a first quantity of bits per cell, wherein the second cell level is associated with a second quantity of bits per cell, and wherein the second quantity of bits per cell is less than the first quantity of bits per cell
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The method of claim 1, wherein the first cell level is associated with a first quantity of bits per cell, wherein the second cell level is associated with a second quantity of bits per cell, and wherein the second quantity of bits per cell is less than the first quantity of bits per cell. (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is less bit quantity cell level than TLC erase which is triple bit cell level)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 1 is equally applicable to claim 2.
Regarding claim 4, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 2. However, IONIN – Yang combination does not explicitly teach The method of claim 2, wherein the second cell level has at least two fewer bits per cell than the first cell level
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The method of claim 2, wherein the second cell level has at least two fewer bits per cell than the first cell level. (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is two fewer bit cell level than TLC erase which is triple bit cell level)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 1 is equally applicable to claim 4.
Regarding claim 5, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 1. However, IONIN – Yang combination does not explicitly teach The method of claim 1, wherein the second cell level is associated with a single-level cell (SLC); and wherein the first cell level is associated with a triple-level cell (TLC)
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The method of claim 1, wherein the second cell level is associated with a single-level cell (SLC); and wherein the first cell level is associated with a triple-level cell (TLC). (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is two fewer bit cell level than TLC erase which is triple bit cell level)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 1 is equally applicable to claim 5.
Regarding claim 8, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 1. However, IONIN – Yang combination does not explicitly teach The method of claim 1, comprising performing a read operation on the block, wherein the read operation comprises: sensing voltage values of cells of the block having data written thereon; and
applying a first read voltage threshold associated with the first cell level, a second read voltage threshold associated with the second cell level, or a third read voltage threshold that is between the first read voltage threshold and the second read voltage threshold
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The method of claim 1, comprising performing a read operation on the block, wherein the read operation comprises: sensing voltage values of cells of the block having data written thereon; and (See Fig 1 and 2A, paragraph [0033] and [0034], illustrates controller 108 may manage the reading of data from and/or the writing of data to the NVM 110 which includes sensing the voltage of a cell and the voltage for a certain cell state)
applying a first read voltage threshold associated with the first cell level, a second read voltage threshold associated with the second cell level, or a third read voltage threshold that is between the first read voltage threshold and the second read voltage threshold. (See Fig 8, paragraph [0059], illustrates controller 108 determines if the blocks passes the SLC pre-erase threshold at block 808 and block 812 If the blocks passes the TLC pre-erase threshold. In other words, controller determines first and second level read voltage threshold)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, IONIN teaches A system comprising: a controller, of a non-volatile memory device, to: (See Fig 1, paragraph [0028], illustrates storage system 106 which includes a controller 108, NVM 110)
identify a block for programming using a first cell level; perform an erase operation, having a second cell level that is greater than the first cell level, on the block based at least in part on the block being associated with write operations using the first cell level; and (See Fig 2C, paragraph [0037], illustrates a voltage distribution curve with SLC erase and TLC programming. In other words, a block of NVM (Fig 2) is erased in SLC mode which is triple bit cell level and programmed in TLC which is single bit cell level)
IONIN teaches non volatile memory cell level erase and program above. However, IONIN does not explicitly teach perform a write operation, on the block, using the first cell level after performing the erase operations wherein the write operation, using the first cell level, is performed on the block in an erase state associated with the second cell level, and
wherein the erase operation is performed and the write operation is performed after the erase operation to reduce errors associated with a partial block write operation
On the other hand, Yang which also relates to non volatile memory cell level erase and program teaches perform a write operation, on the block, using the first cell level after performing the erase operations wherein the write operation, using the first cell level, is performed on the block in an erase state associated with the second cell level, and (See Fig 5, paragraph [0042], illustrates multiple bit per cell memory can be programmed in SLC mode after fresh erase which is done based on multiple bit erase. In other words, second cell level or SLC level programming operation is performed after first cell level or multi bit cell level erase)
wherein the erase operation is performed and the write operation is performed after the erase operation to reduce errors associated with a partial block write operation (See Fig 6, paragraph [0044], illustrates SLC programming after multi bit cell erase increases read margin and reduces error)
Both IONIN and Yang relate to non volatile memory cell level erase and program
(see IONIN, abstract, and see Yang, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Yang by memory cell level erase
and program, as taught by Yang, to enable multiple bit per cell memory can be programmed in SLC mode after fresh erase which is done based on multiple bit erase and SLC programming after multi bit cell erase increases read margin and reduces error. The combined system of IONIN – Yang allows smart management of the data written to the flash memory during the program and erase operation to the memory blocks and by doing so, the erase counts to the memory may be effectively reduced while the performance of the write can be enhanced as mentioned in paragraph [0015]. Therefore, the combination of IONIN - Yang improves endurance and faster programming. See Yang, paragraph [0001].
Regarding claim 10, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 9. However, IONIN – Yang combination does not explicitly teach The system of claim 9, wherein the first cell level is associated with a first quantity of bits per cell, wherein the second cell level is associated with a second quantity of bits per cell, and wherein the second quantity of bits per cell is greater than the first quantity of bits per cell
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The system of claim 9, wherein the first cell level is associated with a first quantity of bits per cell, wherein the second cell level is associated with a second quantity of bits per cell, and wherein the second quantity of bits per cell is greater than the first quantity of bits per cell. (See Fig 2C, paragraph [0037], illustrates TLC program which is triple bit cell level is greater bit quantity cell level than SLC erase which is single bit cell level)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 9 is equally applicable to claim 10.
Regarding claim 12, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 10. However, IONIN – Yang combination does not explicitly teach The system of claim 10, wherein the first cell level has at least two fewer bits per cell than the first cell level
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The system of claim 10, wherein the first cell level has at least two fewer bits per cell than the first cell level. (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is two fewer bit cell level than TLC erase which is triple bit cell level)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 9 is equally applicable to claim 12.
Regarding claim 13, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 9. However, IONIN – Yang combination does not explicitly teach The system of claim 9, wherein the first cell level is associated with a single-level cell (SLC); and wherein the second cell level is associated with a triple-level cell (TLC)
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The system of claim 9, wherein the first cell level is associated with a single-level cell (SLC); and wherein the second cell level is associated with a triple-level cell (TLC). (See Fig 2C, paragraph [0037], illustrates SLC erase which is single bit cell level is two fewer bit cell level than TLC program which is triple bit cell level)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 9 is equally applicable to claim 13.
Regarding claim 16, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 9. However, IONIN – Yang combination does not explicitly teach The system of claim 9, wherein to the controller is to perform a read operation on the block, the read operation comprising: sensing of voltage values of cells of the block having data written thereon; and
application of a first read voltage threshold associated with the first cell level, a second read voltage threshold associated with the second cell level, or a third read voltage threshold that is between the first read voltage threshold and the second read voltage threshold
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The system of claim 9, wherein to the controller is to perform a read operation on the block, the read operation comprising: sensing of voltage values of cells of the block having data written thereon; and (See Fig 1 and 2A, paragraph [0033] and [0034], illustrates controller 108 may manage the reading of data from and/or the writing of data to the NVM 110 which includes sensing the voltage of a cell and the voltage for a certain cell state)
application of a first read voltage threshold associated with the first cell level, a second read voltage threshold associated with the second cell level, or a third read voltage threshold that is between the first read voltage threshold and the second read voltage threshold. (See Fig 8, paragraph [0059], illustrates controller 108 determines if the blocks passes the SLC pre-erase threshold at block 808 and block 812 If the blocks passes the TLC pre-erase threshold. In other words, controller determines first and second level read voltage threshold)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 9 is equally applicable to claim 16.
Regarding claim 17, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 9. However, IONIN – Yang combination does not explicitly teach The system of claim 9, wherein a first portion of the block having data written thereon is electrically coupled to a second portion of the block that is unprogrammed via bit lines
On the other hand, IONIN which also relates to non volatile memory cell level erase and program teaches The system of claim 9, wherein a first portion of the block having data written thereon is electrically coupled to a second portion of the block that is unprogrammed via bit lines. (See Fig 3, paragraph [0070], illustrates data can be internally migrated from the first portion of the non-volatile memory to a second portion of the non-volatile memory. In other words first portion is electrically coupled to second portion of NVM memory)
The same motivation that was utilized for combining IONIN and Yang as set
forth in claim 9 is equally applicable to claim 17.
Regarding claim 18, IONIN teaches A computer program product comprising: one or more non-transitory computer-readable medium, and program instructions collectively stored on the one or more non-transitory computer- readable medium, the program instructions comprising: (See Fig 1, paragraph [0032], illustrates controller 108 may use volatile memory 112 as a cache to store information or instructions for programming to NVM 110)
program instructions to perform an erase operation, having a first cell level, on a block associated with write operations having a second cell level that is less than the first cell level; program instructions to perform a write operation having the second cell level; and (See Fig 2B, paragraph [0036], illustrates a voltage distribution curve with TLC erase and SLC programming. In other words, a block of NVM (Fig 2) is erased in TLC mode which is triple bit cell level and programmed in SLC which is single bit cell level)
program instructions to perform a read operation on the block using a threshold voltage that is associated with the first cell level, the second cell level, or a voltage that is between an erase voltage of the first cell level and an erase voltage of the second cell level. (See Fig 8, paragraph [0059], illustrates controller 108 determines if the blocks passes the SLC pre-erase threshold at block 808 and block 812 If the blocks passes the TLC pre-erase threshold. In other words, controller determines first and second level read voltage threshold)
IONIN teaches non volatile memory cell level erase and program above. However, IONIN does not explicitly teach wherein the write operation, having the second cell level, is performed on the block in an erase state associated with the first cell level, and
wherein the erase operation is performed and the write operation is performed after the erase operation to reduce errors associated with a partial block write operation
On the other hand, Yang which also relates to non volatile memory cell level erase and program teaches wherein the write operation, having the second cell level, is performed on the block in an erase state associated with the first cell level, and (See Fig 5, paragraph [0042], illustrates multiple bit per cell memory can be programmed in SLC mode after fresh erase which is done based on multiple bit erase. In other words, second cell level or SLC level programming operation is performed after first cell level or multi bit cell level erase)
wherein the erase operation is performed and the write operation is performed after the erase operation to reduce errors associated with a partial block write operation (See Fig 6, paragraph [0044], illustrates SLC programming after multi bit cell erase increases read margin and reduces error)
Both IONIN and Yang relate to non volatile memory cell level erase and program
(see IONIN, abstract, and see Yang, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Yang by memory cell level erase
and program, as taught by Yang, to enable multiple bit per cell memory can be programmed in SLC mode after fresh erase which is done based on multiple bit erase and SLC programming after multi bit cell erase increases read margin and reduces error. The combined system of IONIN – Yang allows smart management of the data written to the flash memory during the program and erase operation to the memory blocks and by doing so, the erase counts to the memory may be effectively reduced while the performance of the write can be enhanced as mentioned in paragraph [0015]. Therefore, the combination of IONIN - Yang improves endurance and faster programming. See Yang, paragraph [0001].
Claim(s) 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable
over IONIN in view of Yang and further in view of LEE et al. (US 20250123751 A1) hereinafter LEE.
Regarding claim 3, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 2. However, IONIN – Yang combination does not explicitly teach The method of claim 2, wherein the second cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the first cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell
On the other hand, LEE which also relates to non volatile memory cell level erase
and program in power loss event teaches The method of claim 2, wherein the second cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the first cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell. (See Fig 1, paragraph [0043], illustrates NVM 110 may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with LEE by memory cell level erase and program in power loss event, as taught by LEE, to enable NVM 110 which may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell. The combined system of IONIN – Yang – LEE allows controller to employ mechanism in various SSD architectures, such as an SSD architecture that uses fixed block counts for each block type pool (e.g., SLC block pools, MLC block pools, etc.) as mentioned in paragraph [0038]. Therefore, the combination of IONIN – Yang - LEE improves the performance memory systems. See LEE, paragraph [0061].
Regarding claim 11, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 10. However, IONIN – Yang combination does not explicitly teach The system of claim 10, wherein the first cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the second cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell
On the other hand, LEE which also relates to non volatile memory cell level erase
and program in power loss event teaches The system of claim 10, wherein the first cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the second cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell. (See Fig 1, paragraph [0043], illustrates NVM 110 may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with LEE by memory cell level erase and program in power loss event, as taught by LEE, to enable NVM 110 which may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell. The combined system of IONIN – Yang – LEE allows controller to employ mechanism in various SSD architectures, such as an SSD architecture that uses fixed block counts for each block type pool (e.g., SLC block pools, MLC block pools, etc.) as mentioned in paragraph [0038]. Therefore, the combination of IONIN – Yang - LEE improves the performance memory systems. See LEE, paragraph [0061].
Claim(s) 6-7, 14-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over IONIN in view of Yang and further in view of Zhou et al. (US 20230385191 A1) hereinafter Zhou.
Regarding claim 6, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 1. However, IONIN – Yang combination does not explicitly teach The method of claim 1, wherein the block write operation is associated with one or more of: a power loss event, writing data from a volatile medium of the storage device to a non-volatile medium of the storage device
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The method of claim 1, wherein the block write operation is associated with one or more of: a power loss event, writing data from a volatile medium of the storage device to a non-volatile medium of the storage device. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Yang – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN – Yang - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 7, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 1. However, IONIN – Yang combination does not explicitly teach The method of claim 1, wherein a first portion of the block having data written thereon is electrically coupled to a second portion of the block that is unprogrammed via bit lines
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The method of claim 1, wherein a first portion of the block having data written thereon is electrically coupled to a second portion of the block that is unprogrammed via bit lines. (See Fig 3, paragraph [0070], illustrates data can be internally migrated from the first portion of the non-volatile memory to a second portion of the non-volatile memory. In other words first portion is electrically coupled to second portion of NVM memory)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable data can be internally migrated from the first portion of the non-volatile memory to a second portion of the non-volatile memory or in other words first portion is electrically coupled to second portion of NVM memory. The combined system of IONIN – Yang – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN – Yang - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 14, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 9. However, IONIN – Yang combination does not explicitly teach The system of claim 9, wherein the write operation is associated with a power loss event
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The system of claim 9, wherein the write operation is associated with a power loss event. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Yang – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN – Yang - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 15, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 9. However, IONIN – Yang combination does not explicitly teach The system of claim 9, wherein the write operation is associated with writing data from a volatile medium of a storage device to a non-volatile medium of the storage device
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The system of claim 9, wherein the write operation is associated with writing data from a volatile medium of a storage device to a non-volatile medium of the storage device. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Yang – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN – Yang - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 19, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 18. However, IONIN – Yang combination does not explicitly teach The computer program product of claim 18, wherein the write operation is associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The computer program product of claim 18, wherein the write operation is associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Yang – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN – Yang - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 20, IONIN in view of Yang teaches non volatile memory cell level erase and program teaches in claim 18. However, IONIN – Yang combination does not explicitly teach The computer program product of claim 18, wherein the write operation is further associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The computer program product of claim 18, wherein the write operation is further associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device. (See Fig 1 and 3, paragraph [0067], illustrates at step 336 data can be written from the volatile memory 140 to the first portion of the multi-level non-volatile memory 130)
Both IONIN and Yang and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Yang, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN – Yang combination with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 336 data to be written from the volatile memory 140 to the first portion of the multi-level non-volatile memory 130. The combined system of IONIN – Yang – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN – Yang - Zhou improves write-back policy. See Zhou, paragraph [0014].
Response to Arguments
Applicant’s arguments filed on 04/07/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1, 9 and 18 amendments mapping by
Primary and secondary references IONIN and Zhou in page 9 of the response: Therefore, the combination of IONIN and ZHOU relies on impermissible hindsight, as IONIN provides no motivation to combine a disparaged programming of SLC data in a TLC erased block with any alleged teaching of ZHOU.
For at least the foregoing reasons, IONIN and ZHOU cannot be combined to disclose or suggest "wherein the write operation, using the second cell level, is performed on the block in an erase state associated with the first cell level [the second cell level being is less than the first cell level], and wherein the erase operation, using the first level cell, is performed and the write operation, using the second cell level, is performed after performing the erase operation to reduce errors associated with a partial block write operation," as recited in claim 1, as amended
In summary, applicant argued that primary and secondary references IONIN and Zhou do not teach amended limitation write operation is performed using second level cell after the erase operation which is done in first level cell. The amendment necessitates adding secondary reference Yang in this regard. For further clarification examiner cites portion from Yang. Also, for applicant’s understanding examiner would like to explain the teachings of Yang and examiner’s interpretation in more detail here.
See Fig 5, paragraph [0042], Yang teaches multiple bit per cell memory can be programmed in SLC mode after fresh erase which is done based on multiple bit erase. In other words, second cell level or SLC level programming operation is performed after first cell level or multi bit cell level erase. Also See Fig 6, paragraph [0044], Yang teaches SLC programming after multi bit cell erase increases read margin and reduces error. In the cited portions Yang clearly teaches second cell level or SLC level programming operation is performed after first cell level or multi bit cell level erase and SLC programming after multi bit cell erase increases read margin and reduces error. Thus, the rejection of amended claims 1, 9 and 18 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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