Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) is not submitted.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is
directed to non-statutory subject matter. Claims 18-20 recite a computer readable
storage media storing computer program instructions which when executed. However, the claim does not recite a non-transitory nature of "computer readable storage media," which is also mentioned in paragraph [0009] of the Specification and also does not
exclude signals. Therefore, the current claim language is considered to include signals
per se. It is suggested that claims 18-20 be amended to recite a “non transitory”
computer readable storage media to overcome the rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 8-10, 12-13 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by IONIN et al. (US 20230162808 A1) hereinafter IONIN.
Regarding claim 1, IONIN teaches A method performed by A storage device, the
method comprising: (See Fig 3, paragraph [0041], illustrates a flow diagram of a method 300 where controller manages data written to flash memory during the program and erase operation in different cell level to the memory blocks)
performing an erase operation, associated with a first cell level, on a block based at least in part on a configuration to perform write operations on the block using a second cell level that is less than the first cell level; and (See Fig 2B, paragraph [0036], illustrates a voltage distribution curve with TLC erase and SLC programming. In other words, a block of NVM (Fig 2) is erased in TLC mode which is triple bit cell level and programmed in SLC which is single bit cell level)
performing the write operation after performing the erase operation. (See Fig 1, paragraph [0041], illustrates a hybrid block of NVM 110 can be SLC or TLC programmed after erase)
Regarding claim 2, IONIN teaches The method of claim 1, wherein the first cell level is associated with a first quantity of bits per cell, wherein the second cell level is associated with a second quantity of bits per cell, and wherein the second quantity of bits per cell is less than the first quantity of bits per cell. (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is less bit quantity cell level than TLC erase which is triple bit cell level)
Regarding claim 4, IONIN teaches The method of claim 2, wherein the second cell level has at least two fewer bits per cell than the first cell level. (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is two fewer bit cell level than TLC erase which is triple bit cell level)
Regarding claim 5, IONIN teaches The method of claim 1, wherein the second cell level is associated with a single-level cell (SLC); and wherein the first cell level is associated with a triple-level cell (TLC). (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is two fewer bit cell level than TLC erase which is triple bit cell level)
Regarding claim 8, IONIN teaches The method of claim 1, comprising performing a read operation on the block, the read operation comprising: sensing voltage values of cells of the block having data written thereon; and (See Fig 1 and 2A, paragraph [0033] and [0034], illustrates controller 108 may manage the reading of data from and/or the writing of data to the NVM 110 which includes sensing the voltage of a cell and the voltage for a certain cell state)
applying a first read voltage threshold associated with the first cell level, a second read voltage threshold associated with the second cell level, or a third read voltage threshold that is between the first read voltage threshold and the second read voltage threshold. (See Fig 8, paragraph [0059], illustrates controller 108 determines if the blocks passes the SLC pre-erase threshold at block 808 and block 812 If the blocks passes the TLC pre-erase threshold. In other words, controller determines first and second level read voltage threshold)
Regarding claim 9, IONIN teaches A system comprising: a controller, of a non-volatile memory device, to: (See Fig 1, paragraph [0028], illustrates storage system 106 which includes a controller 108, NVM 110)
identify a block for programming using a first cell level; perform an erase operation, having a second cell level that is greater than the first cell level, on the block based at least in part on the block being associated with programming using the first cell level; and (See Fig 2C, paragraph [0037], illustrates a voltage distribution curve with SLC erase and TLC programming. In other words, a block of NVM (Fig 2) is erased in SLC mode which is triple bit cell level and programmed in TLC which is single bit cell level)
perform a write operation using the first cell level after performing the erase operation. (See Fig 1, paragraph [0041], illustrates and hybrid block of NVM 110 can be SLC or TLC programmed after erase)
Regarding claim 10, IONIN teaches The system of claim 9, wherein the first cell level is associated with a first quantity of bits per cell, wherein the second cell level is associated with a second quantity of bits per cell, and wherein the second quantity of bits per cell is greater than the first quantity of bits per cell. (See Fig 2C, paragraph [0037], illustrates TLC program which is triple bit cell level is greater bit quantity cell level than SLC erase which is single bit cell level)
Regarding claim 12, IONIN teaches The system of claim 10, wherein the first cell level has at least two fewer bits per cell than the first cell level. (See Fig 2B, paragraph [0036], illustrates SLC program which is single bit cell level is two fewer bit cell level than TLC erase which is triple bit cell level)
Regarding claim 13, IONIN teaches The system of claim 9, wherein the first cell level is associated with a single-level cell (SLC); and wherein the second cell level is associated with a triple-level cell (TLC). (See Fig 2C, paragraph [0037], illustrates SLC erase which is single bit cell level is two fewer bit cell level than TLC program which is triple bit cell level)
Regarding claim 16, IONIN teaches The system of claim 9, wherein to the controller is to perform a read operation on the block, the read operation comprising: sensing of voltage values of cells of the block having data written thereon; and (See Fig 1 and 2A, paragraph [0033] and [0034], illustrates controller 108 may manage the reading of data from and/or the writing of data to the NVM 110 which includes sensing the voltage of a cell and the voltage for a certain cell state)
application of a first read voltage threshold associated with the first cell level, a second read voltage threshold associated with the second cell level, or a third read voltage threshold that is between the first read voltage threshold and the second read voltage threshold. (See Fig 8, paragraph [0059], illustrates controller 108 determines if the blocks passes the SLC pre-erase threshold at block 808 and block 812 If the blocks passes the TLC pre-erase threshold. In other words, controller determines first and second level read voltage threshold)
Regarding claim 17, IONIN teaches The system of claim 9, wherein a first portion of the block having data written thereon is electrically coupled to a second portion of the block that is unprogrammed via bit lines. (See Fig 3, paragraph [0070], illustrates data can be internally migrated from the first portion of the non-volatile memory to a second portion of the non-volatile memory. In other words first portion is electrically coupled to second portion of NVM memory)
Regarding claim 18, IONIN teaches A computer program product comprising: one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions comprising: (See Fig 1, paragraph [0032], illustrates controller 108 may use volatile memory 112 as a cache to store information or instructions for programming to NVM 110)
program instructions to perform an erase operation, having a first cell level, on a block associated with write operations having a second cell level that is less than the first cell level; program instructions to perform a write operation having the second cell level; and (See Fig 2B, paragraph [0036], illustrates a voltage distribution curve with TLC erase and SLC programming. In other words, a block of NVM (Fig 2) is erased in TLC mode which is triple bit cell level and programmed in SLC which is single bit cell level)
program instructions to perform a read operation on the block using a threshold voltage that is associated with the first cell level, the second cell level, or a voltage that is between an erase voltage of the first cell level and an erase voltage of the second cell level. (See Fig 8, paragraph [0059], illustrates controller 108 determines if the blocks passes the SLC pre-erase threshold at block 808 and block 812 If the blocks passes the TLC pre-erase threshold. In other words, controller determines first and second level read voltage threshold)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable
over IONIN in view of LEE et al. (US 20250123751 A1) hereinafter LEE.
Regarding claim 3, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 2. However, IONIN does not explicitly teach The method of claim 2, wherein the second cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the first cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell
On the other hand, LEE which also relates to non volatile memory cell level erase
and program in power loss event teaches The method of claim 2, wherein the second cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the first cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell. (See Fig 1, paragraph [0043], illustrates NVM 110 may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with LEE by memory cell level erase and program in power loss event, as taught by LEE, to enable NVM 110 which may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell. The combined system of IONIN – LEE allows controller to employ mechanism in various SSD architectures, such as an SSD architecture that uses fixed block counts for each block type pool (e.g., SLC block pools, MLC block pools, etc.) as mentioned in paragraph [0038]. Therefore, the combination of IONIN - LEE improves the performance memory systems. See LEE, paragraph [0061].
Regarding claim 11, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 10. However, IONIN does not explicitly teach The system of claim 10, wherein the first cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the second cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell
On the other hand, LEE which also relates to non volatile memory cell level erase
and program in power loss event teaches The system of claim 10, wherein the first cell level is associated with a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC); and wherein the second cell level is associated with an MLC, a TLC, a QLC, or a penta-level cell. (See Fig 1, paragraph [0043], illustrates NVM 110 may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see LEE, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with LEE by memory cell level erase and program in power loss event, as taught by LEE, to enable NVM 110 which may include NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, penta-level cell (PLC) memory, N-level cell (XLC) memory, or any combination thereof), or NOR memory for first and second level cell. The combined system of IONIN – LEE allows controller to employ mechanism in various SSD architectures, such as an SSD architecture that uses fixed block counts for each block type pool (e.g., SLC block pools, MLC block pools, etc.) as mentioned in paragraph [0038]. Therefore, the combination of IONIN - LEE improves the performance memory systems. See LEE, paragraph [0061].
Claim(s) 6-7, 14-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over IONIN in view of Zhou et al. (US 20230385191 A1) hereinafter Zhou.
Regarding claim 6, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 1. However, IONIN does not explicitly teach The method of claim 1, wherein the block write operation is associated with one or more of: a power loss event, writing data from a volatile medium of the storage device to a non-volatile medium of the storage device, or a partial block write operation
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The method of claim 1, wherein the block write operation is associated with one or more of: a power loss event, writing data from a volatile medium of the storage device to a non-volatile medium of the storage device, or a partial block write operation. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Zhou, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 7, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 1. However, IONIN does not explicitly teach The method of claim 1, wherein a first portion of the block having data written thereon is electrically coupled to a second portion of the block that is unprogrammed via bit lines
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The method of claim 1, wherein a first portion of the block having data written thereon is electrically coupled to a second portion of the block that is unprogrammed via bit lines. (See Fig 3, paragraph [0070], illustrates data can be internally migrated from the first portion of the non-volatile memory to a second portion of the non-volatile memory. In other words first portion is electrically coupled to second portion of NVM memory)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Zhou, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable data can be internally migrated from the first portion of the non-volatile memory to a second portion of the non-volatile memory or in other words first portion is electrically coupled to second portion of NVM memory. The combined system of IONIN – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 14, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 9. However, IONIN does not explicitly teach The system of claim 9, wherein the write operation is associated with a power loss event
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The system of claim 9, wherein the write operation is associated with a power loss event. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Zhou, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 15, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 9. However, IONIN does not explicitly teach The system of claim 9, wherein the write operation is associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The system of claim 9, wherein the write operation is associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Zhou, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 19, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 18. However, IONIN does not explicitly teach The computer program product of claim 18, wherein the write operation is associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The computer program product of claim 18, wherein the write operation is associated with writing data from a volatile medium of the storage device to a non-volatile medium of the storage device. (See Fig 3, paragraph [0070], illustrates at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Zhou, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable at step 333 power failure event, responsive to detection of power failure data can be written from volatile memory to first portion of multi-level NVM memory at step 336. The combined system of IONIN – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN - Zhou improves write-back policy. See Zhou, paragraph [0014].
Regarding claim 20, IONIN teaches non volatile memory cell level erase and program in power loss event of claim 18. However, IONIN does not explicitly teach The computer program product of claim 18, wherein the write operation comprises a partial block write operation
On the other hand, Zhou which also relates to non volatile memory cell level erase and program in power loss event teaches The computer program product of claim 18, wherein the write operation comprises a partial block write operation. (See Fig 1, paragraph [0024], illustrates data can be written to first portion of non volatile memory 135. In other words, data be written partially)
Both IONIN and LEE relate to non volatile memory cell level erase and program in power loss event (see IONIN, abstract, and see Zhou, abstract, regarding cell level erase and program for non volatile memory).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine IONIN with Zhou by memory cell level erase and program in power loss event, as taught by Zhou, to enable data to be written to first portion of non volatile memory 135. In other words, data be written partially. The combined system of IONIN – Zhou allows each of the non-volatile memory blocks to be utilized to efficiently store large amounts of data and/or operate in accordance with a write-back policy in the absence of a backup power supply failure event as mentioned in paragraph [0025]. Therefore, the combination of IONIN - Zhou improves write-back policy. See Zhou, paragraph [0014].
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure.
a. Yang et al. (US 20170062069 A1) teaches A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.
b. NAGASHIMA et al. (US 20180268910 A1) teaches a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132