DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/07/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Olney U.S. Patent No. 5,602,409 (hereinafter “Olney”).
Regarding claim 19, Olney teaches an electrostatic discharge protection circuit (refer to fig.6 and abstract) coupled between a first voltage terminal (i.e. terminal BP1)(fig.6) and a second voltage terminal (i.e. terminal BP2)(fig.6), wherein the electrostatic discharge protection circuit comprises: a first bipolar junction transistor (i.e. transistor Q1)(fig.6) having a first terminal (refer to collector of Q1)(fig.6), a second terminal (refer to emitter of Q1)(fig.6), and a control terminal (refer to base of Q1)(fig.6), wherein the first terminal of the first bipolar junction transistor is coupled to the first voltage terminal (implicit)(refer to fig.6); and a second bipolar junction transistor (i.e. transistor Q2)(fig.6) having a first terminal (refer to collector of Q2)(fig.6), a second terminal (refer to emitter of Q2)(fig.6), and a control terminal (refer to base of Q2)(fig.6), wherein the second terminal of the second bipolar junction transistor is coupled to the second terminal of the first bipolar junction transistor (implicit)(refer to fig.6), the first terminal of the second bipolar junction transistor is coupled to the second voltage terminal (implicit)(refer to fig.6), and the control terminal of the first bipolar junction transistor is coupled to the control terminal of the second bipolar junction transistor (implicit)(refer to fig.6), wherein a first doping concentration of a semiconductor material forming the first terminal of the first bipolar junction transistor (refer to epitaxial tub 4)(fig.5) is lower than a second doping concentration of a semiconductor material forming the second terminal of the first bipolar junction transistor (refer to heavily doped n-type region 16)(fig.5)(doping of epitaxial tub 4 is lower than the heavily doped n-type region 16), and a third doping concentration of a semiconductor material forming the first terminal of the second bipolar junction transistor (refer to epitaxial tub 6)(fig.5) is lower than a fourth doping concentration of the semiconductor material forming the second terminal of the second bipolar junction transistor (refer to heavily doped n-type region 22)(fig.5)(doping of epitaxial tub 6 is lower than the heavily doped n-type region 22).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-15, 17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Olney.
Regarding claim 1, Olney teaches an electrostatic discharge protection circuit (refer to fig.6 and abstract) coupled between a first voltage terminal (i.e. terminal BP1)(fig.6) and a second voltage terminal (i.e. terminal BP2)(fig.6), wherein the electrostatic discharge protection circuit comprises: a first bipolar junction transistor (i.e. transistor Q1)(fig.6) having a first terminal (refer to collector of Q1)(fig.6), a second terminal (refer to emitter of Q1)(fig.6), and a control terminal (refer to base of Q1)(fig.6), wherein the first terminal of the first bipolar junction transistor is coupled to the first voltage terminal (implicit)(refer to fig.6); and a second bipolar junction transistor (i.e. transistor Q2)(fig.6) having a first terminal (refer to collector of Q2)(fig.6), a second terminal (refer to emitter of Q2)(fig.6), and a control terminal (refer to base of Q2)(fig.6), wherein the second terminal of the second bipolar junction transistor is coupled to the second terminal of the first bipolar junction transistor (implicit)(refer to fig.6), the first terminal of the second bipolar junction transistor is coupled to the second voltage terminal (implicit)(refer to fig.6), and the control terminal of the first bipolar junction transistor is coupled to the control terminal of the second bipolar junction transistor (implicit)(refer to fig.6); wherein a first breakdown voltage of a first junction between the first terminal and the control terminal of the first bipolar junction transistor is greater than a second breakdown voltage of a second junction between the second terminal and the control terminal of the first bipolar junction transistor, and a third breakdown voltage of a third junction between the first terminal and the control terminal of the second bipolar junction transistor is greater than a fourth breakdown voltage of a fourth junction between the second terminal and the control terminal of the second bipolar junction transistor. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein a first breakdown voltage of a first junction between the first terminal and the control terminal of the first bipolar junction transistor is greater than a second breakdown voltage of a second junction between the second terminal and the control terminal of the first bipolar junction transistor, and a third breakdown voltage of a third junction between the first terminal and the control terminal of the second bipolar junction transistor is greater than a fourth breakdown voltage of a fourth junction between the second terminal and the control terminal of the second bipolar junction transistor., since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection circuit of Olney to include wherein a first breakdown voltage of a first junction between the first terminal and the control terminal of the first bipolar junction transistor is greater than a second breakdown voltage of a second junction between the second terminal and the control terminal of the first bipolar junction transistor, and a third breakdown voltage of a third junction between the first terminal and the control terminal of the second bipolar junction transistor is greater than a fourth breakdown voltage of a fourth junction between the second terminal and the control terminal of the second bipolar junction transistor to provide the advantage of using bipolar transistors with typical breakdown characteristics.
Regarding claim 2, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1, wherein the first terminal of the first bipolar junction transistor is formed of a first type semiconductor material (refer to epitaxial tub 4)(fig.5), and the control terminal of the first bipolar junction transistor is formed of a second type semiconductor material (refer to p-type well 14)(fig.5), the first terminal of the second bipolar junction transistor is formed of a third type semiconductor material (refer to epitaxial tub 6)(fig.5), and the control terminal of the second bipolar junction transistor is formed of a fourth type semiconductor material (refer to p-type well 20)(fig.5), the second terminal of the first bipolar junction transistor and the second terminal of the second bipolar junction transistor are both formed of a fifth-type semiconductor material (refer to highly doped n-type regions 16 and 22)(fig.5), wherein the first type semiconductor material, the third type semiconductor material, and the fifth type semiconductor material have same conductive type (implicit)(refer to fig.5)(the first, third, and fifth materials are n-type), the fifth type semiconductor material is different from the first type semiconductor material or the third type semiconductor material (implicit)(refer to fig.5)(the fifth material is heavily doped, the first and third materials are not heavily doped and are epitaxial tubs), and the second type semiconductor material and the fourth type semiconductor material have same conductive type (implicit)(refer to fig.5)(the second and fourth materials are p-type).
Regarding claim 3, Olney teaches the electrostatic discharge protection circuit as claimed in claim 2, wherein the first type semiconductor material and the third type semiconductor material are each low-doped N-type semiconductor materials (implicit)(refer to fig.5)(both the first and third materials are epitaxial tubs and epitaxial tubs are low doped n-type regions), the second type semiconductor material and the fourth type semiconductor material are each P-type semiconductor materials (implicit)(refer to fig.5)(both the second and fourth materials are p-type wells), and the fifth type semiconductor material is a highly-doped N-type semiconductor material (implicit)(refer to fig.5)(16 and 22 are heavily doped n-type regions).
Regarding claim 4, Olney teaches the electrostatic discharge protection circuit as claimed in claim 2, wherein the first type semiconductor material and the third type semiconductor material are each low-doped P-type semiconductor materials (refer to epitaxial tubs 4 and 6)(fig.5)(refer also to claim 7 and col. 3 lines 60-63)(swapping the NPN transistors Q1 and Q2 for PNP transistors as suggested in claim 7 and col. 3 lines 60-63 would reverse all of the conductivity types), the second type semiconductor material and the fourth type semiconductor material are each N-type semiconductor materials (refer to p-type wells 14 and 20)(fig.5)(refer also to claim 7 and col. 3 lines 60-63), and the fifth type semiconductor material is a highly-doped P-type semiconductor material (refer to heavily doped n-type regions 16 and 22)(fig.5)(refer also to claim 7 and col. 3 lines 60-63).
Regarding claim 5, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1, wherein the first terminal of the first bipolar junction transistor is formed of a first type semiconductor material (refer to epitaxial tub 4)(fig.5), and the control terminal of the first bipolar junction transistor is formed of a second type semiconductor material (refer to p-type well 14)(fig.5), the first terminal of the second bipolar junction transistor is formed of a third type semiconductor material (refer to epitaxial tub 6)(fig.5), and the control terminal of the second bipolar junction transistor is formed of a fourth type semiconductor material (refer to p-type well 20)(fig.5), the second terminal of the first bipolar junction transistor is formed of a fifth-type semiconductor material (refer to highly doped n-type region 16)(fig.5), and the second terminal of the second bipolar junction transistor is formed of a sixth-type semiconductor material (refer to highly doped n-type region 22)(fig.5), wherein the first type semiconductor material, the fourth type semiconductor material, and the fifth type semiconductor material have same conductive type (implicit)(refer to fig.5, claim 6, and col. 3 lines 60-63)(switching transistor Q1 or Q2 to a PNP transistor instead of an NPN transistor as suggested in claim 6 and col. 3 lines 60-63 would reverse the conductivity types of the semiconductor materials of one of the transistors Q1 or Q2; therefore, the first, fourth, and fifth type semiconductor materials would be the same conductivity types), and the second type semiconductor material, the third type semiconductor material, and the sixth type semiconductor material have same conductive type (implicit)(refer to fig.5, claim 6, and col. 3 lines 60-63)(switching transistor Q1 or Q2 to a PNP transistor instead of an NPN transistor as suggested in claim 6 and col. 3 lines 60-63 would reverse the conductivity types of the one of the transistors Q1 or Q2; therefore, the second, third, and sixth type semiconductor materials would be the same conductivity types).
Regarding claim 6, Olney teaches the electrostatic discharge protection circuit as claimed in claim 5, wherein the first type semiconductor material is a low-doped P-type semiconductor material (refer to epitaxial tub 4)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the second type semiconductor material is an N-type semiconductor material (refer to p-type well 14)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the third type semiconductor material is a low-doped N-type semiconductor material (refer to epitaxial tub 6)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the fourth type semiconductor material is a P-type semiconductor material (refer to p-type well 20)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the fifth-type semiconductor material is a highly-doped P-type semiconductor material (refer to heavily doped n-type region 16)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), and the sixth-type semiconductor material is a highly-doped N-type semiconductor material (refer to heavily doped n-type region 22)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63); alternatively, the first type semiconductor material is a low-doped N-type semiconductor material (refer to epitaxial tub 4)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the second type semiconductor material is a P-type semiconductor material (refer to p-type well 14)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the third type semiconductor material is a low-doped P-type semiconductor material (refer to epitaxial tub 6)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the fourth type semiconductor material is an N-type semiconductor material (refer to p-type well 20)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), the fifth-type semiconductor material is a highly-doped N-type semiconductor material (refer to heavily doped n-type region 16)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63), and the sixth-type semiconductor material is a highly-doped P-type semiconductor material (refer to heavily doped n-type region 22)(fig.5)(refer also to claims 6 and 7 and col. 3 lines 60-63).
Regarding claim 7, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1; however, Olney does not teach wherein the first breakdown voltage is equal to the third breakdown voltage, and the second breakdown voltage is equal to the fourth breakdown voltage. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the first breakdown voltage is equal to the third breakdown voltage, and the second breakdown voltage is equal to the fourth breakdown voltage, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection circuit of Olney to include wherein the first breakdown voltage is equal to the third breakdown voltage, and the second breakdown voltage is equal to the fourth breakdown voltage to provide the advantage of using identical transistors, thereby simplifying construction/manufacturing of the circuit and balancing the electrostatic discharge over both of the transistors.
Regarding claim 8, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1, wherein the first terminal of the first bipolar junction transistor is a first collector (implicit)(refer to collector of transistor Q1)(fig.6), the second terminal of the first bipolar junction transistor is a first emitter (implicit)(refer to emitter of transistor Q1)(fig.6), the first terminal of the second bipolar junction transistor is a second collector (implicit)(refer to collector of transistor Q2)(fig.6), the second terminal of the second bipolar junction transistor is a second emitter (implicit)(refer to emitter of transistor Q2)(fig.6), and the first emitter is coupled to the second emitter (implicit)(refer to fig.6).
Regarding claim 9, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1; however, Olney does not teach wherein the second terminal of the first bipolar junction transistor is coupled to the second terminal of the second bipolar junction transistor through one or more intermediate transistors. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the second terminal of the first bipolar junction transistor is coupled to the second terminal of the second bipolar junction transistor through one or more intermediate transistors, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge circuit of Olney to include wherein the second terminal of the first bipolar junction transistor is coupled to the second terminal of the second bipolar junction transistor through one or more intermediate transistors to provide the advantage of adjusting the total breakdown voltage of the electrostatic discharge circuit to an appropriate level for the protected circuit.
Regarding claim 10, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1, further comprising a first impedance circuit (i.e. resistance RB1)(fig.6) and a second impedance circuit (i.e. resistance RB2)(fig.6), wherein the first impedance circuit is coupled between the control terminal and the second terminal of the first bipolar junction transistor (implicit)(refer to fig.6), the second impedance circuit is coupled between the control terminal and the second terminal of the second bipolar junction transistor (implicit)(refer to fig.6), and the second terminal of the first bipolar junction transistor is coupled to the second terminal of the second bipolar junction transistor (implicit)(refer to fig.6).
Regarding claim 11, Olney teaches the electrostatic discharge protection circuit as claimed in claim 10, wherein the first impedance circuit comprises one or a combination of a first resistor, a first capacitor, a first inductor, a first diode, at least one first field-effect transistor, and at least one first field-effect transistor (implicit)(refer to resistance RB1)(fig.6), and the second impedance circuit comprises one or a combination of a second resistor, a second capacitor, a second inductor, a second diode, at least one second field-effect transistor, and at least one second field-effect transistor (implicit)(refer to resistance RB2)(fig.6).
Regarding claim 12, Olney teaches the electrostatic discharge protection circuit as claimed in claim 10, wherein a sum of an impedance value of the first impedance circuit and an impedance value of the second impedance circuit is a comprehensive impedance value (implicit), in response to a voltage value of the first voltage terminal being greater than a voltage value of the second voltage terminal and an electrostatic discharge event occurring, a product of the comprehensive impedance value and a first breakdown current of the first junction of the first bipolar junction transistor is greater than or equal to a first conduction voltage of the second junction of the first bipolar junction transistor (inherent)(refer to col. 7 line 25 to col. 8 line 14), and in response to a voltage value of the second voltage terminal being greater than a voltage value of the first voltage terminal and the electrostatic discharge event occurring, a product of the comprehensive impedance value and a third breakdown current of the third junction of the second bipolar junction transistor is greater than or equal to a second conduction voltage of the fourth junction of the second bipolar junction transistor (inherent)(refer to col. 7 line 25 to col. 8 line 14).
Regarding claim 13, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1, further comprising a first impedance circuit (i.e. resistances RB1 and RB2)(fig.6), wherein the first impedance circuit is coupled between the control terminal of the first bipolar junction transistor and the control terminal of the second bipolar junction transistor (implicit)(refer to fig.6).
Regarding claim 14, Olney teaches the electrostatic discharge protection circuit as claimed in claim 13, wherein the first impedance circuit comprises one or a combination of a resistor, a capacitor, an inductor, a diode, a field-effect transistor, and a field-effect transistor (refer to resistances RB1 and RB2)(fig.6).
Regarding claim 15, Olney teaches the electrostatic discharge protection circuit as claimed in claim 13, wherein in response to a voltage value of the first voltage terminal being greater than a voltage value of the second voltage terminal and an electrostatic discharge event occurring, a product of the impedance value of the first impedance circuit and a first breakdown current of the first junction of the first bipolar junction transistor is greater than or equal to a first conduction voltage of the second junction of the first bipolar junction transistor (inherent)(refer to col. 7 line 25 to col. 8 line 14), and in response to a voltage value of the second voltage terminal being greater than a voltage value of the first voltage terminal and the electrostatic discharge event occurring, a product of the impedance value of the first impedance circuit and a third breakdown current of the third junction of the second bipolar junction transistor is greater than or equal to a second conduction voltage of the fourth junction of the second bipolar junction transistor (inherent)(refer to col. 7 line 25 to col. 8 line 14).
Regarding claim 17, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1, wherein the first voltage terminal is a voltage input terminal (implicit)(refer to terminal BP1)(fig.6), and the second voltage terminal is a reference voltage terminal (implicit)(refer to terminal BP2)(fig.6).
Regarding claim 20, Olney teaches the electrostatic discharge protection circuit as claimed in claim 19; however, Olney does not teach wherein the first doping concentration is equal to the third doping concentration, and the second doping concentration is equal to the fourth doping concentration. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the first doping concentration is equal to the third doping concentration, and the second doping concentration is equal to the fourth doping concentration, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection circuit of Olney to include wherein the first doping concentration is equal to the third doping concentration, and the second doping concentration is equal to the fourth doping concentration to provide the advantage of using identical transistors, thereby simplifying construction/manufacturing of the circuit and balancing the electrostatic discharge over both of the transistors.
Claim(s) 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Olney as applied to claim 1 above, and further in view of Chao U.S. Patent Application 2016/0285262 (hereinafter “Chao”).
Regarding claim 16, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1; however, Olney does not teach wherein the first bipolar junction transistor and the second bipolar junction transistor are both heterojunction bipolar transistors. However, Chao teaches wherein the first bipolar junction transistor and the second bipolar junction transistor are both heterojunction bipolar transistors (refer to [0032] and figures 5 and 7). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection circuit of Olney to replace the bipolar transistors with the heterojunction bipolar transistors of Chao to provide the advantage of using transistors with higher operating speeds and higher power efficiency.
Regarding claim 18, Olney teaches the electrostatic discharge protection circuit as claimed in claim 1; however, Olney does not teach wherein the electrostatic discharge protection circuit is used in a high-power radio frequency signal processing circuit. However, Chao teaches wherein the electrostatic discharge protection circuit is used in a high-power radio frequency signal processing circuit (refer to [0005]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection circuit of Olney to use it in a high-power radio frequency signal processing circuit such as in Chao to provide the advantage of protecting circuits which are susceptible to ESD from damage.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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