Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 & 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al., US20010026429 (hereinafter referred to as Fukuda), in view of Muto et al., US20140367739 (hereinafter referred to as Muto).
In regards to claim 1, Fukuda teaches a circuit (overcurrent limiting circuit; [Abstract]) comprising: a first transistor (IGBT 4, main transistor; [Fig. 1]) having a first terminal (4b; [Fig. 1]), a second terminal (4c; [Fig. 1]), and a control terminal (4a; [Fig. 1]); a second transistor (IGBT 4, sense transistor; [Fig. 1]) having a first terminal (4b; [Fig. 1]) coupled to the first terminal of the first transistor (implicit of both being tied to node 4b; [Fig. 1]), a second terminal (4d; [Fig. 1]), and a control terminal (4a; [Fig. 1]) coupled to the control terminal of the first transistor (implicit of both being tied to node 4a; [Fig. 1]); a third transistor (sink driver 3b; [Fig. 1]) having a first terminal (node coupled to resistor 5; [Fig. 1]) coupled to the control terminal of the first transistor (implicit, the first terminal is coupled through resistor 5 to the control terminal; [Fig. 1]), a second terminal (node coupled to ground; [Fig. 1]) coupled to the second terminal of the first transistor (implicit, both are coupled to ground; [Fig. 1]), and a control terminal (base of transistor; [Fig. 1]); and a current limit circuit (overcurrent protection circuit 20a; [Fig. 1]) having an input (4d; [Fig. 1]) coupled to the second terminal of the second transistor (implicit, both are coupled to 4d; [Fig. 1]), and an output (output of latch to input of logic circuit 2; [Fig. 1]) coupled to the control terminal of the third transistor (implicit, the output is coupled to the control terminal through logic circuit 2; [Fig. 1]).
Fukuda does not teach the first transistor and the second transistor as two separate transistors.
Muto teaches the first transistor (Q1; [Fig. 6]) (IGBT 4, main transistor, Fukuda) and the second transistor (Q2; [Fig. 6]) (IGBT 4, sense transistor, Fukuda) as two separate transistors.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda in order to incorporate the first transistor and the second transistor as two separate transistors as taught by Fukuda. An IGBT with a separate terminal is understood by one of ordinary skill in the art as two separate transistors as taught by Muto. The motivation for doing so would be to improve the sensing of the power MOSFET/IGBT.
In regards to claim 3, Fukuda teaches the circuit of claim 1, further comprising a resistor (sense resistor 12; [Fig. 1]) having a first terminal (upper node of 12; [Fig. 1]) coupled to the second terminal of the second transistor (implicit, first terminal is coupled through sense resistor 11; [Fig. 1]), and a second terminal (lower node of 12; [Fig. 1]) coupled to the second terminal of the first transistor (implicit, both are coupled to ground; [Fig. 1]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al., US20010026429 (hereinafter referred to as Fukuda), in view of Muto et al., US20140367739 (hereinafter referred to as Muto) and in further view of Chokhawala, US5559656 (hereinafter referred to as Chokhawala).
In regards to claim 2, Fukuda and Muto do not teach the circuit of claim 1, further comprising a diode and a resistor coupled in series between the first terminal of the first transistor and the control terminal of the first transistor.
Chokhawala teaches the circuit of claim 1, further comprising a diode (diode 22; [Fig. 5]) and a resistor (resistor 16, R1; [Fig. 5]) coupled in series (implicit; [Fig. 5]) between the first terminal of the first transistor and the control terminal of the first transistor (implicit, the series diode and resistor are between the collector and gate of the IGBT; [Fig. 5]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda and Muto in order to incorporate the circuit of claim 1, further comprising a diode and a resistor coupled in series between the first terminal of the first transistor and the control terminal of the first transistor as taught by Chokhawala. The motivation for doing so is to protect the IGBT from a fault while in a conduction state.
Claim(s) 4-5, 8-10, 12, 15- is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al., US20010026429 (hereinafter referred to as Fukuda), in view of Muto et al., US20140367739 (hereinafter referred to as Muto) and in further view of Yoshida et al., US20190372567 (hereinafter referred to as Yoshida).
In regards to claim 4, Fukuda and Muto do not teach wherein the current limit circuit includes: a filter circuit including: a capacitor having a first terminal coupled to the second terminal of the second transistor, and a second terminal; and a resistor having a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the first transistor.
Yoshida teaches wherein the current limit circuit includes: a filter circuit (low pass filter 102; [Fig. 12]) including: a capacitor (capacitor 26; [Fig. 12]) having a first terminal (bottom node of 26; [Fig. 12]) coupled to the second terminal of the second transistor (implicit, the terminal is coupled to ground/return; [Fig. 12]), and a second terminal (top node of 26; [Fig. 12]); and a resistor (resistor 24; [Fig. 12]) having a first terminal (left node of 24; [Fig. 12]) coupled to the second terminal of the capacitor (implicit; [Fig. 12]), and a second terminal (right node of 24; [Fig. 12]) coupled to the second terminal of the first transistor (implicit; [Fig. 12]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda and Muto in order to incorporate wherein the current limit circuit includes: a filter circuit including: a capacitor having a first terminal coupled to the second terminal of the second transistor, and a second terminal; and a resistor having a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the first transistor as taught by Yoshida. The motivation for doing so is to remove any high frequency noise originating from the IGBT.
In regards to claim 5, Fukuda teaches wherein the current limit circuit includes: an amplifier (first comparator 21; [Fig. 1]) having a first input coupled to the second terminal of the capacitor (implicit; [Fig. 1]) (implicit, Yoshida, [Fig. 12]), a second input (- terminal of 21; [Fig. 1]), and an output (output of 21; [Fig. 1]) coupled to the control terminal of the third transistor (implicit, the output is coupled through the delay 22, latch 23, and the input logic circuit 2; [Fig. 1]); and a voltage source (voltage V1; [Fig. 1]) having an output coupled to the second input of the amplifier (implicit; [Fig. 1]).
In regards to claim 8, Fukuda teaches a circuit (overcurrent limiting circuit; [Abstract]) comprising: a first transistor (IGBT 4, main transistor; [Fig. 1]) having a first terminal (4b; [Fig. 1]), a second terminal (4c; [Fig. 1]), and a control terminal (4a; [Fig. 1]); a current sensor (IGBT 4, sense transistor; [Fig. 1]) coupled to the first terminal or the second terminal of the first transistor (implicit, directly tied to the first terminal and coupled to the second terminal; [Fig. 1]); an amplifier (first comparator 21; [Fig. 1]) a second input (- terminal of 21; [Fig. 1]) coupled to a slope input terminal (for first decreasing the main current at a first slope, voltage V1; [0017]), and an output (output of 21; [Fig. 1]); and a second transistor (sink driver 3b; [Fig. 1]) having a first terminal (node coupled to resistor 5; [Fig. 1]) coupled to the control terminal of the first transistor (implicit, the first terminal is coupled through resistor 5 to the control terminal; [Fig. 1]), a second terminal (node coupled to ground; [Fig. 1]) coupled to the second terminal of the first transistor (implicit, both are coupled to ground; [Fig. 1]), and a control terminal (base of transistor; [Fig. 1]) coupled to the output of the amplifier (implicit, the output is coupled to the control terminal through logic circuit 2; [Fig. 1]).
Fukuda does not teach a filter circuit having a first terminal coupled to current sensor, and a second terminal coupled to the second terminal of the first transistor, and a third terminal; the amplifier having a first input coupled to the third terminal of the filter circuit; and the first transistor and the current sensor as being two separate components.
Muto teaches the first transistor (Q1; [Fig. 6]) (IGBT 4, main transistor, Fukuda) and the current sensor (Q2; [Fig. 6]) (IGBT 4, sense transistor, Fukuda) as being two separate components.
Muto does not teach a filter circuit having a first terminal coupled to current sensor, and a second terminal coupled to the second terminal of the first transistor, and a third terminal; the amplifier having a first input coupled to the third terminal of the filter circuit.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda in order to incorporate the first transistor and the current sensor as being two separate components as taught by Muto. An IGBT with a separate terminal is understood by one of ordinary skill in the art as two separate transistors as taught by Muto. The motivation for doing so would be to improve the sensing of the power MOSFET.
Yoshida teaches a filter circuit (low pass filter 102; [Fig. 12]) having a first terminal (right node of 102; [Fig. 12]) coupled to current sensor (implicit, coupled to the second terminal of the current sensor; [Fig. 12]), and a second terminal (bottom node of 26; [Fig. 12]) coupled to the second terminal of the first transistor (implicit, coupled through ground/return; [Fig. 12]), and a third terminal (left node of 102; [Fig. 12]); the amplifier having a first input (+terminal; [Fig. 12]) (first comparator 21, Fukuda) coupled to the third terminal of the filter circuit (implicit; [Fig. 12]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda and Muto in order to incorporate a filter circuit having a first terminal coupled to current sensor, and a second terminal coupled to the second terminal of the first transistor, and a third terminal; the amplifier having a first input coupled to the third terminal of the filter circuit as taught by Yoshida. The motivation for doing so is to remove any high frequency noise originating from the IGBT.
In regards to claim 9, Fukuda teaches wherein the current sensor includes: a third transistor (IGBT 4, sense transistor; [Fig. 1]) having a first terminal (4b; [Fig. 1]) coupled to the first terminal of the first transistor (implicit; [Fig. 1]), a second terminal (4d; [Fig. 1]) coupled to the first terminal of the filter circuit (implicit; [Fig. 1]) (implicit, Yoshida; [Fig. 12]), and a control terminal (4a; [Fig. 1]) coupled to the control terminal of the first transistor (implicit; [Fig. 1]); and a resistor (sense resistor 12; [Fig. 1]) having a first terminal (upper node of 12; [Fig. 1]) coupled to the second terminal of the third transistor (implicit, coupled through sense resistor 11; [Fig. 1]), and a second terminal (lower node of 12; [Fig. 1]) coupled to the second terminal of the first transistor (implicit, both are tied directly to ground; [Fig. 1]).
In regards to claim 10, Fukuda and Muto do not teach wherein the filter circuit includes: a capacitor having a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the first input of the amplifier; and a resistor having a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the first transistor.
Yoshida teaches wherein the filter circuit includes: a capacitor (capacitor 26; [Fig. 12]) having a first terminal (bottom node of 26; [Fig. 12]) coupled to the second terminal of the third transistor (implicit, the terminal is coupled to ground/return; [Fig. 12]), and a second terminal (top node of 26; [Fig. 12]) coupled to the first input of the amplifier (implicit; [Fig. 12]); and a resistor (resistor 24; [Fig. 12]) having a first terminal (left node of 24; [Fig. 12]) coupled to the second terminal of the capacitor (implicit; [Fig. 12]), and a second terminal (right node of 24; [Fig. 12]) coupled to the second terminal of the first transistor (implicit; [Fig. 12]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda and Muto in order to incorporate wherein the filter circuit includes: a capacitor having a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the first input of the amplifier; and a resistor having a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the first transistor as taught by Yoshida. The motivation for doing so is to remove any high frequency noise originating from the IGBT.
In regards to claim 12, Fukuda teaches the circuit of claim 8, further comprising a voltage source (voltage V1; [Fig. 1]) coupled to the slope input terminal (implicit; [Fig. 1]).
In regards to claim 13, Fukuda does not teach the circuit of claim 12, further comprising a temperature sensor having an output coupled to the voltage source.
Muto teaches the circuit of claim 12, further comprising a temperature sensor (temperature detecting diode TD; [Fig. 6]) having an output coupled to the voltage source (Examiner’s Note: The temperature sensor and the voltage source would both be required to be coupled to a housekeeping voltage source.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda in order to incorporate the circuit of claim 12, further comprising a temperature sensor having an output coupled to the voltage source as taught by Muto. The motivation for doing so would be to provide overtemperature protection for the IGBT, the first transistor.
In regards to claim 15, Fukuda teaches a circuit (overcurrent limiting circuit; [Abstract]) comprising: a first transistor (IGBT 4, main transistor; [Fig. 1]) having a first terminal (4b; [Fig. 1]), a second terminal (4c; [Fig. 1]), and a control terminal (4a; [Fig. 1]); a current sensor (IGBT 4, sense transistor; [Fig. 1]) coupled to the first terminal or the second terminal of the first transistor (the first terminals are coupled together at 4b; [Fig. 1]); an amplifier (first comparator 21; [Fig. 1]) having a first input (+input; [Fig. 1]), a second input (-input; [Fig. 1]), and an output (output; [Fig. 1]); a slope threshold circuit (voltage V1; [Fig. 1]) having an input (housekeeping voltage), and an output (upper node of V1; [Fig. 1]) coupled to the second input of the amplifier (implicit; [Fig. 1]); and a second transistor (sink driver 3b; [Fig. 1]) having a first terminal (upper node of 3b; [Fig. 1]) coupled to the control terminal of the first transistor (implicit; [Fig. 1]), a second terminal (lower node of 3b; [Fig. 1]) coupled to the second terminal of the first transistor (implicit, coupled together through the ground/return; [Fig. 1]), and a control terminal (base of 3b; [Fig. 1]) coupled to the output of the amplifier (coupled to the output through the input logic circuit 2, latch 23, and delay 22; [Fig. 1]).
Fukuda does not teach the first transistor and the current sensor being separate components; a filter circuit having a first terminal coupled to the current sensor, and a second terminal coupled to the second terminal of the first transistor, and a third terminal; the amplifier having a first input coupled to the third terminal of the filter circuit; and a temperature sense circuit having an output coupled to the input of the slope threshold circuit.
Muto teaches the first transistor (Q1; [Fig. 6]) (IGBT 4, main transistor, Fukuda) and the current sensor (Q2; [Fig. 6]) (IGBT 4, sense transistor, Fukuda) as being separate components; and a temperature sense circuit (temperature detecting diode TD; [Fig. 6]) having an output coupled to the input of the slope threshold circuit (Examiner’s Note: The temperature sensor and the voltage source would both be required to be coupled to a housekeeping voltage source.).
Muto does not teach a filter circuit having a first terminal coupled to the current sensor, and a second terminal coupled to the second terminal of the first transistor, and a third terminal; the amplifier having a first input coupled to the third terminal of the filter circuit.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda in order to incorporate the first transistor and the current sensor as being separate components; and a temperature sense circuit having an output coupled to the input of the slope threshold circuit as taught by Muto. The motivation for doing so would be to improve the sensing of the power MOSFET/IGBT and to provide overtemperature protection for the power MOSFET/IGBT, the first transistor.
Yoshida teaches a filter circuit (low pass filter 102; [Fig. 12]) having a first terminal (right node of 102; [Fig. 12]) coupled to the current sensor (implicit, coupled to the second terminal of the current sensor; [Fig. 12]), and a second terminal (bottom node of 26; [Fig. 12]) coupled to the second terminal of the first transistor (implicit, coupled through ground/return; [Fig. 12]), and a third terminal (left node of 102; [Fig. 12]); the amplifier having a first input (+terminal; [Fig. 12]) (first comparator 21, Fukuda) coupled to the third terminal of the filter circuit (implicit; [Fig. 12]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda and Muto in order to incorporate a filter circuit having a first terminal coupled to the current sensor, and a second terminal coupled to the second terminal of the first transistor, and a third terminal; the amplifier having a first input coupled to the third terminal of the filter circuit as taught by Yoshida. The motivation for doing so is to remove any high frequency noise originating from the IGBT.
In regards to claim 16, Fukuda teaches wherein the current sensor includes: a third transistor (IGBT 4, sense transistor; [Fig. 1]) having a first terminal (4b; [Fig. 1]) coupled to the first terminal of the first transistor (implicit; [Fig. 1]), a second terminal (4d; [Fig. 1]) coupled to the first terminal of the filter circuit (implicit; [Fig. 1]) (implicit, Yoshida; [Fig. 12]), and a control terminal (4a; [Fig. 1]) coupled to the control terminal of the first transistor (implicit; [Fig. 1]); and a resistor (sense resistor 12; [Fig. 1]) having a first terminal (upper node of 12; [Fig. 1]) coupled to the second terminal of the third transistor (implicit, coupled through sense resistor 11; [Fig. 1]), and a second terminal (lower node of 12; [Fig. 1]) coupled to the second terminal of the first transistor (implicit, both are tied directly to ground; [Fig. 1]).
In regards to claim 17, Fukuda and Muto do not teach wherein the filter circuit includes: a capacitor having a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the first input of the amplifier; and a resistor having a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the first transistor.
Yoshida teaches wherein the filter circuit includes: a capacitor (capacitor 26; [Fig. 12]) having a first terminal (bottom node of 26; [Fig. 12]) coupled to the second terminal of the third transistor (implicit, the terminal is coupled to ground/return; [Fig. 12]), and a second terminal (top node of 26; [Fig. 12]) coupled to the first input of the amplifier (implicit; [Fig. 12]); and a resistor (resistor 24; [Fig. 12]) having a first terminal (left node of 24; [Fig. 12]) coupled to the second terminal of the capacitor (implicit; [Fig. 12]), and a second terminal (right node of 24; [Fig. 12]) coupled to the second terminal of the first transistor (implicit; [Fig. 12]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda and Muto in order to incorporate wherein the filter circuit includes: a capacitor having a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the first input of the amplifier; and a resistor having a first terminal coupled to the second terminal of the capacitor, and a second terminal coupled to the second terminal of the first transistor as taught by Yoshida. The motivation for doing so is to remove any high frequency noise originating from the IGBT.
Claim(s) 11 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuda et al., US20010026429 (hereinafter referred to as Fukuda), in view of Muto et al., US20140367739 (hereinafter referred to as Muto) in further view of Yoshida et al., US20190372567 (hereinafter referred to as Yoshida) and in further view of Chokhawala, US5559656 (hereinafter referred to as Chokhawala).
In regards to claim 11, Fukuda, Muto, and Yoshida do not teach the circuit of claim 8, further comprising a diode and a resistor coupled in series between the first terminal of the first transistor and the control terminal of the first transistor.
Chokhawala teaches the circuit of claim 8, further comprising a diode (diode 22; [Fig. 5]) and a resistor (resistor 16, R1; [Fig. 5]) coupled in series (implicit; [Fig. 5]) between the first terminal of the first transistor and the control terminal of the first transistor (implicit, the series diode and resistor are between the collector and gate of the IGBT; [Fig. 5]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda, Muto, and Yoshida in order to incorporate the circuit of claim 8, further comprising a diode and a resistor coupled in series between the first terminal of the first transistor and the control terminal of the first transistor as taught by Chokhawala. The motivation for doing so is to protect the IGBT from a fault while in a conduction state.
In regards to claim 18, Fukuda, Muto, and Yoshida do not teach the circuit of claim 15, further comprising a diode and a resistor coupled in series between the first terminal of the first transistor and the control terminal of the first transistor.
Chokhawala teaches the circuit of claim 15, further comprising a diode (diode 22; [Fig. 5]) and a resistor (resistor 16, R1; [Fig. 5]) coupled in series (implicit; [Fig. 5]) between the first terminal of the first transistor and the control terminal of the first transistor (implicit, the series diode and resistor are between the collector and gate of the IGBT; [Fig. 5]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fukuda, Muto, and Yoshida in order to incorporate the circuit of claim 15, further comprising a diode and a resistor coupled in series between the first terminal of the first transistor and the control terminal of the first transistor as taught by Chokhawala. The motivation for doing so is to protect the IGBT from a fault while in a conduction state.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 6 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claims 5, 4, and 1, especially “wherein:” “the circuit includes a temperature sensor having an output coupled to the input of the voltage source.”
Claim 7 would be allowed due to dependence on claim 6.
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 14 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claims 13, 12 and 8, especially “wherein: the temperature sensor is configured to sense a temperature of the first transistor and provide, at the output of the temperature sensor, a temperature sense signal representing the temperature of the first transistor; and the voltage source is configured to adjust a voltage provided by the voltage source based on the temperature sense signal.”
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 19 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 15, especially “the slope threshold circuit is configured to adjust a voltage provided at the output of the slope threshold circuit based on the temperature sense signal.”
Claim 20 would be allowed due to dependence on claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20210324826A1 is a close prior art for claim 13 and the objected, but allowed claims 6 and 19.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMANTHA L FAUBERT whose telephone number is (703)756-1311. The examiner can normally be reached Monday - Friday 8AM - 5PM.
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SAMANTHA LYNETTE FAUBERT
Examiner
Art Unit 2836
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
Prosecution Insights