DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1, 3, 6, 8, 10-11, 13, 14, 16, and 18-19 have been amended. Claims 1-23 are currently pending.
Response to Arguments
Applicant's arguments filed 06/30/2026 for claim 11 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments that Wang in view of Cheng does not teach detecting a target event on a communication bus, the target event including a compensation signal of newly amended claim 11, the Examiner respectfully disagrees.
Wang teaches a communication bus comprising a main controller and a plurality of chips (See Wang: Figure 6, Main controller and Chip 1 and Chip 2), wherein the main controller transmits a clock synchronization signal (Fig. 7, Clock synchronization signal; i.e. target event of claim 11) to each chip and each chip comprises a timer and chip controller that detects the clock synchronization signal (Paragraph 0090, main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip through the communication bus, and the timer may receive the clock synchronization signal and start timing from zero; or the clock synchronization signal may be transmitted to the chip controller of each chip; i.e. detecting a target event of claim 11). Since Wang does not teach that the clock synchronization signal (i.e. target event of claim 11) includes a compensation signal, the secondary reference Cheng has been remapped to teach these features. In particular, Cheng teaches a master device coupled to a plurality of slave devices (See Cheng: Figure 1, Slaves 121-122; i.e. at least one chip of claim 11), wherein the master device transmits multiple different clock signals to the slave device (Fig. 5, Master sends signals S504 and S507; i.e. S504 is the target event including a compensation signal of claim 11 and S507 is a corresponding compensation signal on the communication bus of claim 11) based on detecting that the chip fails to generate a successful response message (i.e. a target event corresponding to the chip of claim 11).
While Applicant argues that the different clock frequency signals of Cheng are not compensation signals, the claim language does not specify what qualifies as a compensation signal (i.e. is it a signal that adjusts the chip, a signal that changes a frequency of the chip, a signal from a master that has a differing value, etc.), thus under broadest reasonable interpretation a compensation signal can be any signal from a master device that the master device changes based on the slave or that changes the slave. Cheng teaches that the clock signals in S504 and S507 are adjusted (i.e. compensated) based on the response from the slave (See Cheng: Paragraph 0040, In step S504, the master device uses a clock signal with a clock frequency 200 KHz to perform an addressing check to the three slave devices, and to generate the corresponding checking result. In step S505, whether the checking result is successful or failed is determined… the first operating frequency is reduced to 100 KHz). Therefore, since the clock signals are adjusted by the master device, they can be broadly interpreted as compensation signals because the master is compensating for the slave unsuccessfully recognizing the clock signal by decreasing the frequency of the clock signal used.
Regarding Applicant’s arguments that Wang and Cheng are not analogous arts and would have no motivation to combine for newly amended claim 11, the Examiner respectfully disagrees.
Applicant argues that Wang is directed to signal conflict issues while Cheng is directed to rate matching issues, and thus there is no motivation to look at Cheng to solve rate mismatch problems that do not exist in Wang. However, Wang discloses that the main controller transmits a clock synchronization signal to chips (See Wang: Figure 7) and Cheng discloses a master that transmits clock frequency signals to slave devices (See Cheng: Figs. 1 and 5). As one can see, the main controller and chips of Wang are analogous to the master and slaves of Cheng, respectively, and the clock synchronization signal of Wang is analogous to the clock frequency signals of Cheng as they are both used to synchronize a clock to transmit data between master/slave (i.e. clock synchronization involves determining a clock rate that matches between a master and slave device). Cheng further discloses that the reason multiple clock frequencies are tested is because different slave devices will have different clock frequencies depending on the type of the devices (See Cheng: Paragraph 0003, Currently, some slave devices may allow the master to access data with a higher bit rate (i.e. a clock signal with a higher clock frequency), but some slave devices only allow the master device to access data with a lower bit rate (i.e. a clock signal with a lower clock frequency)) and that by testing different clock frequencies with the different slave devices, optimal clock frequencies can be determined and adjusted (i.e. compensated) for each slave device (See Cheng: Paragraph 0021, in order to increase the overall access speed and performance of the bus system, the master device is configured to use the clock signal of different clock frequencies to address the slave device and read/write data from/to the slave device in the present invention). Thus, by incorporating the secondary reference Cheng to the primary reference Wang, one can allow the main controller of Wang (i.e. same as the master of Cheng) to transmit clock synchronization signals at different rates to the chips of Wang (i.e. same as the slaves of Cheng) to determine optimal frequencies for each slave device, thus providing dynamic frequency matching which enables the master to interface with a wide-range of heterogeneous chip types without having to implement complex circuitry such as clock conversion circuits on the slave devices.
See Below for Detailed Rejection.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“a detection unit, configured to detect a target event” in claims 6, 21, and 23 with corresponding structure in Paragraphs [0128]-[0130].
“a determination unit, configured to determine” in claims 6, 21, and 23 with corresponding structure in Paragraph [0131].
“a signal generation unit, configured to generate a target event” in claims 6, 21, and 23 with corresponding structure in Paragraph [0132].
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2022/0100434) in view of Cheng (US 2023/0341887).
Regarding claim 11, Wang teaches a communication method (Fig. 6, Method performed on bus system between image forming apparatus and plurality of chips), comprising: detecting a target event on a communication bus (Fig. 6, Chips 1 and 2 detects clock synchronization signal; Paragraph 0090, main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip).
Wang does not teach the communication method comprising the target event including a compensation signal; determining whether there is at least one chip that fails to generate a target event corresponding to the chip on the communication bus as expected based on the detected target event; and in response to a determination that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected, generating a corresponding compensation signal on the communication bus.
Cheng teaches the communication method (Fig. 1, Method occurs between master device 1 and first slave device 121) comprising the target event including a compensation signal (Fig. 5, S504 is a target event with a compensation signal that uses a 200 KHz signal instead of a 400 KHz signal in step S501); determining whether there is at least one chip that fails to generate a target event corresponding to the chip on the communication bus as expected based on the detected target event (Fig. 5, Determine failure at step S505; Paragraph 0036, If the address checking unit 41 determines that the address checking unit 41 doesn't accept the response bit, the checking result is failed); and in response to a determination that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected, generating a corresponding compensation signal on the communication bus (Fig. 5, Generate corresponding compensating signal S507 in response to S505 failing; Paragraph 0036, the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device, and the address checking unit 41 will determine whether the master device accept a response bit transmitted by the slave device).
Wang and Cheng are analogous art because they are from the same field of endeavor of synchronizing clock frequencies on a communication bus between master and slave devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s method to incorporate the teachings of Cheng and enable the compensation signal to be sent from the master to slave in response to the master detecting that the clock frequency signal used was inadequate with the corresponding slave.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 12, Wang in view of Cheng teaches the method of claim 11. Wang teaches the method comprising wherein generate a target event corresponding to the chip on the communication bus as expected (Fig. 7, Chip 1 response generation), generating a corresponding compensation signal on the communication bus further comprises: when it is determined that there is a target event corresponding to the chip on the communication bus in a time window corresponding to the chip, generating a corresponding compensation signal on the communication bus (Fig. 7, Chip 1 response occurs in a time window with preset T1, T2, T3, and T4 times).
Cheng teaches the method comprising wherein, when it is determined that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected (Fig. 5, Step 502 fails where slave does not respond with correct response bit) and the method comprising generating a corresponding compensation signal on the communication bus further comprises: when it is determined that there is at least one chip that fails to generate a target event corresponding to the chip on the communication bus corresponding to the chip (Fig. 5, Generate compensating signal S504 in response to S502 failing; Paragraph 0036, the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device, and the address checking unit 41 will determine whether the master device accept a response bit transmitted by the slave device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s method to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 13, Wang in view of Cheng teaches the method of claim 12. Wang teaches wherein, before generating the corresponding compensation signal on the communication bus, the method further comprises: setting a time point at which at least part of signals included in a start signal generated by the host device is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point, or, setting a time point at which at least part of signals included in a compensation signal generated on the communication bus is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point, or, setting a time point at which at least part of signals included in a target event corresponding to the chip generated on the communication bus is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point (The ‘or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 7 where clock synchronization signal is a starting point of the time window with predefined times T1, T2, T3, and T4).
Regarding claim 14, Wang in view of Cheng teaches the method of claim 11. Wang teaches the method comprising wherein, when the target event corresponding to the first chip and the compensation signal are level signals respectively, a level width of the target event corresponding to the first chip is different from a level width of the compensation signal (Fig. 11, Level widths of the chip response signals occur after different t1 to t4 times which affects widths of signals).
Regarding claim 15, Wang in view of Cheng teaches the method of claim 11. Wang teaches wherein when the method is executed in a host device (Fig. 6, Image forming apparatus (i.e. a host device) contains installation detecting pin to determine successful connection; Paragraph 0071, output a low level to the installation detecting pin after the chip is powered on, such that a current loop may be formed between the chip and the image forming apparatus), the method further comprises: determining a connection state between the chip and the host device according to the target event corresponding to the chip and/or, determining a communication rate between the chip and the host device according to the connection status between the chip and the host device (The ‘and/or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 7, chip 1 response which indicates that the host and chip 1 are successfully connected and synchronized; Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)… a current loop may be formed between the chip 1 and the image forming apparatus).
Allowable Subject Matter
Claims 1-10 and 16-23 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, none of the cited references either alone or in combination teaches a communication method, comprising: detecting a target event on a communication bus, the communication bus being configured to be electrically connected to a first chip and at least one second chip, the target event including a compensation signal, the compensation signal being generated in response to that some or all of the at least one second chip fail to generate a target event corresponding to a second chip on the communication bus as expected; determining whether the detected target event meets expectations of the first chip based on the compensation signal; and in response to a determination that the detected target event meets the expectations of the first chip, generating a target event corresponding to the first chip on the communication bus.
Regarding claim 6, none of the cited references either alone or in combination teaches a control device, comprising: a detection unit, configured to detect a target event on a communication bus, the communication bus being electrically connected to a first chip and at least one second chip, the target event including a compensation signal, the compensation signal being generated in response to that some or all of the at least one second chip fail to generate a target event corresponding to the second chip on the communication bus as expected; a determination unit, configured to determine whether the detected target event meets expectations of the first chip based on the compensation signal; and a signal generation unit, configured to generate a target event corresponding to the first chip on the communication bus when it is determined that the detected target event meets the expectations of the first chip.
Regarding claim 16, none of the cited references either alone or in combination teaches a compensation signal generating device, comprising: a detection unit, configured to detect a target event on a communication bus, the target event including a compensation signal; a determination unit, configured to determine, based on the detected target event, whether there is at least one chip that fails to generate a target event corresponding to the chip on the communication bus as expected; and a signal generation unit, configured to generate a corresponding compensation signal on the communication bus in response to a determination that there is at least one chip that fails to generate a target event corresponding to the chip on the communication bus as expected.
Claims 2-5, 7-10, and 17-23 are allowed because they are dependent on the allowed claims.
US PGPUB 2022/0100434 to Wang discloses a main controller that generates a clock synchronization signal to a plurality of chips. No mention of the compensation signal being generated in response to that some or all of the at least one second chip fail to generate a target event corresponding to a second chip on the communication bus as expected; determining whether the detected target event meets expectations of the first chip based on the compensation signal; and in response to a determination that the detected target event meets the expectations of the first chip, generating a target event corresponding to the first chip on the communication bus is present.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent 8,928,505 to Coenen discloses that adjusting a frequency of a clock oscillator compensates for frequency of the clock (Col. 12, Lines 13-15, actively compensate the frequency of the clock signals by adjusting the frequency of oscillator 48 and the base frequency responsively to providing the new values to oscillator 48).
US PGPUB 2016/0337556 to Akita discloses that clock rate matching is the same as clock synchronization (Paragraph 0024, if the frequencies of a data signal and a clock signal do not match, the signals are not synchronized).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY Z WANG whose telephone number is (571)270-1716. The examiner can normally be reached 9 am - 3 pm (Monday-Friday).
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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