DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/28/2025, 05/29/2025, and 03/19/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 3, 8, 10, 13-14, and 19 are objected to because of the following informalities:
“The method according to any one of claims 1” in line 1 of claim 3 should read as “The method according to claim 1”.
“according to any one of claims 6” in line 1 of claim 8 should read as “according to claim 6”.
“a connection state between the first chip and the host device.” in line 2 of claim 10 should read as “a connection state between the first chip and the host device,”.
“after the starting point. or, setting a time point” in lines 10-11 of claim 13 should read as “after the starting point, or, setting a time point”.
“according to claims 11” in line 1 of claim 14 should read as “according to claim 11”.
“according to claims 16” in line 1 of claim 19 should read as “according to claim 16”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“a detection unit, configured to detect a target event” in claims 6, 21, and 23 with corresponding structure in Paragraphs [0128]-[0130].
“a determination unit, configured to determine” in claims 6, 21, and 23 with corresponding structure in Paragraph [0131].
“a signal generation unit, configured to generate a target event” in claims 6, 21, and 23 with corresponding structure in Paragraph [0132].
“a setting up unit, configured to set a time point of at least part of signals” in claim 18.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 18 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 18, claim element “a setting up unit, configured to set a time point of at least part of signals” invokes 35 U.S.C. 112(f), but the written description fails to disclose the corresponding structure, material, or acts for the claimed function.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitation “a setting up unit, configured to set a time point of at least part of signals” recited in claim 18 invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The disclosure is devoid of any structure that performs the function in the claim. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, and 10-23 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2022/0100434) in view of Cheng (US 2023/0341887).
Regarding claim 1, Wang teaches a communication method (Fig. 6, Method performed on bus system between image forming apparatus and plurality of chips), comprising: detecting a target event on a communication bus (Fig. 6, Chips 1 and 2 detects clock synchronization signal; Paragraph 0090, main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip), the communication bus being configured to be electrically connected to a first chip and at least one second chip (Fig. 6, Communication bus connected to chip 1 and chip 2), the target event including a compensation signal (Fig. 7, Chip 1 response is a low level to high level to low level pulse which is a compensation signal); determining whether the detected target event meets expectations of the first chip based on the compensation signal (Fig. 7, Counter of chip 1 is used to measure the number of preset pulses C1 (i.e. meets expectations of the first chip) after the clock synchronization signal is transmitted via the main controller; Paragraph 0139, the image forming apparatus… transmit the clock synchronization signal… Paragraph 0140, counter of the chip 1 may count received pulse signals from zero after receiving the clock synchronization signal. When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)); and when it is determined that the detected target event meets the expectations of the first chip, generating a target event corresponding to the first chip on the communication bus (Fig. 7, When counter of chip 1 reaches the preset first count value C1, chip 1 then transmits a low level signal (i.e. a target event); Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1), the chip controller of the chip 1 may control the installation detecting terminal of the chip 1 to output a low level to the installation detecting pin through the communication bus).
Wang does not teach the communication method comprising the compensation signal being used to indicate that some or all of the at least one second chip fail to generate a target event corresponding to a second chip on the communication bus as expected.
Cheng teaches the communication method (Fig. 1, Method occurs between master device 1 and first slave device 121 where master transmits a signal to the slave) comprising the compensation signal (Fig. 5, Step S504 involves the master sending an address checking signal (i.e. compensating signal) which occurs after the first slave device 121 fails step S502 to transmit a response bit to the master device (i.e. signal S504 occurs after signal S501 and thus compensates for the failure of signal S501); Paragraph 0036, the method which the master device performs the address checking for each of the slave devices is described as… the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device… Paragraph 0040, S504, the master device uses a clock signal with a clock frequency 200 KHz to perform an addressing check to the three slave devices) being used to indicate that some or all of the at least one second chip fail to generate a target event corresponding to a second chip on the communication bus as expected (Fig. 1, First slave device 121 fails to send proper response to the master device 11 which is determined by address checking unit 41 within master device; Paragraph 0036, If the address checking unit 41 determines that the address checking unit 41 doesn't accept the response bit, the checking result is failed).
Wang and Cheng are analogous art because they are from the same field of endeavor of synchronizing clock frequencies on a communication bus between master and slave devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s method to incorporate the teachings of Cheng and allow the master device to send the compensation signal in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 2, Wang in view of Cheng teaches the method of claim 1.
Cheng teaches the method comprising wherein the compensation signal is generated by a host device on the communication bus, and the host device is configured to generate the compensation signal on the communication bus when it is detected that some or all of the at least one second chip fail to generate the target event corresponding to the second chip on the communication bus as expected, or, when the first chip is further configured to communicate with at least two second chips through the communication bus, the compensation signal is used to indicate that some of the at least two second chips fail to generate a target event corresponding to a second chip on the communication bus as expected, and the compensation signal is generated by some or all of the second chips other than second chips, among the at least two second chips, that fail to generate corresponding target events on the communication bus as expected (The ‘or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 5, step S504 where the master device (i.e. a host) generates an address checking signal using 200Khz clock frequency (i.e. compensation signal) in response to the slave device (i.e. second chip) failing to transmit a response to the master device; Paragraph 0039, In step S502, whether the checking result is successful or failed is determined… the first operating frequency is reduced to 200 KHz, and step S504 is executed… Paragraph 0040, In step S504, the master device uses a clock signal with a clock frequency 200 KHz to perform an addressing check).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s method to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 3, Wang in view of Cheng teaches the method of claim 1. Wang teaches the method comprising wherein, when the target event corresponding to the first chip and the compensation signal are level signals respectively, a level width of the target event corresponding to the first chip is different from a level width of the compensation signal (Fig. 11, Level widths of the chip response signals occur after different t1 to t4 times which affects widths of signals).
Regarding claim 5, Wang in view of Cheng teaches the method of claim 1. Wang teaches the method comprising wherein the target event corresponding to the first chip is used to determine a connection state between the first chip and the host device and/or, wherein the target event corresponding to the first chip is used to determine a communication rate between the first chip and the host device ((The ‘and/or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 7, chip 1 response which indicates that the host and chip 1 are successfully connected and synchronized; Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)… a current loop may be formed between the chip 1 and the image forming apparatus).
Regarding claim 6, Wang teaches a control device (Fig. 6, Image forming apparatus), comprising: a detection unit (Fig. 6, Timer of chips 1 and 2), configured to detect a target event on a communication bus (Fig. 6, Chips 1 and 2 detects clock synchronization signal from timer; Paragraph 0090, main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip), the communication bus being electrically connected to a first chip and at least one second chip (Fig. 6, Communication bus connected to chip 1 and chip 2), the target event including a compensation signal (Fig. 7, Chip 1 response is a low level to high level to low level pulse which is a compensation signal); a determination unit (Fig. 6, Chip controller of chips 1 and 2 determines preset timing value (i.e. target event); Paragraph 0097, timer may be configured inside the chip controller, or configured independently from the chip controller and electrically connected to the chip controller, which may be specifically configured to measure time information), configured to determine whether the detected target event meets expectations of the first chip based on the compensation signal (Fig. 7, Counter of chip 1 is used to measure the number of preset pulses C1 (i.e. meets expectations of the first chip) after the clock synchronization signal is transmitted via the main controller; Paragraph 0139, the image forming apparatus… transmit the clock synchronization signal… Paragraph 0140, counter of the chip 1 may count received pulse signals from zero after receiving the clock synchronization signal. When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)); and a signal generation unit (Fig. 6, Installation detecting terminal generates the signal; Paragraph 0091, chip controller of each chip may control the installation detecting terminal of each chip to output the low level to the installation detecting pin), configured to generate a target event corresponding to the first chip on the communication bus when it is determined that the detected target event meets the expectations of the first chip (Fig. 7, When counter of chip 1 reaches the preset first count value C1, chip 1 then transmits a low level signal (i.e. a target event); Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1), the chip controller of the chip 1 may control the installation detecting terminal of the chip 1 to output a low level to the installation detecting pin through the communication bus).
Wang does not teach the control device comprising the compensation signal being configured to indicate that some or all of the at least one second chip fail to generate a target event corresponding to the second chip on the communication bus as expected.
Cheng teaches the control device comprising the compensation signal (Fig. 5, Step S504 involves the master sending an address checking signal (i.e. compensating signal) which occurs after the first slave device 121 fails step S502 to transmit a response bit to the master device (i.e. signal S504 occurs after signal S501 and thus compensates for the failure of signal S501); Paragraph 0036, the method which the master device performs the address checking for each of the slave devices is described as… the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device… Paragraph 0040, S504, the master device uses a clock signal with a clock frequency 200 KHz to perform an addressing check to the three slave devices) being configured to indicate that some or all of the at least one second chip fail to generate a target event corresponding to the second chip on the communication bus as expected (Fig. 1, First slave device 121 fails to send proper response to the master device 11 which is determined by address checking unit 41 within master device; Paragraph 0036, If the address checking unit 41 determines that the address checking unit 41 doesn't accept the response bit, the checking result is failed).
Wang and Cheng are analogous art because they are from the same field of endeavor of synchronizing clock frequencies on a communication bus between master and slave devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s device to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 7, Wang in view of Cheng teaches the device of claim 6.
Cheng teaches the device comprising wherein the compensation signal is generated by a host device on the communication bus, and the host device is configured to generate the compensation signal on the communication bus when it is detected that some or all of the at least one second chip fail to generate the target event corresponding to the second chip on the communication bus as expected, or, when the first chip is further configured to communicate with at least two second chips through the communication bus, the compensation signal is used to indicate that some of the at least two second chips fail to generate a target event corresponding to a second chip on the communication bus as expected, and the compensation signal is generated by some or all of the second chips other than second chips, among the at least two second chips, that fail to generate corresponding target events on the communication bus as expected (The ‘or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 5, step S504 where the master device (i.e. a host) generates an address checking signal using 200Khz clock frequency (i.e. compensation signal) in response to the slave device (i.e. second chip) failing to transmit a response to the master device; Paragraph 0039, In step S502, whether the checking result is successful or failed is determined… the first operating frequency is reduced to 200 KHz, and step S504 is executed… Paragraph 0040, In step S504, the master device uses a clock signal with a clock frequency 200 KHz to perform an addressing check).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s device to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 8, Wang in view of Cheng teaches the device of claim 6. Wang teaches the device comprising wherein, when the target event corresponding to the first chip and the compensation signal are level signals respectively, a level width of the target event corresponding to the first chip is different from a level width of the compensation signal (Fig. 11, Level widths of the chip response signals occur after different t1 to t4 times which affects widths of signals).
Regarding claim 10, Wang in view of Cheng teaches the device of claim 6. Wang teaches the device comprising wherein the target event corresponding to the first chip is used to determine a connection state between the first chip and the host device and/or, wherein the target event corresponding to the first chip is used to determine a communication rate between the first chip and the host device ((The ‘and/or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 7, chip 1 response which indicates that the host and chip 1 are successfully connected and synchronized; Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)… a current loop may be formed between the chip 1 and the image forming apparatus).
Regarding claim 11, Wang teaches a communication method (Fig. 6, Method performed on bus system between image forming apparatus and plurality of chips), comprising: detecting a target event on a communication bus (Fig. 6, Chips 1 and 2 detects clock synchronization signal; Paragraph 0090, main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip); determining whether there is at least one chip that generates a target event corresponding to the chip on the communication bus as expected based on the detected target event (Fig. 7, Counter of chip 1 is used to measure the number of preset pulses C1 (i.e. meets expectations of the first chip) after the clock synchronization signal is transmitted via the main controller; Paragraph 0139, the image forming apparatus… transmit the clock synchronization signal… Paragraph 0140, counter of the chip 1 may count received pulse signals from zero after receiving the clock synchronization signal. When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)); and generating a corresponding compensation signal on the communication bus (Fig. 7, When counter of chip 1 reaches the preset first count value C1, chip 1 then transmits a low level signal (i.e. a target event); Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1), the chip controller of the chip 1 may control the installation detecting terminal of the chip 1 to output a low level to the installation detecting pin through the communication bus).
Wang does not teach the communication method comprising determining whether there is at least one chip that fails to generate a target event; and when it is determined that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected, generating a corresponding compensation signal on the communication bus.
Cheng teaches the communication method (Fig. 1, Method occurs between master device 1 and first slave device 121) comprising the communication method comprising determining whether there is at least one chip that fails to generate a target event (Fig. 5, Determine failure at step S502; Paragraph 0036, If the address checking unit 41 determines that the address checking unit 41 doesn't accept the response bit, the checking result is failed); and when it is determined that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected, generating a corresponding compensation signal on the communication bus (Fig. 5, Generate compensating signal S504 in response to S502 failing; Paragraph 0036, the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device, and the address checking unit 41 will determine whether the master device accept a response bit transmitted by the slave device).
Wang and Cheng are analogous art because they are from the same field of endeavor of synchronizing clock frequencies on a communication bus between master and slave devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s method to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 12, Wang in view of Cheng teaches the method of claim 11. Wang teaches the method comprising wherein generate a target event corresponding to the chip on the communication bus as expected (Fig. 7, Chip 1 response generation), generating a corresponding compensation signal on the communication bus further comprises: when it is determined that there is a target event corresponding to the chip on the communication bus in a time window corresponding to the chip, generating a corresponding compensation signal on the communication bus (Fig. 7, Chip 1 response occurs in a time window with preset T1, T2, T3, and T4 times).
Cheng teaches the method comprising wherein, when it is determined that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected (Fig. 5, Step 502 fails where slave does not respond with correct response bit) and the method comprising generating a corresponding compensation signal on the communication bus further comprises: when it is determined that there is at least one chip that fails to generate a target event corresponding to the chip on the communication bus corresponding to the chip (Fig. 5, Generate compensating signal S504 in response to S502 failing; Paragraph 0036, the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device, and the address checking unit 41 will determine whether the master device accept a response bit transmitted by the slave device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s method to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 13, Wang in view of Cheng teaches the method of claim 12. Wang teaches wherein, before generating the corresponding compensation signal on the communication bus, the method further comprises: setting a time point at which at least part of signals included in a start signal generated by the host device is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point, or, setting a time point at which at least part of signals included in a compensation signal generated on the communication bus is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point, or, setting a time point at which at least part of signals included in a target event corresponding to the chip generated on the communication bus is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point (The ‘or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 7 where clock synchronization signal is a starting point of the time window with predefined times T1, T2, T3, and T4).
Regarding claim 14, Wang in view of Cheng teaches the method of claim 11. Wang teaches the method comprising wherein, when the target event corresponding to the first chip and the compensation signal are level signals respectively, a level width of the target event corresponding to the first chip is different from a level width of the compensation signal (Fig. 11, Level widths of the chip response signals occur after different t1 to t4 times which affects widths of signals).
Regarding claim 15, Wang in view of Cheng teaches the method of claim 11. Wang teaches wherein when the method is executed in a host device (Fig. 6, Image forming apparatus (i.e. a host device) contains installation detecting pin to determine successful connection; Paragraph 0071, output a low level to the installation detecting pin after the chip is powered on, such that a current loop may be formed between the chip and the image forming apparatus), the method further comprises: determining a connection state between the chip and the host device according to the target event corresponding to the chip and/or, determining a communication rate between the chip and the host device according to the connection status between the chip and the host device (The ‘and/or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 7, chip 1 response which indicates that the host and chip 1 are successfully connected and synchronized; Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)… a current loop may be formed between the chip 1 and the image forming apparatus).
Regarding claim 16, Wang teaches a compensation signal generating device (Fig. 6, Image forming apparatus), comprising: a detection unit (Fig. 6, Installation detecting pin), configured to detect a target event on a communication bus (Fig. 6, Installation detecting pin detects a low level output target event; Paragraph 0071, chip controller may be configured to control the installation detecting terminal of the chip to output a low level to the installation detecting pin); a determination unit (Fig. 6, Main controller of image forming apparatus determines target event), configured to determine, based on the target event, whether there is at least one chip that generates a target event corresponding to the chip on the communication bus as expected (Fig. 6, Main controller of image forming apparatus determines target event detected at the installation detecting pin; Paragraph 0079, main controller of the image forming apparatus may determine whether each chip is in a desired contact with the image forming apparatus according to the electrical parameter of the current loop formed between each chip and the image forming apparatus, where M is a natural number greater than or equal to 2).
Wang does not teach the compensation signal generating device, comprising the determination unit, configured to determine whether there is at least one chip that fails to generate a target event; and a signal generation unit configured to generate a corresponding compensation signal when it is determined that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected.
Cheng teaches the compensation signal generating device (Fig. 1, Master device 11), comprising the determination unit, configured to determine whether there is at least one chip that fails to generate a target event (Fig. 4, Address checking unit 41 determines if address check failed or succeeded; Paragraph 0031, address checking unit 41 is configured to check whether the master device successfully uses the clock frequency as the clock signal SCL of the first operating frequency); and a signal generation unit (Fig. 4, Clock signal generation units 42 and 43) configured to generate a corresponding compensation signal when it is determined that at least one chip fails to generate a target event corresponding to the chip on the communication bus as expected (Fig. 4, Generate compensating signal in clock signal generation units 42 and 43; Paragraph 0034, If the checking result is failed, then the frequency control unit 42 generates the first operating setting signal to reduce the first operating frequency, to make the address check unit check again whether the master successfully use the clock frequency as the clock signal SCL of the first operating frequency to address the multiple slave devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s device to incorporate the teachings of Cheng and allow the master device of Wang to generate and send the compensation signal in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 17, Wang in view of Cheng teaches the device of claim 16. Wang teaches the device comprising wherein the determination unit (Fig. 6, Main controller determines time window by transmitting clock synchronization signal to start time window in Figure 7) is configured to determine whether there is at least one chip to generate a target event corresponding to the chip on the communication bus in a time window corresponding to the chip based on the detected target event (Fig. 7, Chip 1 response occurs in a time window with preset T1, T2, T3, and T4 times).
Cheng teaches the device comprising wherein the determination unit is configured to determine whether there is at least one chip that fails to generate the target event corresponding to the chip on the communication bus corresponding to the chip based on the detected target event (Fig. 4, Address checking unit 41 determines if address check failed or succeeded; Paragraph 0031, address checking unit 41 is configured to check whether the master device successfully uses the clock frequency as the clock signal SCL of the first operating frequency); and the signal generation unit (Fig. 4, Clock signal generation units 42 and 43) is configured to generate a corresponding compensation on the communication bus when it is determined that there is at least one chip that fails to generate the target event corresponding to the chip on the communication bus corresponding to the chip (Fig. 5, Generate compensating signal S504 in response to S502 failing; Paragraph 0036, the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device, and the address checking unit 41 will determine whether the master device accept a response bit transmitted by the slave device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s method to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 18, Wang in view of Cheng teaches the device of claim 16. Wang teaches the device comprising: a setting up unit (Fig. 6, Main controller contains circuitry/software to determine time window; Paragraph 0090, the main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip through the communication bus), configured to set a time point at which at least part of signals included in a start signal generated by the host device is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point, or, setting a time point at which at least part of signals included in a compensation signal generated on the communication bus is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point, or, setting a time point at which at least part of signals included in a target event corresponding to the chip generated on the communication bus is generated as a starting point of the time window corresponding to the chip, wherein the time window corresponding to the chip is a predefined time period after the starting point (The ‘or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by Figure 7 where clock synchronization signal is a starting point of the time window with predefined times T1, T2, T3, and T4 and performed by main controller of image forming apparatus).
Regarding claim 19, Wang in view of Cheng teaches the device of claim 16. Wang teaches the device comprising wherein, when the target event corresponding to the first chip and the compensation signal are level signals respectively, a level width of the target event corresponding to the first chip is different from a level width of the compensation signal (Fig. 11, Level widths of the chip response signals occur after different t1 to t4 times which affects widths of signals).
Regarding claim 20, Wang in view of Cheng teaches the device of claim 16. Wang teaches the device further comprising: a control unit, configured to determine a connection state between the chip and the host device according to the target event corresponding to the chip and/or, the control unit is configured to determine a communication rate between the chip and the host device according to the connection status between the chip and the host device (The ‘and/or’ alternatives group only requires one of the elements, thus the italicized limitations above are taught by main controller of image forming apparatus detecting the chip 1 response which indicates that the host and chip 1 are successfully connected and synchronized; Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)… a current loop may be formed between the chip 1 and the image forming apparatus).
Regarding claim 21, Wang in view of Cheng teaches the compensation signal generating device of claim 16. Wang teaches a consumable (Fig. 1, Consumable system shown; Paragraph 0060, image forming apparatus shown in FIG. 1 as an example, the image forming apparatus may be detachably installed with 4 consumables), comprising: a housing (Fig. 1, Printer housing of the image forming apparatus); a developer accommodating portion, located in the housing, for accommodating a developer (Fig. 1, Developer accommodating portion 11 used to accommodate developer 13; Paragraph 0059, image forming portion of the image forming apparatus may include a developer accommodating portion 11, a developing element 12, a developer conveying element 13); and one of a control device (Fig. 6, Chip 1), and a compensation signal generating device that includes the compensation signal generating device according to claim 16 (Fig. 6, Image forming apparatus), wherein the control device includes: a detection unit (Fig. 6, Timer of chips 1 and 2), configured to detect a target event on a communication bus, the communication bus being electrically connected to a first chip and at least one second chip, the target event including a compensation signal (Fig. 6, Chips 1 and 2 detects clock synchronization signal from timer; Paragraph 0090, main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip); a determination unit (Fig. 6, Chip controller of chips 1 and 2 determines preset timing value (i.e. target event); Paragraph 0097, timer may be configured inside the chip controller, or configured independently from the chip controller and electrically connected to the chip controller, which may be specifically configured to measure time information), configured to determine whether the detected target event meets expectations of the first chip based on the compensation signal (Fig. 7, Counter of chip 1 is used to measure the number of preset pulses C1 (i.e. meets expectations of the first chip) after the clock synchronization signal is transmitted via the main controller; Paragraph 0139, the image forming apparatus… transmit the clock synchronization signal… Paragraph 0140, counter of the chip 1 may count received pulse signals from zero after receiving the clock synchronization signal. When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)); and a signal generation unit (Fig. 6, Installation detecting terminal generates the signal; Paragraph 0091, chip controller of each chip may control the installation detecting terminal of each chip to output the low level to the installation detecting pin), configured to generate a target event corresponding to the first chip on the communication bus when it is determined that the detected target event meets the expectations of the first chip (Fig. 7, When counter of chip 1 reaches the preset first count value C1, chip 1 then transmits a low level signal (i.e. a target event); Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1), the chip controller of the chip 1 may control the installation detecting terminal of the chip 1 to output a low level to the installation detecting pin through the communication bus).
Cheng teaches the control chip comprising the compensation signal (Fig. 5, Using second clock frequency to perform address checking in step S504 (i.e. signal S504 occurs after signal S501 and thus compensates for the failure of signal S501) occurs after the first slave device 121 fails step S502 to transmit a response bit to the master device; Paragraph 0036, the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device, and the address checking unit 41 will determine whether the master device accept a response bit transmitted by the slave device) being used to indicate that some or all of the at least one second chip fail to generate a target event corresponding to a second chip on the communication bus as expected (Fig. 1, First slave device 121 fails to send proper response to the master device 11 which is determined by address checking unit 41 within master device; Paragraph 0036, If the address checking unit 41 determines that the address checking unit 41 doesn't accept the response bit, the checking result is failed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s consumable to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Regarding claim 22, Wang in view of Cheng teaches the consumable of claim 21. Wang teaches the consumable further comprising: a developer conveying element for conveying the developer (Fig. 1, Conveying element 13; Paragraph 0059, a developer conveying element 13); and/or a photosensitive drum (Fig. 1, Drum 14; Paragraph 0059, photosensitive element 14 may include a photosensitive drum); and a charging roller (Fig. 1, Charging roller is included with photosensitive element 14) for charging the photosensitive drum (Paragraph 0059, a photosensitive element 14 may include a photosensitive drum (e.g., organic photoconductor drum (OPC)), a charging roller, and the like, where the charging roller may be configured to charge the photosensitive drum).
Regarding claim 23, Wang in view of Cheng teaches the control device of claim 16. Wang teaches a consumable (Fig. 1, Consumable system shown; Paragraph 0060, image forming apparatus shown in FIG. 1 as an example, the image forming apparatus may be detachably installed with 4 consumables), comprising: a photosensitive drum (Fig. 1, Photosensitive drum 14); a charging roller, used for charging the photosensitive drum (Paragraph 0059, a photosensitive element 14 may include a photosensitive drum (e.g., organic photoconductor drum (OPC)), a charging roller, and the like, where the charging roller may be configured to charge the photosensitive drum); and one of a control device (Fig. 6, Chip 1), and a compensation signal generating device that includes the compensation signal generating device according to claim 16 (Fig. 6, Image forming apparatus), wherein the control device includes: a detection unit (Fig. 6, Timer of chips 1 and 2), configured to detect a target event on a communication bus, the communication bus being electrically connected to a first chip and at least one second chip, the target event including a compensation signal (Fig. 6, Chips 1 and 2 detects clock synchronization signal from timer; Paragraph 0090, main controller may generate a clock synchronization signal and transmit the clock synchronization signal to the timer of each chip); a determination unit (Fig. 6, Chip controller of chips 1 and 2 determines preset timing value (i.e. target event); Paragraph 0097, timer may be configured inside the chip controller, or configured independently from the chip controller and electrically connected to the chip controller, which may be specifically configured to measure time information), configured to determine whether the detected target event meets expectations of the first chip based on the compensation signal (Fig. 7, Counter of chip 1 is used to measure the number of preset pulses C1 (i.e. meets expectations of the first chip) after the clock synchronization signal is transmitted via the main controller; Paragraph 0139, the image forming apparatus… transmit the clock synchronization signal… Paragraph 0140, counter of the chip 1 may count received pulse signals from zero after receiving the clock synchronization signal. When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1)); and a signal generation unit (Fig. 6, Installation detecting terminal generates the signal; Paragraph 0091, chip controller of each chip may control the installation detecting terminal of each chip to output the low level to the installation detecting pin), configured to generate a target event corresponding to the first chip on the communication bus when it is determined that the detected target event meets the expectations of the first chip (Fig. 7, When counter of chip 1 reaches the preset first count value C1, chip 1 then transmits a low level signal (i.e. a target event); Paragraph 0140, When the count value of the counting period of the chip 1 reaches the corresponding preset first count value (i.e., C1), the chip controller of the chip 1 may control the installation detecting terminal of the chip 1 to output a low level to the installation detecting pin through the communication bus).
Cheng teaches the control chip comprising the compensation signal (Fig. 5, Using second clock frequency to perform address checking in step S504 (i.e. signal S504 occurs after signal S501 and thus compensates for the failure of signal S501) occurs after the first slave device 121 fails step S502 to transmit a response bit to the master device; Paragraph 0036, the master transmit the start bit, the device address signal of the slave device and the write-in bit to the slave device, and the address checking unit 41 will determine whether the master device accept a response bit transmitted by the slave device) being used to indicate that some or all of the at least one second chip fail to generate a target event corresponding to a second chip on the communication bus as expected (Fig. 1, First slave device 121 fails to send proper response to the master device 11 which is determined by address checking unit 41 within master device; Paragraph 0036, If the address checking unit 41 determines that the address checking unit 41 doesn't accept the response bit, the checking result is failed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang’s consumable to incorporate the teachings of Cheng and allow the compensation signal to be sent in response to the chip failing to transmit a target event.
One of ordinary skill in the art would be motivated to make the modifications in order to enable the master device to successfully determine an optimal bit rate to communicate with the slave devices, thus reducing the error rate which improves system performance (See Cheng Paragraphs 0003 and 0004).
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2022/0100434) in view of Cheng (US 2023/0341887) and further in view of Fuhrmann (US 2010/0014439).
Regarding claim 4, Wang in view of Cheng teaches the method of claim 1. Wang teaches the method comprising wherein, when the target event corresponding to the first chip and the compensation signal are both level signals, determining whether the detected target event meets the expectations of the first chip based on the compensation signal (Fig. 7, Chip responses are all level signals between high and low levels).
Neither Wang nor Cheng teaches the method comprising wherein determining quantity information of predefined level signals in the target event detected on the communication bus and determining whether the target event detected on the communication bus meets the expectations of the first chip based on the quantity information of the predefined level signals and a predefined benchmark quantity information.
Fuhrmann teaches the method comprising wherein determining quantity information of predefined level signals in the target event detected on the communication bus and determining whether the target event detected on the communication bus meets the expectations of the first chip based on the quantity information of the predefined level signals and a predefined benchmark quantity information (Figs. 7 and 8 show cycle counter 71, slot counter 72, syncframe counter 81, bit counter 82 which determines number of cycles/slots (i.e. quantity information) and compares this information in modules 73 and 83 to determine if a predefined quantity information is met; Paragraph 0061, counting values (slot, cycle) are providing to a compare and reset unit 73. The compare and reset unit 73 further receives the number of static slots, the state of the Protocol Operation Control (POC) unit of the communication controller, the slot ID and the cycle ID. Based on these signals, the compare and reset unit 73 is able to compare the slot and cycle counter values of the communication controller 15 with its own slot and cycle counter values. In case of a mismatch, for instance if the slot counter of the communication controller 15 is reset during a state allowing no resetting, an error is detected… Paragraph 0052, Based on the received information, the host 13 may evaluate whether the communication controller 15 behaves correctly or not).
Wang and Fuhrmann are analogous art because they are from the same field of endeavor of synchronizing communications on a bus communication system.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang/Cheng’s method to incorporate the teachings of Fuhrmann and include error detection of communication cycle and slot quantity information of the level signals of Wang.
One of ordinary skill in the art would be motivated to make the modifications in order to increase error detection and mitigation for the communication system (See Fuhrmann: Paragraphs 0009-0014).
Regarding claim 9, Wang in view of Cheng teaches the device of claim 6. Wang teaches the device comprising wherein, when the target event corresponding to the first chip and the compensation signal are both level signals, determining whether the detected target event meets the expectations of the first chip based on the compensation signal (Fig. 7, Chip responses are all level signals between high and low levels).
Neither Wang nor Cheng teaches the device comprising wherein determining quantity information of predefined level signals in the target event detected on the communication bus and determining whether the target event detected on the communication bus meets the expectations of the first chip based on the quantity information of the predefined level signals and a predefined benchmark quantity information.
Fuhrmann teaches the device comprising wherein determining quantity information of predefined level signals in the target event detected on the communication bus and determining whether the target event detected on the communication bus meets the expectations of the first chip based on the quantity information of the predefined level signals and a predefined benchmark quantity information (Figs. 7 and 8 show cycle counter 71, slot counter 72, syncframe counter 81, bit counter 82 which determines number of cycles/slots (i.e. quantity information) and compares this information in modules 73 and 83 to determine if a predefined quantity information is met; Paragraph 0061, counting values (slot, cycle) are providing to a compare and reset unit 73. The compare and reset unit 73 further receives the number of static slots, the state of the Protocol Operation Control (POC) unit of the communication controller, the slot ID and the cycle ID. Based on these signals, the compare and reset unit 73 is able to compare the slot and cycle counter values of the communication controller 15 with its own slot and cycle counter values. In case of a mismatch, for instance if the slot counter of the communication controller 15 is reset during a state allowing no resetting, an error is detected… Paragraph 0052, Based on the received information, the host 13 may evaluate whether the communication controller 15 behaves correctly or not).
Wang and Fuhrmann are analogous art because they are from the same field of endeavor of synchronizing communications on a bus communication system.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang/Cheng’s device to incorporate the teachings of Fuhrmann and include error detection of communication cycle and slot quantity information of the level signals of Wang.
One of ordinary skill in the art would be motivated to make the modifications in order to increase error detection and mitigation for the communication system (See Fuhrmann: Paragraphs 0009-0014).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2020/0389244 to Furtner discloses a slave device that receives sample values from the master device that is used to compensate for phase offsets between the master and slave device.
US PGPUB 2018/0278352 to Hoshino discloses synchronization between a master and slave device.
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/H.Z.W./Examiner, Art Unit 2184
/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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