Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1-20, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jones et al (Pub. No.: US 2012/0044768).
3. Regarding independent claim 1, Jones et al teaches a system (Fig. 6), comprising: a memory array (Fig. 6, #201); and a controller (Fig. 6, #670) coupled to the memory array (Fig. 6, #201), the controller (Fig. 6, #670) to perform operations comprising: identifying (see Fig. 4, see paragraph [0033]) a set of memory cells (Fig. 2) for performing a memory programming operation (paragraph [0022]-[0023]), wherein the set of memory cells (Fig. 2) are electrically coupled to a target wordline (Fig. 2, one of WLs being selected, see paragraph [0023], lines 1-3) and two or more target bitlines (Fig. 2, two of BLs being selected by paragraph [0034], lines 1-8); classifying (Fig. 4, fast cell and slow cells, see paragraph [0034], lines 1-8) the set of memory cells (Fig. 2) into a first subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2) and a second subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2) based on their respective threshold voltages (see Fig. 4, the threshold of fast and slow cells); causing a first bias voltage (Fig. 4, paragraph [0034], lines 2-3 fast cell bias voltage) to be applied to a first target bitline (Fig. 2, one of fast bit lines paragraph [0034], line 2) connected to the first subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2); causing a second bias voltage (Fig. 4, paragraph [0034], lines 5-6 slow cell bias voltage) to be applied to a second target bitline (Fig. 2, slow bit line paragraph [0034], line 6) connected to the second subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2); and causing a programing voltage (see Fig. 4) to be applied to the target wordline (Fig. 2, one of WLs being selected, see paragraph [0023], lines 1-3).
4. Regarding claim 2, 9, 17, Jones et al teaches the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells (Fig. 2), wherein the read strobe returns a value of a bitline state metric (see Fig. 4, paragraph [0033]).
5. Regarding claim 3, 10, 18, Jones et al teaches the operations further comprise: responsive to determining that the value of the bitline state metric exceeds a predefined threshold (see paragraph [0038]), causing a second programing voltage to be applied to the target wordline (Fig. 2, one of WLs being selected, see paragraph [0023], lines 1-3).
6. Regarding claim 4, 11, 19, Jones et al teaches the operations further comprise: responsive to determining that the value of the bitline state metric exceeds a predefined threshold, terminating (see paragraph [0038], lines 6-11) a current programming operation (paragraph [0022]-[0023]) with respect to the set of memory cells (Fig. 2).
7. Regarding claim 5, 12, 20, Jones et al teaches the bitline state metric is provided by a failed byte count (Fig. 3).
8. Regarding claim 6, 13, Jones et al teaches classifying the set of memory cells (Fig. 2) further comprises: causing a read strobe to be performed with respect to the set of memory cells (Fig. 2), wherein the read strobe returns, for each memory cell (Fig. 2, #22), a value reflective (Fig. 4, Fig. 5, paragraph [0033], [0038]) of a threshold voltage of the memory cell (Fig. 2, #220).
9. Regarding claim 7, 14, Jones et al teaches the first subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2) have their respective threshold voltages (see Fig. 4, the threshold of fast and slow cells) lower than (see Fig.4) threshold voltages (see Fig. 4, the threshold of fast and slow cells) of the second subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2), and wherein the second bias voltage (Fig. 4, paragraph [0034], lines 5-6 slow cell bias voltage) exceeds the first bias voltage (Fig. 4, paragraph [0034], lines 2-3 fast cell bias voltage).
10. Regarding independent claim 8, Jones teaches a system (Fig. 6), comprising: a memory array (Fig. 6, #201); and a controller (Fig. 6, #670) coupled to the memory array (Fig. 6, #201), the controller (Fig. 6, #670)to perform operations comprising: classifying a set of memory cells (Fig. 2) into a first subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2) and a second subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2) based on their respective threshold voltages (see Fig. 4, the threshold of fast and slow cells); causing a first bias voltage (Fig. 4, paragraph [0034], lines 2-3 fast cell bias voltage) to be applied to a first target bitline (Fig. 2, one of fast bit lines paragraph [0034], line 2) connected to the first subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2); causing a second bias voltage (Fig. 4, paragraph [0034], lines 5-6 slow cell bias voltage) to be applied to a second target bitline (Fig. 2, slow bit line paragraph [0034], line 6) connected to the second subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2); and causing a programing voltage (Fig. 4) to be applied to a target wordline (Fig. 2, one of WLs being selected, see paragraph [0023], lines 1-3) that is electrically connected (see Fig. 2) to the set of memory cells (Fig. 2).
11. Regarding independent claim 15, Jones et al teaches a system (Fig. 6), comprising: a memory array (Fig. 6, #201); and a controller (Fig. 6, #670) coupled to the memory array (Fig. 6, #201), the controller (Fig. 6, #670)to perform operations comprising: causing a first programming pulse (Fig. 3, paragraph [0021], lines 1-6) to be performed by applying a first programming voltage to a target wordline (Fig. 2, one of WLs being selected, see paragraph [0023], lines 1-3) that is electrically connected to a set of memory cells (Fig. 2); classifying the set of memory cells (Fig. 2) into a first subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2) and a second subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2); causing a first bias voltage (Fig. 4, paragraph [0034], lines 2-3 fast cell bias voltage) to be applied to a first target bitline (Fig. 2, one of fast bit lines paragraph [0034], line 2) connected to the first subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2); causing a second bias voltage (Fig. 4, paragraph [0034], lines 5-6 slow cell bias voltage) to be applied to a second target bitline (Fig. 2, slow bit line paragraph [0034], line 6) connected to the second subset (Fig. 4, fast cells paragraph [0034], lines 1-4, or slow cells paragraph [0034], lines 4-8) of memory cells (Fig. 2); and causing a second programing voltage (Fig. 4, paragraph [0021], lines 6-11) to be applied to the target wordline (Fig. 2, one of WLs being selected, see paragraph [0023], lines 1-3).
12. Regarding claim 16, Jones et al teaches the second bias voltage (Fig. 4, paragraph [0034], lines 5-6 slow cell bias voltage) exceeds the first bias voltage (Fig. 4, paragraph [0034], lines 2-3 fast cell bias voltage).
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Dutta et al (Pub. No: US 2016/0314844).
Dutta et al (Pub. No: US 2016/0314844) shows the fast cells bit line bias voltage and the slow cells bit line bias voltage.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
07/22/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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