DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim 13 has been cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 11-12 and 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jones (US 20020180418).
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With respect to claim 1, figs. 1 and 2 of Jones disclose a circuit, comprising: a first input node (fig. 2 element 11) and a second input node (fig. 2 element 13) configured to receive current sensing signals (fig. 1) from terminals of a sensing circuit element (fig. 1 element 12);
a pair of transistors (fig. 2 elements 60 and 61) coupled to the first and the second input nodes and configured to provide an amplified current sensing signal at an output node via an output stage (fig. 2 element 18A, 22, 26 and 40);
wherein the pair of transistors (fig. 2 60 and 61) comprises a first transistor (fig. 2 element 60) having a current flow path therethrough via a first transistor node (emitter element 60) coupled to the first input node and a second transistor node (collector element 60) coupled to a first biasing current generator circuit (fig. 2 element 65) , and a second transistor (fig 2 element 61) having a current flow path therethrough via a third transistor node (emitter element 61) coupled to the second input node and a fourth transistor node (collector element 61) coupled to and the second biasing current generator circuit (fig. 2 element 66), the first and second transistors in the pair of transistors having a common control node (base connection of fig.2 element 60 and 61) ;
and an auxiliary amplifier circuit (fig. 2 elements 64, 65 and 66) having a first auxiliary input node (node of 65 connected to element 62) coupled between the first biasing current generator circuit and the second transistor node of the first transistor (fig. 2) and a second auxiliary input node (node of 66 coupled to element 63) coupled between the second biasing current generator circuit and the fourth transistor node of the second transistor (fig 2 collector of 61), the auxiliary amplifier circuit further having an output node (node connecting 64 to bases of elements 60 and 61) generating a control signal (22 is a control signal that is feedback through node 20 to first and second auxillary input signals) dependent on signals at the first and second auxiliary input nodes, said control signal applied to the common control node of the pair of transistors (fig. 2).
With respect to claim 2, Jones et al. discloses the circuit of claim 1, wherein the auxiliary amplifier circuit (fig. 2 elements 64, 65 and 66) comprises: an auxiliary differential arrangement of transistors comprising transistors (65 and 66) having a common biasing node (ground) coupled to a biasing current generator referred to ground; and an auxiliary current mirror arrangement (60 and 61 are mirrored) of transistors coupled to the first input node (11) and to the auxiliary differential arrangement of transistors (65 and 66).
With respect to claim 3, Jones et al. discloses the circuit of claim 1, wherein said output stage comprises: a further arrangement of transistors (26) coupled to the pair of transistors (60 and 61); and a set of resistive elements (40, note it is within the scope of the invention for Rout to be resistive elements) interposed between the further arrangement of transistors (26) and ground.
With respect to claim 4, Jones et al. discloses the circuit of claim 1, wherein said pair of transistors (60 and 61) comprises bipolar junction transistors (BJT).
With respect to claim 5, Jones et al. disclose the circuit of claim 1, comprising a minimum selector circuit (i.e. 16 and 19 would suffice to be the selector circuit as well as any circuit upstream from 18A as these features go to the function of the selection which is inherent in the operation of the ampifier) coupled to the auxiliary amplifier circuit (64, 65 and 66) .
With respect to claim 6, Jones et al. discloses the circuit of claim 1, comprising a diode (either 67 or 68) coupled to the common control node of the pair of transistors (60 and 61) of the circuit. (Here, it is believed claim 6 depends on claim 1.)
With respect to claim 7, Jones et al. discloses the circuit of claim 1, comprising: a current mirror arrangement of transistors (60 and 61) configured to mirror said current sensing signal (through diodes); wherein the current mirror arrangement of transistors comprises a first current mirror transistor (60) coupled to the first input node (11) and a second current mirror transistor (61) coupled to the second input node (13), the first current mirror transistor and the second current mirror transistor having a common control node (at base).
With respect to claim 8, Jones et al. discloses the circuit of claim 7, comprising a further current mirror arrangement of transistors (65 and 66) coupled in series with the current mirror arrangement of transistors (60 and 61).
With respect to claim 9, Jones et al. discloses the circuit of claim 8, wherein the transistors in the further current mirror arrangement of transistors (aux circuit comprising 65 and 66) have a different multiplication factor value in order to introduce an offset current to turn off the auxiliary amplifier circuit. (here, the transistors inherently have a multiplication factor value).
With respect to claim 11, Jones et al. discloses the circuit of claim 10, further comprising a clamping diode (Here the clamping diode is interpreted as the mirror element of 65) connected between the output from said further current mirror arrangement of transistors and the common control node of the pair of transistors.
With respect to claim 12, Jones et al. discloses a current sensing device, comprising: a power supply (V3 element 14 or alternatively i.e. VDD) configured to supply an electrical current; a load circuit (15 or alternatively at Vout or i.e Rout) coupled to the power supply to receive the electrical current therefrom; a sensing circuit element (see fig. 1 element 12) interposed the power supply and the load circuit and having a current flow therethrough indicative of a current flowing in said load circuit (15 or alternatively at Vout or i.e Rout), and the circuit of claim 1 coupled to the sensing circuit element (i.e. diode 67 or 68) to receive the current sensing signal therefrom and to provide an amplified current sensing signal at the output node.
With respect to claim 14, Jones (US 20020180418) discloses a circuit comprising: a first input node (11) configured to receive a first current sensing signal from a first terminal ((-) at 11) of a sensing circuit element (12); a second input node (13) configured to receive a second current sensing signal from a second terminal ((+) at 13) of the sensing circuit element (12); a first transistor (fig. 2 element 60) having a first current path (running through 16) coupled to receive the first current sensing signal (from (-) at 11); a first current source (16 is coupled in series with 60 via 17 and 60 being downstream) coupled in series with the first transistor (60) at a first amplifier input node (amplifier input node 17); a second transistor (61) having a second current path (path through 19) coupled to receive the second current sensing signal ((+) at 13); a second current source (19 is coupled in series with 61 via 20 and 61 being downstream) coupled in series with the second transistor (61) at a second amplifier input node (20); a differential ampler circuit (18A) having first and second amplifier inputs coupled to the first and second amplifier input nodes, respectively, and having an amplifier output (22) coupled to common control nodes (at base of 60 and 61) of the first (60) and second (61) transistors, and a first output transistor (26) having a control terminal (base of 26) coupled to first amplifier input node (via the amplifier) and a transistor terminal (control terminal via 20) coupled to the second transistor (61).
With respect to claim 15, Jones (US 20020180418) discloses the circuit of claim 14, further comprising: a third transistor (65) coupled to the first transistor (60) and having a third current path coupled in series with a third current source (64 in series with 65 via ground), and a fourth transistor (66) coupled to the second transistor (61) and having a fourth current path (through 63) coupled in series with a fourth current source; wherein the third and fourth transistors are connected as a first current mirror circuit (65 and 66 are a current mirror circuit).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones (US 20020180418) In view of Vosteen (US 3077566).
With respect to claim 10, Jones et al. discloses the circuit of claim 8, wherein the output stage comprises: a first output transistor (within op amp) having a control node coupled to receive a first control signal (62) generated by an output from said pair of transistors (60 and 61) ; a second output transistor (within op amp) having a control node coupled to receive a second control signal (63) generated by an output from said further current mirror arrangement of transistors (65 and 66) ; wherein the first and second output transistors are connected in parallel (here, the structure of the op amp would be such that the transistors inside would be connected in parallel configuration and thus is within the scope of the invention. See for example US 3077566 fig.1 showing transistors 13 and 14 in parallel between 15 and 19) demonstrating common op amp construction).
Allowable Subject Matter
Claim 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 16, the prior art of record fails to suggest or disclose the circuit of claim 15, further comprising: a fifth transistor coupled between the third transistor and the third current source; and a sixth transistor coupled between the fourth transistor and the fourth current source; wherein the fifth and sixth transistors are connected as a second current mirror circuit.
Here, there is not a fifth nor sixth transistor coupled in a current mirror circuit.
With respect to claim 17, the prior art of record fails to suggest or disclose the circuit of claim 15, further comprising a second output transistor having a control terminal coupled to the series coupling of the third transistor and third current source and a transistor terminal coupled to the fourth transistor.
Here, a second output transistor as specified is not present in the cited prior art.
With respect to claim 18, the prior art of record fails to suggest or disclose the circuit of claim 17, wherein the first and second output transistors are connected in parallel.
Here, claim 18, is allowable based on its dependence on claim 17.
Response to Arguments
Applicant's arguments filed 4/20/2026 have been fully considered but they are not persuasive.
With respect to applicant’s argument that there is no teaching for the auxiliary amplifier circuit, the Examiner disagrees. The examiner points out the amplifier 65, 66 and 64 amplify the input signal to produce an amplified output signal and therefore are sufficient to be interpreted as an auxiliary amplifier by increasing the magnitude of the input signal producing a proportionally larger output signal.
Applicant argues the components 65 and 66 have been used to meeting biasing current generator, the Examiner points out anything upstream would meet the terminology of a generator and the separate component of the amplifier would be suitable to this effect.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2836
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