DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the phrase “the oscillator comprises a first inductor and a second inductor, a capacitor device, a first transistor and a second transistor that are formed on the base substrate layer;” renders the claim indefinite. It is unclear whether “formed on the base substrate layer” refers to only the first and second transistors, or whether it also refers to the inductors and capacitor device. Examiner’s best interpretation based on the specification and remainder of the claim (e.g., “first inductor and the second inductor are… provided on different second device structure layers” recited later in claim 1) is the former interpretation. Appropriate correction is required. Claims 2-19 rejected by nature of dependency upon claim 1.
Further regarding claim 1, the phrase “the first inductor and the second inductor are symmetric with respect to a same symmetry axis” further renders the claim indefinite. It is unclear whether each inductor is, itself, symmetric across the same symmetry axis or whether the inductors are symmetric to each other across the same symmetry axis. Claims 6, 11-13, 15 further recite “symmetry axis” and are indefinite for similar reasons. Appropriate correction is required. Claims 2-19 rejected by nature of dependency upon claim 1.
Regarding claim 14, the term “the metal strips” lacks antecedent basis. Appropriate correction is required.
Regarding claim 17, the term “the second device structure layer” is indefinite. Claim 1 recites a plurality of second device structure layers. It is unclear whether “the second device structure layer” as recited by claim 17 is meant to refer to one or all of the second device structure layers.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9, 11-13, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20050231295 A1 to Maeda.
Regarding claim 1,
US 20050231295 A1 to Maeda teaches:
A semiconductor integrated circuit, comprising:
a base substrate layer, ([0014, 45] – “semiconductor substrate”) and a plurality of metal layers disposed on the base substrate layer and insulated from each other; (Fig. 4 – layers 3, 4, 5, 7, 8, 9, 2, 11, 6) wherein the plurality of metal layers comprise:
a shielding structure layer, (Fig. 4 – shield pattern 11; [0046] – “in the vertical structure, one more wiring layer is interposed between the wiring layers used for the first three-terminal inductor 2 and second three-terminal inductor 6. This interposed wiring layer forms a shield pattern 11 that is connected to GND or VCC.”) a first device structure layer, (Figs. 1, 4; [0041-42] – capacitors 3, 4, 7, 8) and a plurality of second device structure layers, ([0046] – “In the same manner as in Embodiment 2, each of the two different wiring layers is allocated exclusively to one of the first and second three- terminal inductors 2 and 6.”) and the semiconductor integrated circuit comprises an oscillator for outputting differential signals; (Fig. 4; [0046] – “FIG. 4 is a plan view showing the structure of the three-terminal inductors constructing the voltage controlled oscillators of Embodiment 3”)
the oscillator comprises a first inductor and a second inductor, (Fig. 4 – inductors 2, 6) a capacitor device, (Figs. 1, 4; [0041-42] – capacitors 3, 4, 7, 8) a first transistor and a second transistor that are formed on the base substrate layer; (Figs. 1, 4; [0041-42] – “transistors 5, 9) wherein the first inductor and the second inductor are symmetric with respect to a same symmetry axis (Fig. 4) and are provided on different second device structure layers, ([0046] – “in the vertical structure, one more wiring layer is interposed between the wiring layers used for the first three-terminal inductor 2 and second three-terminal inductor 6.” See also rejection under 35 U.S.C. § 112.) and the capacitor device is provided on the first device structure layer; (Figs. 1, 4; [0041-42] – capacitors 3, 4, 7, 8) and
the shielding structure layer is provided with a shielding structure for shielding interference signals leaked by the first inductor and/or the second inductor. ([0046-47] – “Thereby, the first three-terminal inductor 2 and second three-terminal inductor 6 which are separated vertically in the vertical structure are also separated by the shield pattern 11, thus preventing any decrease in Q due to magnetic coupling of the first three-terminal inductor 2 and the second three-terminal inductor 6”)
Regarding claim 2,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, the shielding structure comprises a plurality of metal wires, which are arranged to form a non-closed charge cancellation path; (Fig. 4 – shield pattern 11; [0046-47] – “in the vertical structure, one more wiring layer is interposed between the wiring layers used for the first three-terminal inductor 2 and second three-terminal inductor 6. This interposed wiring layer forms a shield pattern 11 that is connected to GND or VCC.”)
wherein the plurality of metal wires are arranged along a current direction of an inductor, and an extension direction of the plurality of metal wires is perpendicular to the current direction. (Figs. 1, 4; [0046-47] – “The shield pattern 11 has an area substantially the same as the area of the three- terminal inductors 2 and 6 and is provided with a plurality of slits.”)
Regarding claim 3,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, an orthographic projection of the capacitor device on the base substrate layer (Figs. 1, 4; [0041-42] – capacitors 3, 4, 7, 8) does not coincide with an orthographic projection of the shielding structure on the base substrate layer. (Fig. 4 – shield pattern 11)
Regarding claim 5,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, the first inductor comprises a non-closed polygonal annular inductor structure, and a first connection portion connected with the annular inductor structure; (Figs. 1, 4 – connection portions 3, 4, 5, or connection portion (vertical portions connecting annular portion of inductor 2 with elements 3, 4, 5) of inductor 2, compare to instant application Fig. 4 first connection portion 212)
the annular inductor structure comprises a plurality of segments, which are sequentially connected, the first connection portion comprises a first connection sub-portion and a second connection sub-portion, and the first connection sub-portion and the second connection sub-portion are connected with two ends of the annular inductor structure, respectively. (Figs. 1, 4, compare to instant application Fig. 4 first connection portion 212, first connection sub-portion 2121, second connection sub-portion 2122)
Regarding claim 6,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, the first inductor comprises a second connection portion which is provided on the symmetry axis, and the second connection portion is a control terminal of the first inductor. (Figs. 1, 4 – connection portion Vcc, [0042] – “ The first and second three- terminal inductors 2 and 6 are both formed with the same wiring layer of the semiconductor integrated circuit, with the center-tapped terminals of each inductor connected to VCC,” compare to instant application Fig. 4 connection portion 213, see also rejection under 35 U.S.C. § 112)
Regarding claim 7,
Maeda teaches:
The semiconductor integrated circuit according to claim 5, (see rejection of claim above)
wherein, the first connection sub-portion and the second connection sub-portion are rectangular inductor structures. (Figs. 1, 4 – connection portion (vertical portions connecting annular portion of inductor 2 with elements 3, 4, 5) of inductor 2, compare to instant application Fig. 4 first connection portion 212)
Regarding claim 8,
Maeda teaches:
The semiconductor integrated circuit according to claim 5, (see rejection of claim above)
wherein, the shielding structure layer comprises a first shielding structure for shielding an induced current of the annular inductor structure, the first shielding structure comprises a plurality of sub-structures, and a layout position of each sub-structure corresponds to that of a segment of the annular inductor structure. (Figs. 1, 4; [0046-47] – “The shield pattern 11 has an area substantially the same as the area of the three- terminal inductors 2 and 6 and is provided with a plurality of slits.”)
Regarding claim 9,
Maeda teaches:
The semiconductor integrated circuit according to claim 5, (see rejection of claim above)
the shielding structure comprises a sub-structure for shielding the first connection sub-portion and a sub-structure for shielding the second connection sub-portion; (Figs. 1, 4; [0046-47] – “The shield pattern 11 has an area substantially the same as the area of the three- terminal inductors 2 and 6 and is provided with a plurality of slits.”)
wherein each sub-structure comprises a plurality of metal wires provided on the shielding structure layer, in each sub-structure one terminal of each of adjacent metal wires is connected to each other (Figs. 1, 4; [0046-47] – “The shield pattern 11 has an area substantially the same as the area of the three- terminal inductors 2 and 6 and is provided with a plurality of slits.”) and the other terminal of each of the adjacent metal wires is disconnected, and the two sub-structures are connected through a metal wire, such that the two sub-structures as a whole form a non-closed charge cancellation path. ([0045-46] – “in the vertical structure, the first three-terminal inductor 2 and the three-terminal inductor 6 are separated vertically, so that there is no need for the interlayer contacts 10… The difference from Embodiment 2 lies in that, in the vertical structure, one more wiring layer is interposed between the wiring layers used for the first three-terminal inductor 2 and second three-terminal inductor 6. This interposed wiring layer forms a shield pattern 11 that is connected to GND or VCC.”)
Regarding claim 11,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, a control terminal of the oscillator is located on the symmetry axis, and a first output terminal and a second output terminal of the oscillator are arranged symmetrically with respect to the symmetry axis. (Figs. 1, 4, see also rejection under 35 U.S.C. § 112)
Regarding claim 12,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, the second inductor is provided as a metal structure extending along a direction of the symmetry axis, and a projection of the second inductor is partially or entirely located within a region uncovered by a projection of the first inductor. (Figs. 1, 4, see also rejection under 35 U.S.C. § 112)
Regarding claim 13,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein the second inductor comprises one or more of the following structures: a coil structure symmetrical with respect to the symmetry axis, (Figs. 1, 4; [0014] – “The apparatus is characterized in that two of the three-terminal or two-terminal inductors constructing the first and second voltage controlled oscillators have a coil shape formed with a wiring layer,” see also rejection under 35 U.S.C. § 112) a bent structure arranged along a direction of the symmetry axis, and a strip-shaped structure arranged along the direction of the symmetry axis. (Figs. 1, 4)
Regarding claim 15,
Maeda teaches:
The semiconductor integrated circuit according to claim 5, (see rejection of claim above)
wherein an orthographic projection of a first terminal and an orthographic projection of a second terminal of the second inductor are both located on the symmetry axis. (Figs. 1, 4, see also rejection under 35 U.S.C. § 112)
Claim(s) 1, 4-5, 11-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20140159825 A1 to Samala
Regarding claim 1,
US 20140159825 A1 to Samala teaches:
A semiconductor integrated circuit, comprising:
a base substrate layer, and a plurality of metal layers disposed on the base substrate layer and insulated from each other; wherein the plurality of metal layers comprise: (Figs. 3, 5)
a shielding structure layer, (Figs. 5, 6; [0020] – “high Q shielded inductor… Both these inductors 505 and 510 have shield structures to improve the quality factor. They are interleaved at the ends in a symmetric manner”) a first device structure layer, (Figs. 3, 5-6 – capacitor 315 and/or pair of cross coupled transistors 330, implemented as n-channel transistors) and a plurality of second device structure layers, (Figs. 3, 5-6; [0022] – “In one embodiment, the center tapped inductor 310 and degeneration inductor 335 are implemented as illustrated in FIG. 5, 505 and 510 respectively. The center tapped inductor 505 and degeneration inductor 510 are implemented in different thick metals.”) and the semiconductor integrated circuit comprises an oscillator for outputting differential signals;
the oscillator comprises a first inductor and a second inductor, (Figs. 3, 5 – inductors 310, 335) a capacitor device, (Figs. 3, 5-6 – capacitor 315) a first transistor and a second transistor that are formed on the base substrate layer; (Figs. 3, 5-6 – A pair of cross coupled transistors 330, implemented as n-channel transistors)
wherein the first inductor and the second inductor are symmetric with respect to a same symmetry axis and are provided on different second device structure layers, (Figs. 3, 5-6; [0022] – “In one embodiment, the center tapped inductor 310 and degeneration inductor 335 are implemented as illustrated in FIG. 5, 505 and 510 respectively. The center tapped inductor 505 and degeneration inductor 510 are implemented in different thick metals.” See also rejection under 35 U.S.C. § 112.) and the capacitor device is provided on the first device structure layer; (Figs. 3, 5-6 – capacitor 315) and
the shielding structure layer is provided with a shielding structure for shielding interference signals leaked by the first inductor and/or the second inductor. (Figs. 5, 6; [0020] – “high Q shielded inductor… Both these inductors 505 and 510 have shield structures to improve the quality factor.”)
Regarding claim 4,
Samala teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein a first terminal of the first inductor is connected with a first terminal of the capacitor device, a first electrode of the first transistor, and a control electrode of the second transistor; (Fig. 3 – inductor 310, capacitor 315, pair of cross coupled transistors 330; compare to instant application Fig. 2)
a second terminal of the first inductor is connected with a second terminal of the capacitor device, a first electrode of the second transistor and a control electrode of the first transistor; (Fig. 3 – inductor 310, capacitor 315, pair of cross coupled transistors 330; compare to instant application Fig. 2)
a control terminal of the first inductor is connected to a voltage terminal; (Fig. 3 – inductor 310, supply terminal Vdd, compare to instant application Fig. 2)
a second electrode of the first transistor is connected with a first terminal of the second inductor; (Fig. 3 – pair of cross coupled transistors 330, inductor 335, compare to instant application Fig. 2)
a second electrode of the second transistor is connected with the first terminal of the second inductor; (Fig. 3 – pair of cross coupled transistors 330, inductor 335, compare to instant application Fig. 2)
a second terminal of the second inductor is grounded; (Fig. 3 – inductor 335; [0019] – “inductor 335 is coupled to the pair of cross coupled transistors 330 and to the ground terminal,” compare to instant application Fig. 2)
the second electrode of the first transistor is connected with a first output terminal of the oscillator; (Fig. 3 – transistors 330; [0018] – “drains of the transistors 330 are cross coupled to the opposite gates,” compare to instant application Fig. 2)
the second electrode of the second transistor is connected with a second output terminal of the oscillator; (Fig. 3 – transistors 330; [0018] – “drains of the transistors 330 are cross coupled to the opposite gates,” compare to instant application Fig. 2) and
the first output terminal and the second output terminal of the oscillator output differential signals. ([0048] – “The pair of cross coupled transistors 330 is used to compensate for the losses in the variable capacitor 315 and the inductor 310. The pair of cross coupled transistors 330 creates negative impedance that compensate for the losses. The output voltage of the VCO is available at the drains of the transistors 330 and to keep best waveform symmetry and efficiency, it is drawn in a differential way via suitable followers.”)
Regarding claim 5,
Samala teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, the first inductor comprises a non-closed polygonal annular inductor structure, and a first connection portion connected with the annular inductor structure; (Figs. 5-6, compare to instant application Fig. 4 first connection portion 212)
the annular inductor structure comprises a plurality of segments, which are sequentially connected, the first connection portion comprises a first connection sub-portion and a second connection sub-portion, and the first connection sub-portion and the second connection sub-portion are connected with two ends of the annular inductor structure, respectively. (Figs. 5-6, compare to instant application Fig. 4 first connection portion 212, first connection sub-portion 2121, second connection sub-portion 2122)
Regarding claim 11,
Samala teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, a control terminal of the oscillator is located on the symmetry axis, and a first output terminal and a second output terminal of the oscillator are arranged symmetrically with respect to the symmetry axis. (Figs. 3, 5, 6, see also rejection under 35 U.S.C. § 112)
Regarding claim 12,
Samala teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, the second inductor is provided as a metal structure extending along a direction of the symmetry axis, and a projection of the second inductor is partially or entirely located within a region uncovered by a projection of the first inductor. (Figs. 3, 5, 6, see also rejection under 35 U.S.C. § 112)
Regarding claim 13,
Samala teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein the second inductor comprises one or more of the following structures: a coil structure symmetrical with respect to the symmetry axis, a bent structure arranged along a direction of the symmetry axis, and a strip-shaped structure arranged along the direction of the symmetry axis. (Fig. 3, 5, see also rejection under 35 U.S.C. § 112)
Regarding claim 14,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
Maeda does not appear to explicitly teach the additional elements of the claim.
However, US 20190238004 A1 to Zargham teaches:
parallel metal strips in the second inductor (Fig. 3; [0084] – “The inductor may comprise a plurality of parallel conductive metal strips to meet density rules and reduce high-frequency eddy losses.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Zargham’s known technique to Maeda’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Maeda teaches a base VCO apparatus including inductors; (2) Zargham teaches a specific technique of splitting an inductor into a plurality of parallel conductive metal strips to meet density rules and reduce high-frequency eddy losses; (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in a system with improved ability to meet density rules and reduce high-frequency eddy losses; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
A modification of the combination of Maeda in view of Zargham to set the recited strip and spacing widths would have been obvious to try as one of a finite number of identified, predictable solutions with a reasonable expectation of success. Such a finding is proper because (1) at the time of the invention, there had been a recognized problem or need in the art, in this case a need to choose inductor strip and spacing widths to meet desired densities and decrease loss (E.g., see Zargham [0084] ; (2) there are a finite number of identified, predictable potential solutions to the recognized need or problem; (3) one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim 15,
Samala teaches:
The semiconductor integrated circuit according to claim 5, (see rejection of claim above)
wherein an orthographic projection of a first terminal and an orthographic projection of a second terminal of the second inductor are both located on the symmetry axis. (Figs. 3, 5, 6, see also rejection under 35 U.S.C. § 112)
Regarding claim 16,
Samala teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
wherein, the shielding structure layer comprises a second shielding structure for shielding an induced current of the second inductor. (Figs. 5, 6; [0020] – “high Q shielded inductor… Both these inductors 505 and 510 have shield structures to improve the quality factor. They are interleaved at the ends in a symmetric manner”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20050231295 A1 to Maeda in view of US 20190238004 A1 to Zargham.
Regarding claim 10,
Maeda teaches:
The semiconductor integrated circuit according to claim 5, (see rejection of claim above)
Maeda does not appear to explicitly teach the additional elements of the claim.
However, US 20190238004 A1 to Zargham teaches:
wherein, each segment of the annular transistor structure comprises a plurality of metal strips arranged in a same direction; (Fig. 3; [0084] – “The inductor may comprise a plurality of parallel conductive metal strips to meet density rules and reduce high-frequency eddy losses.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Zargham’s known technique to Maeda’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Maeda teaches a base VCO apparatus including inductors; (2) Zargham teaches a specific technique of splitting an inductor into a plurality of parallel conductive metal strips to meet density rules and reduce high-frequency eddy losses; (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in a system with improved ability to meet density rules and reduce high-frequency eddy losses; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
A modification of the combination of Maeda in view of Zargham to set the recited strip and spacing widths would have been obvious to try as one of a finite number of identified, predictable solutions with a reasonable expectation of success. Such a finding is proper because (1) at the time of the invention, there had been a recognized problem or need in the art, in this case a need to choose inductor strip and spacing widths to meet desired densities and decrease loss (E.g., see Zargham [0084] ; (2) there are a finite number of identified, predictable potential solutions to the recognized need or problem; (3) one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20050231295 A1 to Maeda in view of US 20090322446 A1 to Daley.
Regarding claim 17,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
Maeda does not appear to explicitly teach the additional elements of the claim.
However, US 20090322446 A1 to Daley teaches:
wherein the first device structure layer is located between the second device structure layer and the shielding structure layer. (Figs. 4, 4A; [0051] – “the stacked arrangement of the on-chip capacitor 16, on-chip inductor 20 and Faraday shield 60 of the BEOL wiring structure 10 may be modified” See also rejection under 35 U.S.C. § 112.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Daley’s known technique to Maeda’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Maeda teaches a base VCO apparatus including inductor, capacitor, and shield layers; (2) Daley teaches specific and interchangeable orders between inductor, capacitor, and shield layers; (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in a system with improved flexibility of shape / order of layers; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20050231295 A1 to Maeda in view of US 20080297414 A1 to Krishnaswamy.
Regarding claim 18,
Maeda teaches:
The semiconductor integrated circuit according to claim 1, (see rejection of claim above)
Maeda does not appear to explicitly teach the additional elements of the claim.
However, US 20080297414 A1 to Krishnaswamy teaches:
A phase-locked loop, (Figs. 4 – PLL 405)
wherein the phase-locked loop comprises a frequency phase detector, (Figs. 4 – frequency phase detector 408) a charge pump, (Figs. 4 – charge pump 410) a filter, (Figs. 4 – loop filter 412) and an oscillator (Figs. 4; [0061] – “FIG. 4(b) depicts the representative tunable oscillator 402 as utilized for FIG. 4(a)”) and a frequency divider (Figs. 4 – frequency divider 406) which are arranged in the semiconductor circuit; ([00134, claims 9-10] – “The circuit of claim 8, wherein the plurality of tunable amplifiers and first phase-locked loop are disposed on a semiconductor substrate… The circuit of claim 8, wherein the plurality of tunable amplifiers and first phase-locked loop are disposed on a semiconductor substrate.”)
wherein, a first input terminal of the frequency phase detector is an input terminal of the phase-locked loop, a second input terminal of the frequency phase detector is connected with an output terminal of the frequency divider, and an output terminal of the frequency phase detector is connected with an input terminal of the charge pump; (Fig. 4A) and
an output terminal of the charge pump is connected with an input terminal of the filter, an output terminal of the filter is connected with a control terminal of the oscillator, and an output terminal of the oscillator is connected with an input terminal of the frequency divider. (Fig. 4A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Krishnaswamy’s known technique to Maeda’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Maeda teaches a base VCO apparatus including inductors and capacitors; (2) Krishnaswamy teaches a PLL to be implemented in integrated circuit with layered substrates, metals, etc. (E.g., see Fig. 12, [0112] – “Regarding fabrication of architecture UWB VPRO-PLL 1200, as depicted in micrograph portion of FIG. 12, the architecture 1200 was implemented in a 0.13 CMOS process with 8 metal layers,” [0038] – “FIG. 12 depicts an ultra-wideband (UWB) VPRO-PLL transmitter phased array architecture overlaid on a chip micrograph of a corresponding integrated circuit,” (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in a system with improved implementation; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim 19,
Maeda in view of Krishnaswamy teaches:
the phase-locked loop is the phase-locked loop according to claim 18 (see rejection of claim above)
Krishnaswamy further teaches:
A radar sensor, comprising a signal receiving module, ([0121] – “radar receiver would use an identical VPRO to correlate with the incoming signal, and distortion in the transmitter and receiver front-end circuits reduces the signal-to-noise ratio ("SNR") benefit achieved through matched filtering.”) a signal transmitting module, (Fig. 4; [0133] – “Accordingly, exemplary embodiments of the present disclosure can provide a fully-integrated, UWB, multiple channel (e.g., 4-channel) K-band CMOS, phased-array transmitter, related circuits/architectures, and related methods. Such embodiments can be used for transmitter vehicular radar applications”) and a clock source, (Figs. 4; [0059] – “the phase loop sets the necessary phase shift between adjacent elements in the ring configuration while the frequency loop forces the oscillation frequency to be equal to that of a reference.”) wherein the signal transmitting module is configured to transmit an electromagnetic wave signal via a transmitting antenna based on a reference frequency provided by a phase-locked loop in the clock source, ([0059-60] – “the phase loop sets the necessary phase shift between adjacent elements in the ring configuration while the frequency loop forces the oscillation frequency to be equal to that of a reference… The PLL shown also… can serve to modulate arbitrary transmit waveforms and distribute them to all elements ”) and the signal receiving module is configured to receive an echo reflected by a target object using a receiving antenna, and perform down-conversion processing based on the reference frequency provided by the phase-locked loop in the clock source to generate and output an intermediate frequency signal; (Fig. 5-6; [0060] – “the PLL can also demodulate arbitrary received waveforms and combine them” [0069] – “down-converted baseband information, .theta..sub.BB(t).” [0072] – “down-converted received wave form 612”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Krishnaswamy’s known technique to Maeda’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Maeda teaches a base VCO apparatus including inductors and capacitors; (2) Krishnaswamy teaches a PLL to be implemented in integrated circuit with layered substrates, metals, etc. (E.g., see Fig. 12, [0112] – “Regarding fabrication of architecture UWB VPRO-PLL 1200, as depicted in micrograph portion of FIG. 12, the architecture 1200 was implemented in a 0.13 CMOS process with 8 metal layers,” [0038] – “FIG. 12 depicts an ultra-wideband (UWB) VPRO-PLL transmitter phased array architecture overlaid on a chip micrograph of a corresponding integrated circuit,” (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in a system with improved implementation; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim 20,
Maeda in view of Krishnaswamy teaches:
the phase-locked loop according to claim 18. (see rejection of claim above)
Krishnaswamy further teaches:
An electronic apparatus comprising the phase-locked loop (Fig. 4; [0133] – “Accordingly, exemplary embodiments of the present disclosure can provide a fully-integrated, UWB, multiple channel (e.g., 4-channel) K-band CMOS, phased-array transmitter, related circuits/architectures, and related methods. Such embodiments can be used for transmitter vehicular radar applications”)
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/JULIANA CROSS/Examiner, Art Unit 3648
/BRADY W FRAZIER/Primary Examiner, Art Unit 3648
