DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Remarks/Arguments
With respect to the rejection of claim 1 under 35 USC 102(a)(2), Applicant's arguments filed 06/19/2026 have been fully considered but are moot in view of new grounds of rejection set forth herein as necessitated by Applicant's amendments.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/27/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6, 9, 10, 13, 15-17, 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li (US 11,494,627 A1).
Regarding claim 1, Li teaches a neural network circuit (Fig. 1, col. 1, lines 48-49, a neural network accelerator) comprising:
a first set of cascaded processing element (PE) circuits (Fig. 1, a row of cell 10), wherein an output of a first PE circuit in the first set is coupled to an input of a second PE circuit in the first set (Fig. 1, an output of a cell 10 is an input of subsequent cell 10, see top row for example) and wherein each PE circuit (Fig. 1, 10) in the first set of cascaded PE circuits comprises:
a multiply-and-accumulate (MAC) circuit (Fig. 2, 110, 112, col. 3, lines 44-47, multiplier 110, adder-comparator 112);
a local accumulator circuit having an input coupled to an output of the MAC circuit (Fig. 2, , col. 3, lines 44-47, accumulator register 114); and
a set of flip-flops having an input coupled to an output of the local accumulator circuit (Fig. 2, col. 3, lines 57-58, output register 118); and
a first global accumulator circuit (Fig. 1, col. 2, line 20, edge cell 12, Fig. 3, col. 4, accumulation by adder-comparator 112) having an input coupled to an output of the first set of cascaded PE circuits (Fig. 1, 12 gets input from cascaded cells 10),
wherein each PE circuit in the first set of cascaded PE circuits is configured to concurrently and independently perform a MAC operation with the MAC circuit (Figs. 1 and 2, col. 2, line 21, 2D multiplication; Fig. 4, 12, 10, col. 5, lines 42-46, four independent process streams can operate simultaneously) and a shift operation with the set of flip-flops to shift a value from the PE circuit to a next PE circuit in the first set of cascaded PE circuits or to the first global accumulator circuit (Figs. 1 and 2, col. 3, lines 57-60, shifted into the next computations cell 10).
Regarding claim 3, all the limitations of claim 1 are taught by Li.
Li further teaches the circuit, further comprising a memory (Fig. 3, 114), wherein: the first global accumulator circuit is configured to write partial sums to (Fig. 3, partial sum from 112), and read the partial sums from (Fig. 3, from 114 to 112), the memory; and
the first set of cascaded PE circuits is not configured to write the partial sums to, or read the partial sums from, the memory (Fig. 1, 10 does not have access to 114 of 12).
Regarding claim 4, all the limitations of claim 1 are taught by Li.
Li further teaches the circuit wherein the first global accumulator circuit (Figs. 1 and 3, 12) comprises:
a first accumulator (Fig. 3, 112);
a flip-flop array (114) having an input coupled to an output of the first accumulator;
a write register (102); and
a first multiplexer (130) having a first input coupled to an output of the write register (102), having a second input coupled to an output of the flip-flop array (output of 114 through 118 to 130), and having an output coupled to a first input of the first accumulator (output of 130 to 112 via 110).
Regarding claim 5, all the limitations of claim 4 are taught by Li.
Li further teaches the circuit wherein the first global accumulator circuit further comprises a read register having an input coupled to the output of the flip-flop array (Fig. 3, 118).
Regarding claim 6, all the limitations of claim 5 are taught by Li.
Li further teaches the circuit further comprising a tightly coupled memory (Fig. 1, WGT 22, OUT 26, col. 2, line 36, weight registers 22, line 40, output registers 26), wherein the first global accumulator circuit further comprises:
a write bus coupled between an output of the read register and the tightly coupled memory (Fig. 3, output from 118); and
a read bus coupled between the tightly coupled memory and an input of the write register (input to 102).
Regarding claim 9, all the limitations of claim 1 are taught by Li.
Li further teaches the circuit, wherein the first set of cascaded PE circuits comprises a number of cascaded PE circuits, such that the first global accumulator circuit is configured to receive a partial sum from the first PE circuit through all the PE circuits in the first set after a number of activation-input-bit cycles has occurred that matches the number of cascaded PE circuits (Figs. 1~3, col. 3, lines 57~65).
Regarding claim 10, all the limitations of claim 1 are taught by Li.
Li further teaches the circuit, wherein: the first global accumulator circuit is configured to receive a partial sum from the first PE circuit through all the PE circuits in the first set after a number of activation-input-bit cycles has occurred (Figs. 1~3, col. 3, lines 57~65); and
a number of cascaded PE circuits in the first set is greater than or equal to the number of activation-input-bit cycles (Figs. 1~3, col. 3, lines 57~65; shifted by control bits from 120).
Regarding claim 13, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 13 is rejected under the same rationale as claim 1 above.
Regarding claim 15, this claim has substantially the same subject matter as that in claim 3. Therefore, claim 15 is rejected under the same rationale as claim 3 above.
Regarding claim 16, this claim has substantially the same subject matter as that in claim 4. Therefore, claim 16 is rejected under the same rationale as claim 4 above.
Regarding claim 17, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 17 is rejected under the same rationale as claim 1 above.
Regarding claim 19, this claim has substantially the same subject matter as that in claim 3. Therefore, claim 19 is rejected under the same rationale as claim 3 above.
Regarding claim 20, this claim has substantially the same subject matter as that in claim 4. Therefore, claim 20 is rejected under the same rationale as claim 4 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 8, 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 11,494,627 A1) in view of Meyer (US 12,380,321 B1).
Regarding claim 7, all the limitations of claim 6 are taught by Li.
Li does not explicitly teach the circuit, further comprising a global memory coupled to the read bus of the first global accumulator circuit.
Meyer teaches a circuit comprising a global memory coupled to the read bus of the first global accumulator circuit (Fig. 2, 204, col. 9, line 50~52).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Meyer to the teachings of Li in order to provide storage for weights, input data and output data for proper operations (col. 9, lines 50~52).
Regarding claim 8, all the limitations of claim 1 are taught by Li.
Li does not explicitly teach the circuit, wherein the first set of cascaded PE circuits is configured such that weights are loaded in parallel into the first set of cascaded PE circuits.
Instead, Li teaches the first set of cascaded PE circuits is configured such that inputs are loaded in parallel into the first set of cascaded PE circuits (Fig. 1, IN 28).
Meyer teaches a circuit, wherein a first set of cascaded PE circuits is configured such that weights are loaded in parallel into the first set of cascaded PE circuits (Abstract).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the parallel loading of weights as taught by Meyer to the teachings of Li instead of parallel loading of inputs, in order to speed up weight loading time (Meyer, Abstract).
Regarding claim 14, this claim has substantially the same subject matter as that in claim 8. Therefore, claim 14 is rejected under the same rationale as claim 8 above.
Regarding claim 18, this claim has substantially the same subject matter as that in claim 8. Therefore, claim 18 is rejected under the same rationale as claim 8 above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Li (US 11,494,627 A1) in view of Seo (US 2026/0073208 A1).
Regarding claim 11, all the limitations of claim 1 are taught by Li.
Li does not explicitly teach the circuit, wherein each PE circuit in the first set of cascaded PE circuits is a digital compute-in-memory (DCIM) PE circuit, wherein the MAC circuit in each PE circuit comprises a DCIM array, wherein the DCIM array comprises a plurality of compute-in-memory cells, and wherein at least one of the compute-in-memory cells comprises an eight-transistor (8T) static random-access memory (SRAM) cell.
Seo teaches a circuit, wherein each PE circuit in the first set of cascaded PE circuits is a digital compute-in-memory (DCIM) PE circuit (Fig. 2), wherein the MAC circuit in each PE circuit comprises a DCIM array, wherein the DCIM array comprises a plurality of compute-in-memory cells, and wherein at least one of the compute-in-memory cells comprises an eight-transistor (8T) static random-access memory (SRAM) cell (Fig. 3A).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Seo to the teachings of Li in order to support a range of deep neural network (DNN) for fast and energy-efficient inference using such DNN models (Seo, [0029], [0030]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li (US 11,494,627 A1) in view of Tadishetti (US 2024/0320496 A1).
Regarding claim 12, all the limitations of claim 1 are taught by Li.
Li further teaches the circuit, further comprising:
a second set of cascaded PE circuits (Fig. 1, a second row), wherein an output of a first PE circuit in the second set is coupled to an input of a second PE circuit in the second set (computational cells 10 are cascaded) and wherein each PE circuit in the second set of cascaded PE circuits comprises:
a multiply-and-accumulate (MAC) circuit (Fig. 2, 110, 112, col. 3, lines 44-47, multiplier 110, adder-comparator 112);
a local accumulator circuit having an input coupled to an output of the MAC circuit (Fig. 2, , col. 3, lines 44-47, accumulator register 114); and
a set of flip-flops having an input coupled to an output of the local accumulator circuit (Fig. 2, col. 3, lines 57-58, output register 118); and
a second global accumulator circuit (Fig. 1, col. 2, line 20, edge cell 12, Fig. 3, col. 4, accumulation by adder-comparator 112) having an input coupled to an output of the first set of cascaded PE circuits (Fig. 1, 12 gets input from cascaded cells 10);
a first copy-flop having an input coupled to an output of the first global accumulator circuit (Fig. 1, 26, first row); and
a second copy-flop having a first input coupled to an output of the second global accumulator circuit and having a second input coupled to an output of the first copy-flop (Fig. 1, 26, second row).
Li does not explicitly teach the circuit, comprising a super global accumulator circuit having an input coupled to an output of the second copy-flop.
Tadishetti teaches a neural network circuit comprising a super global accumulator circuit having an input coupled to an output of the second copy-flop (Fig. 2B, reduction tree 270, output 295, [0050]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply a final accumulator to accumulate all the outputs from the array of PEs as taught by Tadishetti to the teachings of Li in order to process the output function of the neural network as commonly known in the art (Tadishetti, Fig. 1A, [0041]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2845
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