Detailed Action
Claims 1-9,11 are pending in this application. Claim 10 was cancelled. This is a response to the Amendments/Remarks filed on 6/24/26. This is a Final Rejection.
Claim Objections
Claims 1, objected to because of the following informalities:
As per claims 1, recites “further including a firewall positionable between a production server and the high-speed…”, should be “the production server” since step (a) already recites “a production server”.
As per claim 11, recites “(a) receiving data from a production server”, should be “the production server” since the preceding limitation “a firewall…between a production…”, already recites “a production server”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 9, 11 rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0272245 issued to Olarig et al.(Olarig) in view of US 2019/0012350 issued to Sindhu et al.(Sindhu) in view of Premio, How can DPU Servers Improve Data Centers?, https://premioinc.com/blogs/blog/how-can-dpu-servers-improve-data-centers, May 12, 2021,pgs 1-6, (Premio) in view of US 2014/0269288 issued to Crisan et al.(Crisan).
As per claim 1,11, Olarig teaches a high-speed data transfer architecture comprising: an ethernet switch(Fig.1A,B, [0034] Each of the switchboard 101a or 101b includes a central processing unit (CPU) 102, a baseboard management controller (BMC) 103, an Ethernet switch controller 105…..);
an ethernet interface communicating with the ethernet switch(Fig.1A,B, [0034]… a high-speed connector 115 for interfacing with a plurality of data storage devices 150 (e.g., NVMe SSDs or Ethernet SSDs (eSSDs)) via a common midplane 151, and a management local area network (LAN) port 116…..; high speed connector interpreted as the ethernet interface);
a bank of multiple solid-state drives(Fig.1A,B, [0034] …, a high-speed connector 115 for interfacing with a plurality of data storage devices 150 (e.g., NVMe SSDs or Ethernet SSDs (eSSDs)) via a common midplane 151….. An example of the data storage system 150 is a PM1725a NVMe SSD designed and manufactured by Samsung Electronics, Co. Ltd. In the following, the terms, data storage device and eSSD, may be interchangeably used for the convenience of explanation in some embodiments; however, it is understood that the data storage device 150 can be any type of data storage devices, for example, an NVMe SSD, an Ethernet SSD, and a multi-mode SSD that can be configured to as an NVMe SSD or an NVMe-oF SSD);
a processor communicating with the bank of multiple solid-state drives and the ethernet network interface(Fig.1A,B, [0034] Each of the switchboard 101a or 101b includes a central processing unit (CPU) 102, a baseboard management controller (BMC) 103, an Ethernet switch controller 105, a PCIe switch 106, a plurality of uplink ports 114 including Ethernet ports and PCIe ports, a high-speed connector 115 for interfacing with a plurality of data storage devices 150 (e.g., NVMe SSDs or Ethernet SSDs (eSSDs)) via a common midplane 151, and a management local area network (LAN) port 116….);
the processor, ethernet interface, operating to execute a stored program to:
(a) receive data from a host through the ethernet switch, ethernet interface, and processor for storage in the bank of multiple solid-state drives at a first data rate([0037] For example, each of the uplink ports is a 100 Gigabit Ethernet (Gbe) port. In the case of NVMe-oF, the host computer can send Ethernet packets to the switchboard 101 including commands to read, modify, and write data on the data storage devices 150. In the case of NVMe, the data storage device 150 is attached to a conventional X86-based motherboard (not shown));
(b) transmit the data from the bank of multiple solid-state drives through the processor and ethernet interface to the ethernet switch([0038] …, for example, one or more dual data rate 4 (DDR4) dual in-line memory modules (DIMMs) to facilitate transfer of data to and from the data storage devices 150 and control and efficiently manage the data storage devices 150. [0040] …. Ethernet and PCIe traffic sent to and received from each of the data storage devices 150 are routed through the Ethernet switch controller 105 and the PCIe switch 106 respectively.);
wherein the processor and ethernet interface further operate to execute the stored program to receive the data over ethernet([0037] For example, each of the uplink ports is a 100 Gigabit Ethernet (Gbe) port. In the case of NVMe-oF, the host computer can send Ethernet packets to the switchboard 101 including commands to read, modify, and write data on the data storage devices 150. In the case of NVMe, the data storage device 150 is attached to a conventional X86-based motherboard (not shown).
Olarig however does not explicitly teach a firewall postionable between a production server and the processor; ethernet switch communication with the Internet; a bank of at least one network processor communicating with the ethernet switch; b) transmit data for receipt by the network processors; and (c) transmit from the network processors to the Internet at a data rate in excess of 50 Gb per second. ; to independently transmit the data from the network processors to the Internet at the data rate in excess of 50 GB per second.
Sindhu teaches production server(para.22; teaches server); ethernet switch communication with the Internet(Fig.1A, switch fabric communication with network 7(ie Internet) [0038] … compute node 30A to network 50A, which may represent the Internet. Network 50A may be substantially similar to network 7 and/or switch fabric 14 from FIG. 1A…..);
a band of at least one network processor communicating with the ethernet switch(Fig.1A; ([0022] One or more of the devices in the different racks 20, 22, 24, or 26 may be configured to operate as storage systems and application servers for data center 10. For example, CPU rack 20 holds a plurality of CPU blades (“CPUs A-N”) 21 that each includes at least a CPU. One or more of CPU blades 21 may include a CPU, a DPU, and one or more storage devices, e.g., SSDs, communicatively coupled via PCI-e links or buses. In this implementation, the DPU is configured to retrieve data from the storage devices on behalf of the CPU, store data to the storage devices on behalf of the CPU, and retrieve data from network 7 and/or switch fabric 14 on behalf of the CPU….; [0038]; DPU interpreted as the network processors);
b) transmit data for receipt by the network processors ([0022] … In this implementation, the DPU is configured to retrieve data from the storage devices on behalf of the CPU, store data to the storage devices on behalf of the CPU, and retrieve data from network 7 and/or switch fabric 14 on behalf of the CPU….); and
(c) transmit from the network processors to the Internet, and to independently transmit the data from the network processors to the Internet(Fig.1B,2, [0016] In accordance with the techniques of this disclosure, the highly programmable DPU comprises a network interface (e.g., Ethernet) to connect to a network to send and receive stream data units (e.g., data packets)….);
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig’s switchboard used for storing data on eSSD to include Sindhu’s teaching of servers, and a DPU that receives data and transmit the data to the Internet in order to provide the predictable result of a switchboard with a DPU for receiving data from servers to be stored on eSSD and transmitting data from the eSSD to the Internet/customers.
One ordinary skill in the art would have been motivated to combine the teachings in order to use a highly programmable, high performance I/O and data processing hub which is designed to aggregate ad process network and storage I/O which frees up resources for the CPU(Sindhu, para.4).
Olarig in view of Sindu does not explicitly teach a firewall postionable between a production server and the high-speed data transfer architecture/processor; via the firewall and transmit at a data rate in excess of 50 Gb per second.
Premio explicitly teaches transmit at a data rate in excess of 50 Gb per second(pg.2, What is a DPU?; A DPU, also known as a data processing unit, is made from a Multi-core processor (usually an Arm processor), a network interface controller capable of transferring data at extremely high speeds (100 Gigabits/s to 200 Gigabits/s), a set of acceleration engines that accelerate application performance, and RAM memory, What are Common Configurations For a DPU Server? 3. High-Speed Network Connectivity, pg.4, High-performance DPU servers have a ton of connectivity via Ethernet LAN ports that are located both onboard and the DPUs themselves. The motherboard itself comes with 2x Gigabit Ethernet ports and a single management port. However, the amount of connectivity available depends on how many data processing units and regular NICs you configure your system with. Here are the performance specs of some of the most popular DPUs currently available: Xilinx Alveo U25 – 2x 25 Gigabit Ethernet Ports Xilinx Alveo U50 – 1x 100 Gigabit Ethernet Port Xilinx Alveo U 200 – 2x 100 Gigabit Ethernet Ports Xilinx Alveo U250 – 2x 100 Gigabit Ethernet Ports Xilinx Alveo U280 – 2x 100 Gigabit Ethernet Ports Nvidia Mellanox BlueField 2 – Dual Ports of 10/25/50/100 Gigabits or a single port of 200 Gigabits Silicom FPGA SmartNIC N5010 Series – 4x 100 Gigabit Ethernet Ports )
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig in view of Sindhu of a switchboard with a DPU for receiving data to be stored on eSSD and transmitting data from the eSSD to the Internet/customers to apply the teachings of Permio of a DPU can transmit data at high speed(100-200 Gb/s) in order to provide the predictable result of a switchboard with a DPU for receiving data to be stored on eSSD and transmitting data from the eSSD to the Internet/customers at high speeds(100-200 Gb/s).
One ordinary skill in the art would have been motivated to combine the teachings in order to use a highly programmable, high performance I/O and data processing hub which is designed to aggregate ad process network and storage I/O which frees up resources for the CPU(Sindhu, para.4, Pemio, pg.1, How Can DPU Servers Improve Data Centers?).
Olarig in view of Sinhu in view of Permio does not explicitly teach a firewall postionable between a production server and the high-speed data transfer architecture/processor; via the firewall; Olarig, para.37, teaches the the high-speed data transfer architecture/processor and Sinhu, para.22, teach a server.
Crisan explicitly teaches the use of the well known firewall( [0025] The network 101 can include a combination of wireless, wired, and/or fiber optic links. The network 101 as depicted in FIG. 1 represents a simplified example for purposes of explanation. Embodiments of the network 101 can include numerous switches 106 (e.g., hundreds) with dozens of ports and links per switch 106. The network 101 may support a variety of known communication standards that allow data to be transmitted between the servers 102, client systems 104, switches 106, network controller 112, firewalls(s) 114, and load balancer(s) 116. Communication protocols are typically implemented in one or more layers, such as a physical layer (layer-1), a link layer (layer-2), a network layer (layer-3), a transport layer (layer-4), and an application layer (layer-5). In exemplary embodiments, the network 101 supports OpenFlow as a layer-2 protocol. The switches 106 can be dedicated OpenFlow switches or OpenFlow-enabled general purpose switches that also support layer-2 (for example Ethernet) and layer-3 (for example Internet Protocol (IP)).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig in view of Sindhu in view of Permio of a switchboard with a DPU and ethernet switch for receiving data to be stored on eSSD and transmitting data to from the eSSD to the Internet/customers at high speeds(100-200 Gb/s) to apply the well known teaching of Crisan of the use of firewall in order to provide the predictable result of transmitting data from a server through a firewall to a switchboard with a DPU.
One ordinary skill in the art would have been motivated to combine the teachings in order to provide cyber security.
As per claim 2, Olarig in view of Sinhu in view of Permio teaches high-speed data transfer architecture of claim 1 wherein the bank of multiple solid-state drives includes at least two network processors each communicating with the ethernet switch for simultaneous transmission to the Internet to provide the data rate(Sinhu, Fig.1A shows multiple DPUs, Fig.1B, [0016] In accordance with the techniques of this disclosure, the highly programmable DPU comprises a network interface (e.g., Ethernet) to connect to a network to send and receive stream data units (e.g., data packets)….Permio, 3. High-Speed Network Connectivity, pg.4, High-performance DPU servers have a ton of connectivity via Ethernet LAN ports that are located both onboard and the DPUs themselves. The motherboard itself comes with 2x Gigabit Ethernet ports and a single management port. However, the amount of connectivity available depends on how many data processing units and regular NICs you configure your system with. Here are the performance specs of some of the most popular DPUs currently available: …. Nvidia Mellanox BlueField 2 – Dual Ports of 10/25/50/100 Gigabits or a single port of 200 Gigabits ; teaches the DPU with multiple ports and different data rate such as 10/25/50/100 Gb/s). Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig in view of Sindhu in view of Permio and Sindhu’s teaching of multiple DPUs for sending data to the Internet with Sindhu’s teachings of the DPUs having different data speed to design a system for multiple DPUs with different data rates for simultaneous transmission of data to achieve a particular data rate( ie one DPU transmitting at 25 Gb/s and another DPU transmitting at 50 Gb/s to achieve 75 Gb/s). One ordinary skill in the art would have been motivated to combine the teachings in order to use a highly programmable, high performance I/O and data processing hub which is designed to aggregate ad process network and storage I/O which frees up resources for the CPU(Sindhu, para.4, Pemio, pg.1, How Can DPU Servers Improve Data Centers?) and further to reduce the load on a particular DPU.
As per claim 9, Olarig in view of Sinhu in view of Permio teaches high-speed data transfer architecture of claim 1 wherein the network processors are data processing units integrating network interface hardware(Sinhu, Abstract, teaches DPU, Permio, pg.1, teaches DPU). Motivation to combine set forth in claim 1.
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0272245 issued to Olarig et al.(Olarig) in view of US 2019/0012350 issued to Sindhu et al.(Sindhu) in view of Premio, How can DPU Servers Improve Data Centers?, https://premioinc.com/blogs/blog/how-can-dpu-servers-improve-data-centers, May 12, 2021,pgs 1-6, (Premio) in view of US 2014/0269288 issued to Crisan et al.(Crisan) in view of US 2015/0106345 issued to Trimble et al.(Trimble).
As per claim 3, Olarig in view of Sinhu in view of Permio in view of Crisan teaches high-speed data transfer architecture of claim 1, however does not explicitly teach wherein the ethernet switch has a transmission capacity of greater than 100 Gb per second, which is taught by Trimble, [0042] ….In various embodiments, the forwarding device 106 includes a switch, such as Ethernet switch, or set of switches. These switches may be Ethernet switches capable of 1 Gb/s, 10 Gb/s, 40 Gb/s, 100 Gb/s, or greater data rates).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig in view of Sindhu in view of Permio in view of Crisan of a switchboard with a DPU for receiving data to be stored on eSSD and transmitting data from the eSSD to the Internet/customers at high speeds(100-200 Gb/s) to apply the teaching of Trimble of the ethernet switch capability of 100 Gb/s or greater in order to provide the predictable result of a switchboard with a DPU for receiving data at 100 Gb/s or greater to be stored on eSSD.
One ordinary skill in the art would have been motivated to combine the teachings in order to send/receive data at a high data rate which provides faster storage and access.
Claims 4-7 rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0272245 issued to Olarig et al.(Olarig) in view of US 2019/0012350 issued to Sindhu et al.(Sindhu) in view of Premio, How can DPU Servers Improve Data Centers?, https://premioinc.com/blogs/blog/how-can-dpu-servers-improve-data-centers, May 12, 2021,pgs 1-6, (Premio) in view of US 2014/0269288 issued to Crisan et al.(Crisan) in view of US 2021/0240579 issued to Khandkar et al.(Khandkar).
As per claim 4, Olarig in view of Sinhu in view of Permio in view of Crisan teaches high-speed data transfer architecture of claim 1, however does not explicitly teach wherein the bank of multiple solid-state drives have a capacity of at least 500 GB, which is taught by Khandkar, [0119] … Processor 1132 allows physical machine 1130 to execute computer-readable instructions stored in memory 1133 to perform processes described herein. Disk 1134 may include a HDD and/or a SSD. In some cases, disk 1134 may include a flash-based SSD or a hybrid HDD/SSD drive. In one embodiment, the storage appliance 1170 may include a plurality of physical machines arranged in a cluster (e.g., eight machines in a cluster). Each of the plurality of physical machines may include a plurality of multi-core CPUs, 128 GB of RAM, a 500 GB SSD, four 4 TB HDDs, and a network interface controller.
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig in view of Sindhu in view of Permio in view of Crisan of a switchboard with a DPU for receiving data to be stored on eSSD and transmitting data from the eSSD to the Internet/customers at high speeds(100-200 Gb/s) to apply the teaching of Khandkar of the SSD having a capacity of 500 GB in order to provide the predictable result of a switchboard with a DPU for receiving data to be stored on eSSD with 500 GB capacity and transmitting data from the eSSD to the Internet/customers at high speeds(100-200 Gb/s
One ordinary skill in the art would have been motivated to combine the teachings in order to store large amounts of data on SSD.
As per claim 5, Olarig in view of Sinhu in view of Permio in view of Crisan in view of Khandkar teaches high-speed data transfer architecture of claim 4 wherein the bank of multiple solid-state drives receive data using the NVMe protocol(Olarig, [0023] The present disclosure describes a common system platform that can support dissimilar non-volatile memory express (NVMe) over fabrics (NVMe-oF) devices made by different suppliers, and a multi-mode storage device that can be configured as an NVMe device or an NVMe-oF device. According to one embodiment, the present common system platform may refer to a rack-mountable chassis (or enclosure) including a midplane and one or more motherboards (in the case of NVMe devices) or one or more switchboards (in the case of NVMe of devices) that can respectively accept a plurality of NVMe or NVMe-oF devices. The present common system platform can support an NVMe-oF device with a standard U.2 connector (e.g., PM1725a/1735 SSDs) as well as new emerging devices such as New Form Factor 1 (NF1)-based SSDs using an M.2 connector.).
As per claim 6, Olarig in view of Sinhu in view of Permio in view of Crisan in view of Khandkar teaches high-speed data transfer architecture of claim 5 wherein the processor communicates with the bank of multiple solid-state drives over a Peripheral Component Interconnect Express (PCIe) bus(Olarig, Fig.1A, [0024] A multi-mode non-volatile memory express (NVMe) over fabrics (NVMe-oF) device can support either NVMe or NVMe-oF protocol by detecting information from a known location or a chassis type pin, for example, the pin E6 or a vendor-defined reserved pin of the U.2 connector depending on a chassis type that the multi-mode NVMe-oF device is inserted into. If the multi-mode NVMe-oF device is inserted to a drive bay of an NVMe chassis, all of the four peripheral component interconnect express (PCIe) lanes of the U.2 connector are driven by an embedded PCIe engine. In this case, the NVMe-oF device disables an embedded Ethernet engine, and all NVMe commands and functionalities are supported or enabled. On the other hand, if the multi-mode NVMe-oF device is inserted into a drive bay of an NVMe-oF chassis, the Ethernet ports of the NVMe-oF device are enabled and use as a data-plane. In this mode, the by-4 (×4) PCIe lanes are operated as two control planes as two by-2 (×2) PCIe lanes.).
As per claim 7, Olarig in view of Sinhu in view of Permio in view of Crisan teaches high-speed data transfer architecture of claim 1 wherein the communication between the ethernet interface and the processor and the ethernet interface and the ethernet switch (Olarig, Fig.1A) however does not explicitly teach the Network File System (NFS) protocol, which is taught by Khandkar, [0054] ….. The script information 140 may be communicated in a directory 130 that is independent of the multiples of four. According to one embodiment, the file information 142 and the script information 140 may be communicated, via the directories 130, utilizing the Network Files System (NFS) protocol. The NFS protocol is one of several distributed file system standards for network-attached storage. NFS is a distributed file system protocol that enables a user on a client computer to access files over a computer network as local storage is accessed. NFS builds on the Open Network Computing Remote Procedure Call (ONC RPC) system).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig in view of Sindhu in view of Permio in view of Crisan of a switchboard with a DPU and ethernet switch for receiving data to be stored on eSSD and transmitting data to from the eSSD to the Internet/customers at high speeds(100-200 Gb/s) to apply the well known teaching of Khandkar of the NFS protocol in order to provide the predictable result of a switchboard with a DPU and ethernet switch that uses NFS prtocol for receiving data to be stored on eSSD and transmitting data to from the eSSD to the Internet/customers at high speeds(100-200 Gb/s
One ordinary skill in the art would have been motivated to combine the teachings in order to access and share files and directories over a network easily.
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0272245 issued to Olarig et al.(Olarig) in view of US 2019/0012350 issued to Sindhu et al.(Sindhu) in view of Premio, How can DPU Servers Improve Data Centers?, https://premioinc.com/blogs/blog/how-can-dpu-servers-improve-data-centers, May 12, 2021,pgs 1-6, (Premio) in view of US 2014/0269288 issued to Crisan et al.(Crisan) in view of US 2018/0067810 issued to Li
As per claim 8, Olarig in view of Sinhu in view of Permio in view of Crisan teaches high-speed data transfer architecture of claim 1, a processor(Olarig, Fig.1A; it is obvious to one ordinary skill in the art that a processor has RAM and DRAM memory) however does not explicitly teach wherein the processor is a von Neumann CPU with an internal cache memory of static random access memory communicating in a memory hierarchy with dynamic random access memory holding at least a portion of the program, which is taught by Li, para.25,61,75; teaches von Neumann CPU and RAM and DRAM memory.
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Olarig in view of Sindhu in view of Permio in view of Crisan of a switchboard with a processor and DPU and ethernet switch for receiving data to be stored on eSSD and transmitting data from the eSSD to the Internet/customers at high speeds(100-200 Gb/s) to apply the well known teaching of Li of the von Neumann CPU with RAM and DRAM memory in order to provide the predictable result of a switchboard with a von Neumann CPU with RAM and DRAM and DPU and ethernet switch for receiving data to be stored on eSSD and transmitting data from the eSSD to the Internet/customers at high speeds(100-200 Gb/s)
One ordinary skill in the art would have been motivated to combine the teachings in order to provide flexibility, simplicity and low cost.
Response to Arguments
The applicant overcame the previous claim objection and 112(b) rejection therefore those objection are withdrawn, however the amendment to claims raised new claim objections.
Applicant's arguments filed 6/24/26 have been fully considered but they are not persuasive. The applicant argues in substance that the prior art does not teach the present invention provides a burst buffer with a dedicated processor that can be positioned outside of a firewall from the production server and operate independently, and the combination of the prior art does not teach an autonomous burst buffer as claimed positioned outside of a firewall from the production server.
In reply to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a burst buffer with a dedicated processor and/or an autonomous burst buffer ) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
US 2021/0373951 issued to Malladi et al., teaches determining a first value of a parameter associated with at least one first device in a first cluster; determining a threshold based on the first value of the parameter; receiving a request for processing a workload at the first device; determining that a second value of the parameter associated with at least one second device in a second cluster meets the threshold; and responsive to meeting the threshold, routing at least a portion of the workload to the second device.
US 2018/0342039 issued to Kachare et al., teaches in one aspect of the present disclosure, a data storage and processing system is provided. The system includes a host server and a storage unit. The storage unit includes a drive comprising a memory and a drive processor, an external switch configured to couple the host server to the drive to send and receive data between the host server and the memory of the drive and a graphics processing unit. The drive processor is configured to send processing instructions and data from the drive memory to the graphics processing unit and the graphics processing unit is configured to process the data according to the processing instructions to generate result data.
US 10,073,640 issued to Klein teaches a plurality of open channel solid state drives (SSDs) are implemented over a network comprised of a network switch having a plurality of nodes, a remote host connected to a first node of the network switch, a metadata server connected to a second node of the network switch, and an abstracted memory structure comprised of at least part of one of the plurality of open channel SSDs. In one embodiment, the remote host is configured to communicate with the metadata server by issuing a command identifying data related to the abstracted memory structure. In another embodiment, the metadata server is configured to communicate with the remote host by responding to the command and identifying a physical address corresponding to the identified data.
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A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BACKHEAN TIV/
Primary Examiner, Art Unit 2459
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