DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 20 December 2024.
Claims 1-20 are pending and have been presented for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 18 January 2024. It is noted, however, that applicant has not filed a certified copy of the KR10-2024-0008273 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6-10 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over SONG (U.S. Patent Application Publication #2024/0143497) in view of WU (U.S. Patent Application Publication #2024/0070801).
1. SONG discloses A memory device comprising: a memory processor comprising a plurality of processing units (PUs) (see [0085]: MAC operators MAC0…MAC7; [0113]-[0113]: the MAC circuit includes logic circuits for performing multiplying, accumulative adding and addition processing on data stored in memory) and a processor controller configured to control the plurality of Pus (see [0087]: peripheral circuit that includes a control circuit for command/address signal; [0090]: the operation mode where the MAC operator will perform a MAC calculation comes from an outside command that the control circuit for command/address will process); and a memory controller configured to communicate with the processor controller and control first memory banks (see [0087]: control circuit for input/output of data), wherein the memory processor is configured to determine, based on a type of an operation performed by the memory processor, a read scheme (see [0086]: to perform a MAC operation, first data is read from one bank and second data is read from a second bank; [0082]: interleaving read operation; [0131]: simultaneous read from both banks) by which the memory controller reads second data stored in second memory banks of a host device into the first memory banks as first data for the memory processor (see WU below).
WU discloses the following limitations that are not disclosed by SONG: a read scheme by which the memory controller reads second data stored in second memory banks of a host device into the first memory banks as first data for the memory processor (see [0022]: MAC engine operates on data stored in SRAM, before the MAC operation the parameters are transferred from DRAM to SRAM; [0042]: data is transferred between DRAM and SRAM). SONG already discloses performing a data write operation for storing data to be used for a MAC arithmetic operation. WU discloses transferring data from DRAM to SRAM that will be used in a MAC operation. This would be considered a data write operation to store data to be used for a MAC operation. Therefore, the transfer of data disclosed by WU would be compatible with the system disclosed by SONG. This transfer allows the system to sequence and/or buffer data that will be needed before the function unit circuity begins to execute instructions on the data (see [0005]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SONG to determine a read scheme where data from second banks is transferred to first banks, as disclosed by WU. One of ordinary skill in the art would have been motivated to make such a modification to buffer and/or sequence data needed prior to starting execution, as taught by WU. SONG and WU are analogous/in the same field of endeavor as both references are directed to fetching data to perform MAC operations in a processing in memory system.
2. The memory device of claim 1, wherein the read scheme is one of: a first scheme of reading the second data stored in the second memory banks column-wise; a second scheme of reading the second data stored in the second memory banks row-wise (see WU [0043]: transfer an entire DRAM row to SRAM); and a third scheme of accessing and reading the second data stored in the second memory banks with different addresses simultaneously through interleaving (see SONG [0082]: operate memory banks using interleaving).
3. The memory device of claim 1, wherein the memory processor is configured to relocate the first data in the first memory banks to match the read scheme (see WU [0043]: data is relocated to the first banks [SRAM] row-wise).
4. The memory device of claim 1, wherein the memory processor is configured to: receive information for the operation from the host device (see SONG [0080]: receive external command from a host device; [0093]: command from host requesting a MAC operation); and store the information for the operation in a register of the processor controller (see [0093]: receiving driver stores the command received from the host).
6. The memory device of claim 1, wherein the memory processor is configured to determine, based on at least one of the type of the operation and throughputs of the plurality of PUs, whether to relocate the first data to the first memory banks and whether to reuse the second data read from the second memory banks (see WU [0058]: parameters for the neural network are stored in DRAM an transferred to SRAM, parameters are a type of data that would be reused).
7. The memory device of claim 1, wherein the memory processor is configured to relocate the first data in the first memory banks (see WU [0022]: data is relocated from DRAM to SRAM) or divide the first data according to throughputs of the plurality of PUs.
8. The memory device of claim 1, wherein the memory processor is configured to determine an address area for reading the second data in the second memory banks by considering the read scheme (see WU [0042]-[0043]: DRAM row is activated to transfer the data, the row has an address).
9. The memory device of claim 1, wherein the memory processor is configured to: store, in the first memory banks, the second data read from the second memory banks of the host device (see WU [0022]: data is relocated from DRAM to SRAM); and enable the plurality of PUs to perform an operation corresponding to the type of the operation by allocating the second data stored in the first memory banks to the plurality of PUs by the processor controller (see WU [0046]: data is streamed from the SRAM to the MAC to be used for processing).
10. The memory device of claim 9, wherein the memory processor further comprises a static random-access memory (SRAM) buffer (see WU [0032]: SRAM can be a cache, cache and buffer are equivalent), and the memory processor is configured to: store, in the SRAM buffer, an operation result obtained when the plurality of PUs performs the operation corresponding to the type of the operation (see WU [0082]: output from the neural network is stored in SRAM); and write the operation result stored in the SRAM buffer to the second memory banks (see SONG [0079]: MAC result data can be stored in the data storage region).
16. The memory device of claim 1, wherein the memory device is integrated into a mobile device, a mobile computing device, a mobile phone, a smartphone, a personal digital assistant (PDA), a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an entertainment unit, a navigation device, a communication device, a global positioning system (GPS) device, a television, a tuner, a satellite radio, a music player, a digital video player, a digital video disk (DVD) player, a vehicle, a component of the vehicle, an avionics system, a drone, a multicopter, or a medical device (see WU [0123]: implemented in various computing devices).
17. SONG discloses An operating method of a memory device, the operating method comprising: receiving, from a host device, information for an operation performed by a memory processor of the memory device (see [0080]: receive external command from a host device; [0093]: command from host requesting a MAC operation); determining, based on a type of the operation comprised in the information for the operation, a read scheme (see [0086]: to perform a MAC operation, first data is read from one bank and second data is read from a second bank; [0082]: interleaving read operation; [0131]: simultaneous read from both banks) by which a memory controller reads second data stored in second memory banks of the host device; reading the second data into first memory banks as first data to match the read scheme; performing an operation corresponding to the type of the operation by allocating the first data stored in the first memory banks to a plurality of processing units (PUs) by a processor controller; and writing an operation result obtained by performing the operation on the first memory banks (see WU below).
WU discloses the following limitations that are not disclosed by SONG: a read scheme by which a memory controller reads second data stored in second memory banks of the host device (see [0022]: MAC engine operates on data stored in SRAM, before the MAC operation the parameters are transferred from DRAM to SRAM; [0042]: data is transferred between DRAM and SRAM); reading the second data into first memory banks as first data to match the read scheme (see [0022]: MAC engine operates on data stored in SRAM, before the MAC operation the parameters are transferred from DRAM to SRAM; [0042]: data is transferred between DRAM and SRAM); performing an operation corresponding to the type of the operation by allocating the first data stored in the first memory banks to a plurality of processing units (PUs) by a processor controller (see [0046]: data is streamed from the SRAM to the MAC to be used for processing); and writing an operation result obtained by performing the operation on the first memory banks (see [0082]: output from the neural network is stored in SRAM). SONG already discloses performing a data write operation for storing data to be used for a MAC arithmetic operation. WU discloses transferring data from DRAM to SRAM that will be used in a MAC operation. This would be considered a data write operation to store data to be used for a MAC operation. Therefore, the transfer of data disclosed by WU would be compatible with the system disclosed by SONG. This transfer allows the system to sequence and/or buffer data that will be needed before the function unit circuity begins to execute instructions on the data (see [0005]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SONG to determine a read scheme where data from second banks is transferred to first banks, as disclosed by WU. One of ordinary skill in the art would have been motivated to make such a modification to buffer and/or sequence data needed prior to starting execution, as taught by WU. SONG and WU are analogous/in the same field of endeavor as both references are directed to fetching data to perform MAC operations in a processing in memory system.
18. The operating method of claim 17, wherein the determining of the read scheme comprises determining an address area for reading the second data from the second memory banks by considering the read scheme (see WU [0042]-[0043]: DRAM row is activated to transfer the data, the row has an address).
19. The operating method of claim 17, wherein the reading of the second data in the memory banks comprises relocating the first data for the memory processor to the first memory banks for the memory processor to match the read scheme (see WU [0022]: data is relocated from DRAM to SRAM).
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over SONG (U.S. Patent Application Publication #2024/0143497) and WU (U.S. Patent Application Publication #2024/0070801) as applied to claims 1-4, 6-10 and 16-19 above, and further in view of HORNUNG (U.S. Patent Application Publication #2023/0393970).
14. The memory device of claim 1 (see SONG above), wherein the memory processor is configured to receive a request for access to the first memory banks from the host device through an interface based on a compute express link (CXL) protocol or a peripheral component interconnect express (PCI-e) protocol (see HORNUNG below).
HORNUNG discloses the following limitations that are not disclosed by SONG: the memory processor is configured to receive a request for access to the first memory banks from the host device through an interface based on a compute express link (CXL) protocol or a peripheral component interconnect express (PCI-e) protocol (see [0015]-[0018]: CXL which runs on PCIe PHY). CXL facilitates high performance computational workloads (see [0015]) and can be used in compute-near-memory devices (see [0024]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SONG to utilize an interface based on CXL or PCI-e, as disclosed by HORNUNG. One of ordinary skill in the art would have been motivated to make such a modification to facilitate high performance computational workloads, as taught by HORNUNG. SONG and HORNUNG are analogous/in the same field of endeavor as both references are directed to compute-near-memory devices.
15. The memory device of claim 1 (see SONG above), wherein the memory processor is connected to the first memory banks through a device bus (see SONG [0126]: communication between MAC operator and memory bank over GIO line), and the memory controller is connected to the host device through a peripheral component interconnect express (PCI-e) interface (see HORNUNG below).
HORNUNG discloses the following limitations that are not disclosed by SONG: the memory controller is connected to the host device through a peripheral component interconnect express (PCI-e) interface (see [0015]-[0018]: CXL which runs on PCIe PHY). CXL facilitates high performance computational workloads (see [0015]) and can be used in compute-near-memory devices (see [0024]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SONG to utilize an interface based on CXL or PCI-e, as disclosed by HORNUNG. One of ordinary skill in the art would have been motivated to make such a modification to facilitate high performance computational workloads, as taught by HORNUNG. SONG and HORNUNG are analogous/in the same field of endeavor as both references are directed to compute-near-memory devices.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SONG (U.S. Patent Application Publication #2024/0143497) in view of WU (U.S. Patent Application Publication #2024/0070801) and KERSTETTER (U.S. Patent Application Publication #2025/0118386).
20. SONG discloses A non-transitory computer-readable storage medium storing instructions (see KERSTETTER below) that, when executed by a processor (see [0085]: MAP operator is a processor), causes the processor to perform the operating method of claim 17 (see claim 17 above).
KERSTETTER discloses the following limitations that are not disclosed by SONG: A non-transitory computer-readable storage medium storing instructions (see [0020]: microcode stored in non-volatile memory to perform PIM operations). Microcode is used to enable the circuitry to perform processor-in-memory operations. The use of microcode, stored in a memory, is one of a limited number of known solutions to have a processor perform specific operations. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SONG to include a non-transitory storage medium with instructions, as disclosed by KERSTETTER. One of ordinary skill in the art would have been motivated to make such a modification to enable the circuitry to perform the PIM operations, as taught by KERSTETTER. SONG and KERSTETTER are analogous/in the same field of endeavor as both references are directed to processor in memory systems.
Allowable Subject Matter
Claims 5 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The art of record fails to anticipate, or render obvious, “…wherein the information for the operation comprises: a dynamic random-access memory (DRAM) map comprising at least one of a number of rows of the second memory banks, a number of columns of the second memory banks, a number of the second memory banks, sizes of the second memory banks, and an offset; and processor register set information comprising at least one of information related to sizes of the first memory banks, a number of rows of the first memory banks, a number of columns of the first memory banks, a number of first memory banks, information indicating whether to relocate the first data, a direction in which the first data is stored in the first memory banks, and an operation type for the first data.”
The art of record fails to anticipate, or render obvious, “… the processor controller comprises: an instruction fetcher configured to fetch, from the host device, an instruction comprising information for an operation performed by the memory processor; and a data reformatter configured to relocate the first data to the first memory banks to match the read scheme corresponding to the type of the operation comprised in the instruction.”
The art of record fails to anticipate, or render obvious, “…row buffers respectively corresponding to the first memory banks, wherein the data reformatter is configured to copy the first data stored in a first area of the first memory banks to the row buffers and move the first data copied to the row buffers to a second area corresponding to a column or a row of another bank of the first memory banks to match the read scheme.”
The art of record fails to anticipate, or render obvious, “…a shared buffer shared among the first memory banks, wherein the data reformatter is configured to copy the first data stored in a first area of the first memory banks to the shared buffer and move the first data copied to the shared buffer to a second area corresponding to a column or a row of another bank of the first memory banks to match the read scheme.”
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MAI [2025/035561] discloses transferring data between banks of memory cells. [0029]
PAUL [2025/0156356] discloses the advantages of the CXL protocol. [0019]
CHOI [2025/0156309] discloses processing-in-memory devices.
AGA [2025/0110898] discloses reading elements from multiple banks that are fed into a processing-in-memory component. [0054]-[0056]
YUDANOV [2024/0070107] discloses a processing-in-memory component that operates on data in DRAM and SRAM. [0035]-[0044]
“DNA Mapping using Processor-in-Memory architecture”: discloses a processor in memory architecture with one processor for each 64 Mbytes of DRAM. See section II
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132