DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-11 are pending in this application.
Election/Restrictions
Applicant’s election without traverse of Species I directed to figs.1-3 and 14-16 in the reply filed on 08/13/2026 is acknowledged. Upon further consideration, claim 7 is directed to figures 22-29. Hence claim 7 is not examined at this time.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 12/20/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Applicant is reminded of the proper language and format for an abstract of the disclosure.
Reference numbers of the main technical features placed between parentheses.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Langguth (US 20230238454 A1).
Regarding claim 1, Langguth teaches a circuit device (abstract, a semiconductor device) comprising:
a first terminal (e.g. power supply terminal VDD, fig.4A);
a second terminal (e.g. power supply terminal VSS, fig.4A);
a thyristor circuit (e.g. circuit comprising 320, 322 and 324, fig.4A) provided between the first terminal and a first node (e.g. 320, 322, 324 are between VDD and node at the drain of 426, fig.4A);
a voltage hold circuit (e.g. circuit comprising NMOS transistor 426, fig.4A) provided between the first node and the second terminal (e.g. 426 is between drain of 426 and VSS, fig.4A);
a trigger transistor (e.g. transistor 330, fig.4A) configured to cause a trigger current to flow through the thyristor circuit ([0039], current supplied to the base-emitter junction of pnp transistor 320 triggers SCR 302, thereby allowing ESD current) ([0043], transistors 414, 426, as well as transistor 330, are turned on);
a predetermined capacitor (i.e. capacitor 336, fig.4A); and
a predetermined resistor (i.e. resistor 334, fig.4A).
In the embodiment of fig.4A, Langguth does not each the predetermined capacitor is provided between the first terminal and a gate of the trigger transistor; and
the predetermined resistor is provided between the gate of the trigger transistor and the second terminal.
In the embodiment of fig.5A, Langguth teaches a predetermined capacitor is provided between the first terminal and a gate of the trigger transistor (e.g. capacitor 504 is provided between VDD and gate of NMOS transistor 502, fig.5A); and
a predetermined resistor is provided between the gate of the trigger transistor and the second terminal (e.g. resistor 507 is provided between gate of 502 and VSS, fig.5A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the predetermined capacitor provided between the first terminal and a gate of the trigger transistor; and the predetermined resistor provided between the gate of the trigger transistor and the second terminal in fig.4A of Langguth, as taught by fig.5A of Langguth, as it provides the flexibility of using NMOS or PMOS type transistor as trigger transistor.
Regarding claim 6, Langguth teaches the circuit device according to claim 1, wherein the first terminal is one of a high-potential-side power supply terminal and a low-potential-side power supply terminal, and the second terminal is the other of the high-potential-side power supply terminal and the low-potential-side power supply terminal ([0021], the SCR can be turned on by applying a positive voltage between anode and cathode initiated by an avalanche breakdown) (it is necessarily true that VDD is positive voltage compared to VSS).
Regarding claim 10, Langguth teaches the circuit device according to claim 1, further comprising: a gate protection circuit provided between the gate of the trigger transistor and the second terminal ([0039], As long as the voltage across capacitor 336 is less than the threshold of inverter 332).
Regarding claim 11, Langguth teaches the circuit device according to claim 1, wherein the thyristor circuit includes an anode region of a second conductivity type that is provided at a first well of a first conductivity type and is electrically coupled to the first terminal (e.g. n+ region 212 connected to VDD, fig.4C), a cathode region of the first conductivity type that is provided at a second well of the second conductivity type and is electrically coupled to the second terminal (e.g. n+ region 208 connected to VSS, fig.4C), a first gate region of the first conductivity type that is provided at the first well and is electrically coupled to the first terminal via a first resistor having one end coupled to the first terminal (e.g. nw region 216 connected via resistor 324 to VDD, fig.4C), and a second gate region of the second conductivity type that is provided at the second well and is electrically coupled to the second terminal via a second resistor (e.g. pw region 214 connected via resistor to VSS, fig.4C), and the trigger transistor is provided between the other end of the first resistor in the thyristor circuit and the second terminal (e.g. transistor 456 between 324 and VSS, fig.4C).
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Langguth (US 20230238454 A1), and further in view of Xia (Ruirui Xia, Xiaowu Cai, Liqiang Ding, Chuanbin Zeng, Yuexin Gao, Mingzhu Li, Shiping Wang, Bo Li, Fazhan Zhao, Design of a NMOS-triggered SCR for dual-direction low-voltage ESD protection, Solid-State Electronics, Volume 190, 2022, 108250, ISSN 0038-1101, https://doi.org/10.1016/j.sse.2022.108250).
Regarding claim 3, Langguth teaches the circuit device according to claim 1.
Langguth does not teach, wherein the trigger transistor is a transistor having a DMOS structure.
Xia teaches in a similar field of endeavor of NMOS triggered SCR for ESD protection, a trigger transistor is a transistor having a DMOS structure (abstract, An improved NMOS triggered dual-direction silicon controlled rectifier (NMOS-DDSCR) device is fabricated in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the trigger transistor is a transistor having a DMOS structure in Langguth, as taught by Xia, as it provides the advantage of lower overshoot voltage, faster turn-on speed and sufficient latchup immunity.
Regarding claim 4, Langguth and Xia teach the circuit device according to claim 3, wherein the trigger transistor is a transistor having the DMOS structure of a first conductivity type (Xia, e.g. P-well of D, fig.2a) or a transistor having the DMOS structure of a second conductivity type, and an anode region of the thyristor circuit and a source region and a drain region of the DMOS structure of the second conductivity type are second conductivity type impurity diffusion regions of a same layer (Xia, e.g. N-well of SCR1 and SCR2, fig.2a).
Regarding claim 5, Langguth and Xia teach the circuit device according to claim 3, wherein a cathode region of the thyristor circuit and a region for setting a potential of a substrate of a transistor having the DMOS structure of a second conductivity type are a same second conductivity type impurity diffusion region (Xia, e.g. P+ region in N-well region of SCR1 and SCR2, and in P-well region of D, fig.2a).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Langguth (US 20230238454 A1), and further in view of Kumagai (CN 113571637 A).
Regarding claim 8, Langguth teaches the circuit device according to claim 1.
Langguth does not teach, wherein the capacitor is a MOM capacitor.
Kumagai teaches in a similar field of endeavor of circuit devices, a MOM capacitor (abstract, a MOM capacitor).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the capacitor as a MOM capacitor in Langguth, as taught by Kumagai, as it provides the advantage of reduced parasitic capacitance and noise inhibition.
Regarding claim 9, Langguth and Kumagai teach the circuit device according to claim 8, wherein the MOM capacitor includes a first electrode that is provided at a first metal layer and has a comb tooth shape in a plan view, and a second electrode that is provided at a second metal layer, faces the first electrode, and has a comb tooth shape in a plan view (abstract, he integrated upper and/or lower part of the multi-layer capacitor unit stacked in the MOM capacitor is set with a virtual electrode in a comb-shaped structure) (Kumagai, e.g. virtual electrodes 12 and 22, figs.1 and 2).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Langguth (US 20230238454 A1) teaches the circuit device according to claim 1.
Langguth does not teach, wherein the voltage hold circuit includes a plurality of hold elements coupled in series, and a coupling node between an n-th hold element and an (n + 1)-th hold element among the plurality of hold elements is coupled to the gate of the trigger transistor.
Prior art Chen (US 20040100746 A1), Van Wijmeersch (US 9042065 B2), Ikeda (US 20170244244 A1) and Van Wijmeersch (US 9882375 B2) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the voltage hold circuit includes a plurality of hold elements coupled in series, and a coupling node between an n-th hold element and an (n + 1)-th hold element among the plurality of hold elements is coupled to the gate of the trigger transistor.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
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/SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 09/21/2026
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