Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 6.
b. Claims 1-13 are pending on the application.
Drawings
2. The drawings were received on 12/20/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 12/20/2024. The information disclosed therein was considered.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “Disclosed” in page 1, line 3, which is implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (Pub. No.: US 2025/0086443 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Lee et al in Figures 1-9 are directly discloses a two-transistor (2T) DRAM cell (a two transistors cell 400, 500, Figs. 4-5) comprising:
a write transistor (a write transistor 410, Fig. 4) configured to transmit information of a bit line connected (write bit-line WBL 414, Fig. 4) to one terminal of the write transistor to a storage node (a storage node SN 402, Fig. 4) which is the other terminal of the write transistor in response to a signal of a write word line (a write word line WWL 412, Fig. 4) during a write operation (for example, the gate terminal 412 of the write transistor 410 is coupled to write word-line WWL and configured to receive a gate voltage VWWL and the first teriminal 414 of the write transistor 410 is coupled to a write bit-line WBL and configured to receive a write voltage (or a read voltage VWBL during the write operation, column 7, paragraph 0083); and
a read transistor (a read transistor 420, Fig. 4) comprising a main gate (a gate 422, Fig. 4) that is activated in response to a voltage of the storage node (a storage node SN 402, Fig. 4) and an off gate that is formed at a place that comes into contact with the main gate (the gate 422) and that is activated in response to a voltage of a source line (a read word line RWL 426, Fig. 4) and configured to transmit a voltage corresponding to the voltage of the storage node to the bit line (a read bit-line RBL 424, Fig. 4) during a read operation (for example, the read transistor 420 includes a charge storage layer 423 at the gate terminal 422 for changing a threshold voltage of the read transistor 420. The threshold voltage of the read transistor 420 can be changed based on a value of the applied high voltage and a time period of applying the voltage on the gate terminal 422, see column 7, paragraph 0084-0086 and the related disclosures).
Regarding dependent claim 2, Lee et al in Figures 1-9 are directly discloses a two-transistor (2T) DRAM cell (a two transistors cell 400, 500, Figs. 4-5) comprising: the read transistor (the read transistor 420) has one terminal connected to the bit line (a read bit-line RBL 424) and the other terminal connected to the source line (a read word line RWL 426), a terminal of the off gate (the gate 422) is connected to the source line (the gate 422 coupled to the read word-line RWL), and a terminal of the main gate (the gate 422) is connected to the storage node (the storage node SN402)(the gate 422 coupled to the storage node SN 402, Fig. 4).
Allowable Subject Matter
6. Claims 3-5 and 9-12, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 3-4, the prior art fails to tech or suggest the claimed limitations, namely, the 2T DRAM cell, wherein during the read operation, a second channel that is formed by the off gate is activated, and a first channel that is formed by the main gate is activated or inactive based on an information stored in the storage node, wherein: in the state in which the second channel has been activated, the value stored in the storage node is a logic high when the first channel is activated, and in the state in which the second channel has been activated, the value stored in the storage node is a logic low when the first channel is not activated.
With respected to dependent claim 5, the prior art fails to tech or suggest the claimed limitations, namely, the plurality of 2T DRAM cells in which a plurality of bit lines, a plurality of source lines, and a plurality of write word lines are connected, wherein one terminal of a write transistor and one terminal of a read transistor are connected to a corresponding bit line, among the plurality of bit lines, in common, a gate terminal of the write transistor is connected to a corresponding write word line, among the plurality of write word lines, and the main gate of the read transistor is connected to the other terminal of the write transistor, and the off gate of the read transistor is connected to the source line.
With respected to dependent claim 9, the prior art fails to tech or suggest the claimed limitations, namely, the 2T DRAM cell is implemented to have an inner gate structure, and the off gate of the read transistor is formed under an electrode material with an offset which is an off gate region when a trench corresponding to a storage node having the inner gate structure is filled with the electrode material.
With respected to dependent claims 10-11, the prior art fails to tech or suggest the claimed limitations, namely, the 2T DRAM cell is implemented to have a planar transistor structure, and when the read transistor is formed, an electrode corresponding to the off gate is formed independently of the main gate, when the read transistor is formed, the off gate is formed by forming an insulator in a region corresponding to an off gate region.
With respected to dependent claim 12, the prior art fails to tech or suggest the claimed limitations, namely, the write transistor has a planar structure, and the read transistor has a vertical structure.
7. Claims 6-8 and 13 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 6: there is no teaching, suggestion, or motivation for combination in the prior art to the steps of “an information read step of detecting and amplifying information stored in the DRAM cell to which the refresh pulse signal has been applied; a step of activating a write word line connected to the DRAM cell; and a step of confirming information to be refreshed based on a voltage level of a bit line connected to the DRAM cell and restoring the information to be refreshed to information in the DRAM cell by applying a voltage corresponding to the information to be refreshed to the bit line.” in a method of refreshing a two transistor dram cell as claimed in the independent claim 6. Claims 7-8 and 13 are also allowed because of their dependency on claim 6.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ling (US. 2025/0008720 A1) discloses semiconductor storage cell structure and manufacturing method thereof.
Zhu et al (US. 2024/0412778 A1) discloses memory cell, array read-write method, control chip memory and electronic device.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights