DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. 20160092363 herein Wang.
Per claim 1, Wang discloses: a shared last level cache coupled to multiple clients and a dynamic random access memory; (fig. 1 ¶0022&0023; processor 110 may be a single die processor including multiple tiles 120.sub.a-120.sub.n. Each tile includes a processor core and an associated private cache memory hierarchy that, in some embodiments is a three-level hierarchy with a low level cache, a MLC and an LLC. In addition, each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual tile) a linear dropout regulator that supplies power to the shared last level cache;(¶0023; Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual tile) and a data fabric that controls a level of the power supplied from the linear dropout regulator based on usage of the shared last level cache (¶0022& ¶0081; a processor 110 which as shown is a multicore processor. Processor 110 may be coupled to a power supply 150 via an external voltage regulator 160, which may perform a first voltage conversion to provide a primary regulated voltage to processor 110).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-7 and 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. 20160092363 herein Wang and Ramani et al 20150268711 herein Ramani.
Per claim 2, Wang discloses: wherein the data fabric is configured to control the level of the power supplied from the linear dropout regulator to be either a first level that enables at least one active client to use the shared last level cache or a second level to keep the shared last level cache in a ready state when the at least one active client does not use the shared last level cache (¶0048; Note that this threshold may be a value above zero. That is, even if MLC is generating misses, but the misses are generated at a very slow pace, it may be more beneficial to power gate the LLC and let those misses be serviced by a further portion of a memory hierarchy instead of keeping the LLC consuming on and leakage power to service such a slow request rate. In some embodiments, this threshold (th_MPKI) may depend on the LLC leakage and the dynamic power difference between fetching data from the LLC as compared to fetching data from memory).
Wang does not specifically disclose: maintaining a status record indicating each of the multiple clients that is sharing access to the shared last level cache.
However, Ramani discloses: maintaining a status record indicating each of the multiple clients that is sharing access to the shared last level cache (¶0049; based on cache utilization statistics (such as the above counts of cache line states), it can be determined how much a core is relying on the cache memory for performance, and in a situation where high reliance is present, a flush may be avoided, e.g., by not entering into a low power state that does not provide a retention voltage. For this analysis, instead of comparing a break even residency with a time until a next event, a core cache utilization (e.g., measured using a number of cache lines (and optionally of particular cache coherency states) used by a give core) can be compared to a cache performance threshold. If it is determined that the utilization exceeds this threshold, a flush may be prevented, and the processor may be controlled to enter a low power state in which a retention voltage is provided to the cache memory (such that a flush does not occur); the examiner notes that the maintaining a record is akin to the utilization statistics).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Wang and Ramani’s processor status to maintain the appropriate level of supply voltage in the cache for the processor in the system Ramani’s power management optimizes low power state selection and cache flushing (¶0013).
Per claim 3, Wang discloses: a side-band connection between the linear dropout regulator and the data fabric, (fig. 1) wherein the data fabric controls the level of the power supplied from the linear dropout regulator by sending a signal over the side-band connection to cause the linear dropout regulator to supply power for the shared last level cache at either the first level or the second level (¶0023; each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage (first level or second level) and thus power and performance of each individual tile.¶0025; PCU 138 may include logic to perform adaptive local LLC power control in accordance with an embodiment of the present invention. Furthermore, PCU 138 may be coupled via a dedicated interface to external voltage regulator 160. In this way, PCU 138 can instruct the voltage regulator to provide a requested regulated voltage to the processor. ¶0032; circuit 275 includes various components that provide information regarding processor activities to a cache power management logic 290 that in turn generates a decision as to power control of an LLC.).
Per claim 4, Wang discloses: wherein the first level comprises a normal voltage level and the second level comprises a retention voltage level that is less than the normal voltage level (¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0059; the association of cores with a given cluster may change dynamically. Also, depending on the activity of the cores, one or more of the corresponding clusters 620 may be placed into a low power state to reduce power consumption as described above.).
Wang does not specifically disclose: wherein the retention voltage level configures the shared last level cache to maintain at least one of fuse distributions, cache content, or parameters within the shared last level cache, and wherein the retention voltage level is not sufficient to enable use of the shared last level cache.
However Ramani discloses: wherein the retention voltage level configures the shared last level cache to maintain at least one of fuse distributions, cache content, or parameters within the shared last level cache, and wherein the retention voltage level is not sufficient to enable use of the shared last level cache (¶0049; based on cache utilization statistics (such as the above counts of cache line states), it can be determined how much a core is relying on the cache memory for performance, and in a situation where high reliance is present, a flush may be avoided, e.g., by not entering into a low power state that does not provide a retention voltage. For this analysis, instead of comparing a break even residency with a time until a next event, a core cache utilization (e.g., measured using a number of cache lines (and optionally of particular cache coherency states) used by a give core) can be compared to a cache performance threshold. If it is determined that the utilization exceeds this threshold, a flush may be prevented, and the processor may be controlled to enter a low power state in which a retention voltage is provided to the cache memory; the examiner notes that the claim merely requires a first and second voltage level wherein the level is kept to maintain the retention voltage or not. The rest of the claim are the intended result of maintain the level or not).
Per claim 5, Wang discloses: at least one processor configured to execute power management firmware that: turns the linear dropout regulator on to supply the power at the first level to initialize the shared last level cache and enable the at least one active client to use the shared last level cache; and turns the linear dropout regulator off to supply the power at a third level that is lower than the second level when none of the multiple clients is active (¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0059; the association of cores with a given cluster may change dynamically. Also, depending on the activity of the cores, one or more of the corresponding clusters 620 may be placed into a low power state to reduce power consumption as described above.; the examiner notes that the different levels is a result of power management).
Wang does not specifically disclose: maintains a client record of each of the multiple clients that have access to the shared last level cache.
However Ramani discloses: maintains a client record of each of the multiple clients that have access to the shared last level cache; (¶0049; based on cache utilization statistics (such as the above counts of cache line states), it can be determined how much a core is relying on the cache memory for performance, and in a situation where high reliance is present, a flush may be avoided, e.g., by not entering into a low power state that does not provide a retention voltage. For this analysis, instead of comparing a break even residency with a time until a next event, a core cache utilization (e.g., measured using a number of cache lines (and optionally of particular cache coherency states) used by a give core) can be compared to a cache performance threshold. If it is determined that the utilization exceeds this threshold, a flush may be prevented, and the processor may be controlled to enter a low power state in which a retention voltage is provided to the cache memory; the examiner notes that the maintaining a record is akin to the utilization statistics identifying the core cache utilization).
Per claim 6, Wang discloses: wherein the third level comprises an approximately zero-voltage level (¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0059; the association of cores with a given cluster may change dynamically. Also, depending on the activity of the cores, one or more of the corresponding clusters 620 may be placed into a low power state to reduce power consumption as described above.; the examiner notes that the different levels is a result of power management).
Per claim 7, Wang discloses: wherein the system is configured to operate in at least three different states, wherein: during a first state, the power management firmware causes the shared last level cache to be powered-off; during a second state, the power management firmware causes the shared last level cache to be powered-on; and configure the shared last level cache to operate in retention mode wherein, based on the power supplied for the shared last level cache at the second level, the shared last level cache remains initialized during the retention mode and ready to handle future accesses upon later transitioning back to the second state (¶0023; each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage (first level or second level) and thus power and performance of each individual tile.¶0025; PCU 138 may include logic to perform adaptive local LLC power control in accordance with an embodiment of the present invention. Furthermore, PCU 138 may be coupled via a dedicated interface to external voltage regulator 160. In this way, PCU 138 can instruct the voltage regulator to provide a requested regulated voltage to the processor. ¶0032; circuit 275 includes various components that provide information regarding processor activities to a cache power management logic 290 that in turn generates a decision as to power control of an LLC.¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0059; the association of cores with a given cluster may change dynamically. Also, depending on the activity of the cores, one or more of the corresponding clusters 620 may be placed into a low power state to reduce power consumption as described above.; the examiner notes that the different levels is a result of power management).
Wang does not specifically disclose: and during a third state, the data fabric controls the linear dropout regulator using a side- band connection between the linear dropout regulator and the data fabric to: supply power via the linear dropout regulator for the shared last level cache at the second level.
However, Ramani discloses: and during a third state, the data fabric controls the linear dropout regulator using a side- band connection between the linear dropout regulator and the data fabric to: supply power via the linear dropout regulator for the shared last level cache at the second level; (¶0049; based on cache utilization statistics (such as the above counts of cache line states), it can be determined how much a core is relying on the cache memory for performance, and in a situation where high reliance is present, a flush may be avoided, e.g., by not entering into a low power state that does not provide a retention voltage. For this analysis, instead of comparing a break even residency with a time until a next event, a core cache utilization (e.g., measured using a number of cache lines (and optionally of particular cache coherency states) used by a give core) can be compared to a cache performance threshold. If it is determined that the utilization exceeds this threshold, a flush may be prevented, and the processor may be controlled to enter a low power state in which a retention voltage is provided to the cache memory).
Per claim 12, Wang discloses: wherein when none of the multiple clients is active the system transitions from the second state to the first state or from the third state to the second state to the third state (¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0049; a decision may be made as to whether an LLC slice should be power gated when an associated core or cluster of cores enters into a given low power state. Independently, MLC utilization may be monitored to determine whether the LLC can be power gated even when the core is running).
Per claim 13, Wang discloses: wherein the multiple clients include a central processing unit, wherein the system further comprises a main cache internal to the central processing unit, and the shared last level cache is coupled to the main cache and the dynamic random access memory (¶0030; Core 210 may couple to a first level cache 220 that may be a relatively small cache memory closely associated with the core. In turn, cache 220 is coupled to a mid-level cache (MLC) 230 that may include greater storage capacity. In turn, MLC 230 is coupled to a further portion of a cache hierarchy, namely a last level cache (LLC) 240 that may include even greater amounts of storage capacity; ¶0031; Also understand that this tile-included cache hierarchy includes slices or portions of a shared cache implemented with LLC 240 of a larger cache memory structure).
Per claim 14, Wang discloses: route memory accesses by multiple active clients to a shared last level cache or a dynamic random access memory of a system; and control a level of power supplied to the shared last level cache (¶0032; circuit 275 includes various components that provide information regarding processor activities to a cache power management logic 290 that in turn generates a decision as to power control of an LLC.¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not.) switch a level of power supplied to a shared last level cache to be at a first level that enables multiple active clients to use the shared last level cache; switch the level of power to be at a second level that keeps the shared last level cache in a ready state when each of the active clients is idle with respect to use of the shared last level cache; and switch the level of power to be at the first level when at least one of the active clients is no longer idle with respect to use of the shared last level cache (¶0023; each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage (first level or second level) and thus power and performance of each individual tile.¶0025; PCU 138 may include logic to perform adaptive local LLC power control in accordance with an embodiment of the present invention. Furthermore, PCU 138 may be coupled via a dedicated interface to external voltage regulator 160. In this way, PCU 138 can instruct the voltage regulator to provide a requested regulated voltage to the processor. ¶0032; circuit 275 includes various components that provide information regarding processor activities to a cache power management logic 290 that in turn generates a decision as to power control of an LLC.¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0059; the association of cores with a given cluster may change dynamically. Also, depending on the activity of the cores, one or more of the corresponding clusters 620 may be placed into a low power state to reduce power consumption as described above.; the examiner notes that the different levels is a result of power management).
Per claim 15, Wang discloses: enabling, by a data fabric of a system, an active client to fulfill accesses using a shared last level cache instead of a dynamic random access memory; (fig. 1 ¶0022&0023; processor 110 may be a single die processor including multiple tiles 120.sub.a-120.sub.n. Each tile includes a processor core and an associated private cache memory hierarchy that, in some embodiments is a three-level hierarchy with a low level cache, a MLC and an LLC. In addition, each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual tile) controlling, by the data fabric, a linear dropout regulator to switch a level of power supplied to the shared last level cache to be at a first level; (¶0023; Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual tile) and based on the active client being idle with respect to use of the shared last level cache; and controlling, by the data fabric, the linear dropout regulator to switch the level of power to be at a second level when the active client is no longer idle with respect to use of the shared last level cache (¶0022& ¶0081; a processor 110 which as shown is a multicore processor. Processor 110 may be coupled to a power supply 150 via an external voltage regulator 160, which may perform a first voltage conversion to provide a primary regulated voltage to processor 110; ¶0048; Note that this threshold may be a value above zero. That is, even if MLC is generating misses, but the misses are generated at a very slow pace, it may be more beneficial to power gate the LLC and let those misses be serviced by a further portion of a memory hierarchy instead of keeping the LLC consuming on and leakage power to service such a slow request rate. In some embodiments, this threshold (th_MPKI) may depend on the LLC leakage and the dynamic power difference between fetching data from the LLC as compared to fetching data from memory).
Per claim 16, Wang discloses: executing, by a processor of the system, power management firmware to identify a workload of the active client that benefits from access to the shared last level cache instead of the dynamic random access memory; and communicating the active client to the data fabric to cause the data fabric to enable the active client to fulfill accesses at the shared last level cache (¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0059; the association of cores with a given cluster may change dynamically. Also, depending on the activity of the cores, one or more of the corresponding clusters 620 may be placed into a low power state to reduce power consumption as described above.; the examiner notes that the different levels is a result of power management).
Wang does not specifically disclose: wherein the power management firmware maintains a client record of the active client and communicates to the data fabric whether the active client is active and whether the shared last level cache is usable by the active client.
However, Ramani discloses: wherein the power management firmware maintains a client record of the active client and communicates to the data fabric whether the active client is active and whether the shared last level cache is usable by the active client (¶0049; based on cache utilization statistics (such as the above counts of cache line states), it can be determined how much a core is relying on the cache memory for performance, and in a situation where high reliance is present, a flush may be avoided, e.g., by not entering into a low power state that does not provide a retention voltage. For this analysis, instead of comparing a break even residency with a time until a next event, a core cache utilization (e.g., measured using a number of cache lines (and optionally of particular cache coherency states) used by a give core) can be compared to a cache performance threshold. If it is determined that the utilization exceeds this threshold, a flush may be prevented, and the processor may be controlled to enter a low power state in which a retention voltage is provided to the cache memory (such that a flush does not occur); the examiner notes that the maintaining a record is akin to the utilization statistics).
Per claim 17, Wang discloses: controlling, via the power management firmware, the linear dropout regulator to switch the level of the power supplied to the shared last level cache to be at a third level that is lower than the second level to power off the shared last level cache when no active clients are available to use the shared last level cache; and controlling, via the power management firmware, the linear dropout regulator to switch the level of the power supplied to the shared last level cache to transition from the third level to the first level for enabling the active client to use the shared last level cache (¶0023; each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage (first level or second level) and thus power and performance of each individual tile.¶0025; PCU 138 may include logic to perform adaptive local LLC power control in accordance with an embodiment of the present invention. Furthermore, PCU 138 may be coupled via a dedicated interface to external voltage regulator 160. In this way, PCU 138 can instruct the voltage regulator to provide a requested regulated voltage to the processor. ¶0032; circuit 275 includes various components that provide information regarding processor activities to a cache power management logic 290 that in turn generates a decision as to power control of an LLC.¶0048; A still further exemplary technique for power management is to power gate a LLC based on a measurement of MLC utilization to determine whether the LLC is needed or not. ¶0059; the association of cores with a given cluster may change dynamically. Also, depending on the activity of the cores, one or more of the corresponding clusters 620 may be placed into a low power state to reduce power consumption as described above.; the examiner notes that the different levels is a result of power management).
Per claim 18, Wang discloses: wherein controlling the linear dropout regulator by the data fabric comprises: sending, by the data fabric, a signal over a side-band connection between the linear dropout regulator and the data fabric, (fig. 1) whether the linear dropout regulator is to supply power at the first level or the second level (¶0023; each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage (first level or second level) and thus power and performance of each individual tile.¶0025; PCU 138 may include logic to perform adaptive local LLC power control in accordance with an embodiment of the present invention. Furthermore, PCU 138 may be coupled via a dedicated interface to external voltage regulator 160. In this way, PCU 138 can instruct the voltage regulator to provide a requested regulated voltage to the processor. ¶0032; circuit 275 includes various components that provide information regarding processor activities to a cache power management logic 290 that in turn generates a decision as to power control of an LLC.).
Claim(s) 8, 10-11 and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. 20160092363 herein Wang and Ramani in view of Lilly et al. 20140195737 herein Lilly.
Per claim 8, Wang discloses dynamic power regulation but does not specifically disclose: wherein the system transitions from the first state to the second state when at least one of the multiple clients becomes active and the system transitions from the second state to the third state during an idle period of the data fabric when the at least one active client is not using the shared last level cache.
However, Lilly discloses: wherein the system transitions from the first state to the second state when at least one of the multiple clients becomes active and the system transitions from the second state to the third state during an idle period of the data fabric when the at least one active client is not using the shared last level cache (fig. 4B, ¶0073; At block 455, the second cache is put into a low-power state. In some embodiments, the second cache is shared between multiple processor cores. The second cache may be put into the low-power state based on a determination that all cores associated with the second cache are in a low-power state. The second cache may be brought out of the low-power state based on a determination that one or more processing elements associated with the second cache is no longer in a low-power state. Flow ends at block 455).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teaching of Wang, Ramani and Lilly’s cache power states to conserve power. Lilly reduces power consumption (¶0005; This may reduce power consumption compared to software flushing implementations.)
Per claim 10, Lilly discloses: wherein after transitioning to the third state the shared last level cache maintains cache content stored in the shared last level cache during the second state (fig. 4B, ¶0072-73; At block 455, the second cache is put into a low-power state. In some embodiments, the second cache is shared between multiple processor cores. The second cache may be put into the low-power state based on a determination that all cores associated with the second cache are in a low-power state. The second cache may be brought out of the low-power state based on a determination that one or more processing elements associated with the second cache is no longer in a low-power state. Flow ends at block 455) using the linear dropout regulator to supply the power at the second level for serving the cache content following transitions from the third state back to the second state (Wang: ¶0023; each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage (first level or second level) and thus power and performance of each individual tile.¶0025; PCU 138 may include logic to perform adaptive local LLC power control in accordance with an embodiment of the present invention.).
Per claim 11, Lilly discloses: wherein after transitioning to the third state the shared last level cache maintains fuse distributions previously established for the shared last level cache during the second state (fig. 4B, ¶0072-73; At block 455, the second cache is put into a low-power state. In some embodiments, the second cache is shared between multiple processor cores. The second cache may be put into the low-power state based on a determination that all cores associated with the second cache are in a low-power state. The second cache may be brought out of the low-power state based on a determination that one or more processing elements associated with the second cache is no longer in a low-power state. Flow ends at block 455) using the linear dropout regulator to supply the power at the second level for maintaining the fuse distributions following transitions from the third state back to the second state (Wang: ¶0023; each tile may be associated with an individual voltage regulator 125.sub.a-125.sub.n. Accordingly, a fully integrated voltage regulator (FIVR) implementation may be provided to allow for fine-grained control of voltage (first level or second level) and thus power and performance of each individual tile.¶0025; PCU 138 may include logic to perform adaptive local LLC power control in accordance with an embodiment of the present invention.).
Per claim 19, Lilly discloses: wherein controlling the linear dropout regulator to switch the level of power to be at the second level comprises maintaining cache content in the shared last level cache (fig. 4B, ¶0072-73; At block 455, the second cache is put into a low-power state. In some embodiments, the second cache is shared between multiple processor cores. The second cache may be put into the low-power state based on a determination that all cores associated with the second cache are in a low-power state. The second cache may be brought out of the low-power state based on a determination that one or more processing elements associated with the second cache is no longer in a low-power state. Flow ends at block 455).
Wang does not specifically disclose: by supplying a retention voltage from the linear dropout regulator to the shared last level cache via a voltage plane, the retention voltage being less than a normal voltage supplied via the voltage plane when the active client is not idle.
However, Ramani discloses: by supplying a retention voltage from the linear dropout regulator to the shared last level cache via a voltage plane, the retention voltage being less than a normal voltage supplied via the voltage plane when the active client is not idle (¶0049; based on cache utilization statistics (such as the above counts of cache line states), it can be determined how much a core is relying on the cache memory for performance, and in a situation where high reliance is present, a flush may be avoided, e.g., by not entering into a low power state that does not provide a retention voltage. For this analysis, instead of comparing a break even residency with a time until a next event, a core cache utilization (e.g., measured using a number of cache lines (and optionally of particular cache coherency states) used by a give core) can be compared to a cache performance threshold. If it is determined that the utilization exceeds this threshold, a flush may be prevented, and the processor may be controlled to enter a low power state in which a retention voltage is provided to the cache memory (such that a flush does not occur); the examiner notes that the maintaining a record is akin to the utilization statistics).
Per claim 20, Lilly discloses: controlling, by the data fabric, the linear dropout regulator to switch the level of power to be at the second level for maintaining the cache content and fuse distributions previously established for the shared last level cache (fig. 4B, ¶0072-73; At block 455, the second cache is put into a low-power state. In some embodiments, the second cache is shared between multiple processor cores. The second cache may be put into the low-power state based on a determination that all cores associated with the second cache are in a low-power state. The second cache may be brought out of the low-power state based on a determination that one or more processing elements associated with the second cache is no longer in a low-power state. Flow ends at block 455).
Per claim 21, Ramani discloses: wherein the fuse distributions and the cache content are preserved based on the retention voltage for avoiding reinitialization of the shared last level cache when the level of power switches back to the first level (¶0049; based on cache utilization statistics (such as the above counts of cache line states), it can be determined how much a core is relying on the cache memory for performance, and in a situation where high reliance is present, a flush may be avoided, e.g., by not entering into a low power state that does not provide a retention voltage. For this analysis, instead of comparing a break even residency with a time until a next event, a core cache utilization (e.g., measured using a number of cache lines (and optionally of particular cache coherency states) used by a give core) can be compared to a cache performance threshold. If it is determined that the utilization exceeds this threshold, a flush may be prevented, and the processor may be controlled to enter a low power state in which a retention voltage is provided to the cache memory (such that a flush does not occur).
Response to Arguments
Applicant's arguments filed 4/28/26 have been fully considered but they are not persuasive.
The applicant argues: Wang does not disclose "a data fabric" or "a linear dropout regulator." Wang discloses "a power control unit (PCU) 138" that includes "hardware, software and/or firmware to perform power management operations" and that "can instruct the voltage regulator to provide a requested regulated voltage to the processor." Wang, paragraph [0025]. Wang discloses "a fully integrated voltage regulator (FIVR) implementation" and "an external voltage regulator 160." Wang, paragraphs [0022] and [0023]. Wang does not disclose "a data fabric" that controls "a linear dropout regulator to switch a level of power supplied to the shared last level cache" "based on the active client being idle with respect to use of the shared last level cache," as recited by amended claim 15. Accordingly, Applicant respectfully requests that the 35 U.S.C. § 102 rejection of claim 15 be withdrawn.
The examiner respectfully disagrees and asserts that the claim language merely requires an interface (fabric) and a linear voltage regulator wherein the data fabric controls the linear voltage regulator. The examiner notes that Wang clearly discloses in fig. 1 and its corresponding description a data fabric (PCU which comprises hardware, software and firmware to interface the VR to the FIVR). The fabric is merely an interfacing element as described by the claims and applicant’s specification (¶0041). Further, the FIVR by definition refers to any regulation circuitry built on the chip/core, which can use either linear or switching topologies. Therefore Wang teaches a linear voltage regulator as claimed. Fig. 1 ¶0023 and ¶0025 clearly discloses the relationship between he VR PCU and FIVR as claimed. Therefore, Wang discloses “controlling, by the data fabric, a linear dropout regulator to switch a level of power supplied to the shared last level cache…”
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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