DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 12/20/2024.
The Examiner acknowledges the preliminary amendments made to the claims filed 01/16/2025.
Claims 1-20 have been cancelled.
Claims 21-40 have been added.
Claims 21-40 are pending.
Claims 21-28 and 30-40 are rejected.
Claim 29 is objected to.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the rejections provided herein which must be addressed accordingly.
Priority
Applicant’s priority claims as a continuation of US Application 17/978,415, now US Patent No. 12,216,916, filed 11/01/2022 which further claims foreign priority to KR10-2022-0012595 filed 01/27/2022 and KR10-2021-0154270 filed 11/10/2021 is herein acknowledged.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 12/20/2024 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 12/20/2024 are acceptable for examination purposes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 30 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 30 recites “wherein the storage device includes a plurality of cores”. Claim 28, from which claim 30 depends, recites “an operating method of a storage device including a storage controller and a non-volatile memory, the storage controller including a plurality of cores”. Therefore, claim 30, lacks proper antecedent basis regarding the term “plurality of cores”. It is suggested to either remove the language from claim 30 as it appears redundant or to amend the language to establish either antecedent basis with claim 28 or distinction from claim 28.
Appropriate corrections are required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-28 and 30-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,216,916, hereinafter referred to as “Patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are of a broader recitation of those in the US Patent as demonstrated by the comparison below. In this manner, it may be considered that the claims of the US Patent may anticipate the claims of the instant application as they are of narrower scope.
Instant Application
US Patent 12,216,916
A storage device comprising: a non-volatile memory; and a storage controller including a plurality of cores, the storage controller configured to communicate with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of a direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the storage controller configured to communicate with the non-volatile memory by, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation, and in response to a power being cut off to the storage device and the fault being detected in the performance path, transmitting recovery data to the non-volatile memory through the at least one direct path, wherein the recovery data is data required to recover the storage device when the power is restored after the power is cut off.
A storage device comprising: a non-volatile memory including a plurality of memory regions; and a storage controller including a plurality of cores and a buffer memory configured to store recovery data, the storage controller configured to communicate with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the storage controller configured to communicate with the non-volatile memory by, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation, detecting whether a fault is present in performance of the performance path, in response to a power being cut-off to the storage device, and in response to the fault being detected as present in the performance path while the power remains cut-off, moving the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory through the at least one direct path, wherein the performance path is for performing the write operation, the read operation, and the erase operation, and wherein the at least one direct path is for performing only the write operation.
The storage device of claim 21, wherein the storage controller is configured to determine the performance path as having the fault in response to at least one of write operations of writing first to n-th data of the recovery data to the non-volatile memory not being completed within a first time.
The storage device of claim 1, wherein the plurality of cores includes a first core configured to perform an operation related to an interface with a host, and a second core configured to perform an operation related to an interface with the non-volatile memory, the first core and the second core being included in the performance path, and in response to the fault being detected as present in the performance path while the power remains cut-off, the storage controller is configured to select one of the plurality of cores as a selected core and move the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory via a corresponding one of the plurality of direct paths.
The storage device of claim 21, wherein the storage controller is configured to transmit an error signal to a host as a response corresponding to user data and marks a data defect on user data in response to at least a portion of the user data not being written to the non-volatile memory due to power off.
The storage device of claim 2, wherein the at least one direct path includes a first direct path and a second direct path, the first core is configured to write the recovery data to a first memory region, among the plurality of memory regions, through the first direct path, and the second core is configured to write the recovery data to a second memory region, among the plurality of memory regions, through the second direct path.
The storage device of claim 21, wherein the recovery data includes user data, debug data, user data digest, device metadata, and map data.
The storage device of claim 1, wherein the storage controller includes: a plurality of first cores configured to perform an operation related to an interface with a host; and a plurality of second cores configured to perform an operation related to an interface with the non-volatile memory, the performance path includes the plurality of first cores and the plurality of second cores, and in response to the power being cut off and the fault being detected in the performance path, each of the first cores is configured to write the recovery data to the non-volatile memory through the at least one direct path.
The storage device of claim 21, wherein the performance path is for performing the write operation, the read operation, and the erase operation, and wherein the at least one direct path is for performing only the write operation.
The storage device of claim 1, wherein the storage controller includes first to third cores sequentially included in the performance path, and in response to the power being cut off and the fault being detected in the performance path, each of the first and second cores is configured to write the recovery data to the non-volatile memory through the at least one direct path.
The storage device of claim 21, wherein the plurality of cores includes a first core configured to perform an operation related to an interface with a host, and a second core configured to perform an operation related to an interface with the non-volatile memory, the first core and the second core being included in the performance path, the at least one direct path includes a first direct path and a second direct path, the first core is configured to write the recovery data to a first memory region, included in the non-volatile memory, through the first direct path, and the second core is configured to write the recovery data to a second memory region included in the non-volatile memory, through the second direct path.
The storage device of claim 5, wherein the at least one direct path includes a first direct path, a second direct path and a third direct path, the first core is configured to write the recovery data to a first memory region, among the plurality of memory regions, through the first direct path, and the third core is configured to write the recovery data in a second memory region, among the plurality of memory regions, through the third direct path.
The storage device of claim 21, wherein the storage controller includes: a plurality of first cores configured to perform an operation related to an interface with a host; and a plurality of second cores configured to perform an operation related to an interface with the non-volatile memory, the performance path includes the plurality of first cores and the plurality of second cores, and in response to the power being cut off and the fault being detected in the performance path, each of the first cores is configured to write the recovery data to the non-volatile memory through the at least one direct path.
The storage device of claim 1, wherein the recovery data includes user data, debug data, user data digest, device metadata, and map data.
An operating method of a storage device including a storage controller and a non-volatile memory, the storage controller including a plurality of cores, the operating method comprising: communicating with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the communicating including, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation, and in response to a power being cut off to the storage device and the fault being detected in the performance path, selecting one of the plurality of cores as a selected core, and writing the recovery data to the non-volatile memory through the direct path corresponding to the selected core, wherein the recovery data is data required to recover the storage device when the power is restored after the power is cut off.
An operating method of a storage device including a storage controller and a non-volatile memory, the storage controller including a plurality of cores and a buffer memory configured to store recovery data, the operating method comprising: communicating with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the communicating including, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation, detecting whether a fault is present in performance of the performance path, in response to a power being cut-off to the storage device, in response to the fault being detected as present in the performance path while the power remains cut-off, selecting one of the plurality of cores as a selected core and collecting recovery data written in the buffer memory, and moving the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory through the direct path corresponding to the selected core, wherein the performance path is for performing the write operation, the read operation, and the erase operation, and wherein the direct path is for performing only the write operation.
The operating method of claim 28, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and in response to at least a portion of primary recovery data, among the recovery data, being not written to the specified position, determining the storage device to be unavailable.
The operating method of claim 8, further comprising: writing the recovery data to the non-volatile memory through the performance path, in response to the power being cut off and the performance path being determined to be normal.
The operating method of claim 28, wherein the storage device includes a plurality of cores, and the selecting of the core includes selecting the core among the plurality of cores for which the direct path directly accessing the non-volatile memory is formed.
The operating method of claim 8, wherein the recovery data includes user data, debug data, user data digest, device metadata, and map data.
The operating method of claim 28, wherein the recovery data includes user data, debug data, user data digest, device metadata, and map data.
The operating method of claim 8, further comprising: determining the performance path to be normal, in response to each of write operations of writing first to n-th data of the recovery data to the non-volatile memory being completed within a first time.
The operating method of claim 28, further comprising: setting write information including position information indicating a position in the non- volatile memory to which the recovery data is to be written, wherein the writing of the recovery data includes writing the recovery data to the non- volatile memory based on the write information.
The operating method of claim 8, further comprising: setting write information including position information indicating a position in the non-volatile memory to which the recovery data is to be written, wherein the writing of the recovery data includes writing the recovery data to the non-volatile memory based on the write information.
The operating method of claim 32, wherein the non-volatile memory includes a plurality of memory regions, and the writing of the recovery data includes writing the recovery data to a memory region included in the non-volatile memory corresponding to the selected core based on the write information.
The operating method of claim 12, wherein the non-volatile memory includes a plurality of memory regions, and the writing of the recovery data includes writing the recovery data to a memory region among the plurality of memory regions corresponding to the selected core based on the write information.
The operating method of claim 28, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and opening the non-volatile memory in response to the recovery data being all written to the specified position.
The operating method of claim 8, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and opening the non-volatile memory in response to the recovery data being all written to the specified position.
The operating method of claim 28, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and in response to primary recovery data, among the recovery data, being written to the specified position, marking a data defect on user data corresponding to the primary recovery data.
The operating method of claim 8, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and in response to primary recovery data, among the recovery data, being written to the specified position, marking a data defect on user data corresponding to the primary recovery data.
The operating method of claim 35, wherein the primary recovery data includes a user data digest, device metadata, and map data.
The operating method of claim 15, wherein the primary recovery data includes a user data digest, device metadata, and map data.
The operating method of claim 35, further comprising: in response to the primary recovery data, among the recovery data, being written to the specified position, transmitting, to a host, an error signal as a response signal according to the user data corresponding to the primary recovery data.
The operating method of claim 15, further comprising: in response to the primary recovery data, among the recovery data, being written to the specified position, transmitting, to a host, an error signal as a response signal according to the user data corresponding to the primary recovery data.
An operating method of a storage device including a storage controller and a non-volatile memory, the storage controller including a plurality of cores and a buffer memory configured to store recovery data, the operating method comprising: setting write information for writing recovery data written in the buffer memory to the non- volatile memory; and communicating with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the communicating including, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation on the data, and in response to a power being cut off to the storage device and the fault being detected in the performance path, writing the recovery data to the non-volatile memory through the direct path corresponding to a core selected based on the write information among the plurality of cores, wherein the recovery data is data required to recover the storage device when the power is restored after the power is cut off.
An operating method of a storage device including a storage controller and a non-volatile memory, the storage controller including a plurality of cores and a buffer memory configured to store recovery data, the operating method comprising: setting write information for writing recovery data written in a buffer memory to the non-volatile memory; and communicating with the non-volatile memory through both a performance path that includes the plurality of cores and at least one direct path of a plurality of direct paths each corresponding to one of the plurality of cores in which at least one of the plurality of cores is directly connected to the non-volatile memory without traversing other direct paths of ones of the plurality of cores, the communicating including, communicating with the non-volatile memory via the performance path during normal operation, in which the plurality of cores operate together to perform a write operation, a read operation or an erase operation on the data, detecting whether a fault is present in performance of the performance path, in response to a power being cut-off to the storage device, and in response to the fault being detected as present in the performance path while the power remains cut-off, selecting, based on the write information, one of the plurality of cores as a selected core and collecting the recovery data, and moving the recovery data from the buffer memory to the non-volatile memory by transmitting the recovery data to the non-volatile memory through the direct path corresponding to the selected core, wherein the performance path includes the plurality of cores, and the direct path includes one of the plurality of cores.
The operating method of claim 38, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and in response to primary recovery data, among the recovery data, being written to the specified position, marking a data defect on user data corresponding to the primary recovery data.
The operating method of claim 18, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and opening the non-volatile memory in response to the recovery data being all written to the specified position.
The operating method of claim 38, wherein writing the recovery data includes selecting the core among the plurality of cores performing an operation related to an interface with a host.
The operating method of claim 19, further comprising: marking a data defect on user data corresponding to primary recovery data among the recovery data, in response to the primary recovery data being written to a specified position, and wherein the primary recovery data includes a user data digest, device metadata, and map data.
Regarding claim 21, the claim of the instant application is substantially similar to that of Claim 1 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 21 of the instant application and claim 1 of US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application.
Regarding claim 22 of the instant application, the limitations are substantially identical to claim 11 of the Patent as while claim 11 recites steps directed to a method claim, one of ordinary skill in the art would recognize the system of claim 22 as being capable of executing the method steps. Furthermore, it would be obvious to one of ordinary skill in the art that the claim limitation of claim 11 of the US Patent thereby presents the context for claim 22 of the instant application regarding the determination of the fault as whether completion is within a first time or not being a binary state.
Regarding claim 23 of the instant application, the limitations are substantially identical to limitations of claim 17 of the Patent as while claim 17 recites steps directed to a method claim, one of ordinary skill in the art would recognize the system of claim 23 as being capable of executing the method steps. Furthermore, it would be obvious to one of ordinary skill in the art that the claim limitation of claim 17 of the US Patent thereby presents the context for claim 23 of the instant application regarding at least a portion of user data not being written due to power off.
Regarding claim 24 of the instant application, the limitations are substantially identical to limitations of claim 7 of the Patent.
Regarding claim 25 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 26 of the instant application, the limitations are substantially identical to limitations of claim 3 of the Patent.
Regarding claim 27 of the instant application, the limitations are substantially identical to claim 4 of the Patent.
Regarding claim 28 of the instant application, the limitations are substantially identical to claim 8 of the Patent. Furthermore, it would be obvious to one of ordinary skill in the art that the claim limitation of claim 8 of the US Patent thereby presents the context for claim 28 of the instant application regarding the recovery data as being data required to recover the storage device when power is restored.
Regarding claim 30 of the instant application, the limitations are substantially identical to claim 8 of the Patent.
Regarding claim 31 of the instant application, the limitations are substantially identical to claim 10 of the Patent.
Regarding claim 32 of the instant application, the limitations are substantially identical to limitations of claim 12 of the Patent.
Regarding claim 33 of the instant application, the limitations are substantially identical to limitations of claim 13 of the Patent
Regarding claim 34 of the instant application, the limitations are substantially identical to claims 14 of the Patent.
Regarding claim 35 of the instant application, the limitations are substantially identical to limitations of claim 15 of the Patent.
Regarding claim 36 of the instant application, the limitations are substantially identical to claim 16 of the Patent.
Regarding claim 37 of the instant application, the limitations are substantially identical to claim 17 of the Patent.
Regarding claim 38 of the instant application, the limitations are substantially identical to claim 18 of the Patent. Furthermore, it would be obvious to one of ordinary skill in the art that the claim limitation of claim 18 of the US Patent thereby presents the context for claim 38 of the instant application regarding the recovery data as being data required to recover the storage device when power is restored.
Regarding claim 39 of the instant application, the limitations are substantially identical to claim 20 of the Patent.
Regarding claim 40 of the instant application, the limitations are substantially identical to claim 18 of the Patent.
This is a nonstatutory double patenting rejection.
Allowable Subject Matter
Claim 29 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and all outstanding issues resolved. Claim 29 recites “[t]he operating method of claim 28, further comprising: scanning a specified position in the non-volatile memory in response to the power being provided; and in response to at least a portion of primary recovery data, among the recovery data, being not written to the specified position, determining the storage device to be unavailable.” Herein the claim requires scanning a specified position in the non-volatile for at least a portion of primary recovery data, which is stored among the recovery data, to determine whether the storage device is available. The prior art of record deemed of closest relevance, including Gao as noted in the current action, teach provisioning of bypass datapaths to be used by a processor to transfer data to and from non-volatile memory during power cut-off scenarios; however, the prior art of record alone and in combination do not render obvious to one of ordinary skill in the art the claimed implementation of scanning for primary recovery data among stored recovery data at a specified position in the manner as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US 2018/0089116) – Abstract wherein selection of a transfer path by an application processor to a storage device based on current power is discussed.
Jayakumar et al. (US 2015/0186278) – Figures 1 and 2 and corresponding description wherein processor core cache flushing during power failure is discussed.
Basu (US 2020/0050512) – Paragraphs [0039-45] and [0073-77] wherein storing protective codeword information in response to power loss is discussed.
Gao et al. (US 2022/0206702) – Paragraphs [0214-220] wherein selectable processor data paths are discussed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135