DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-20 are pending.
Information Disclosure Statement PTO-1449
The Information Disclosure Statement submitted by applicant on 07-07-2025, 03-05-2025 and 12-20-2024 have been considered. Please see attached PTO-1449.
Claim Objections
Claim 14 recites limitation similar to the limitation of the claim 13 and is objected to as being a duplicated copy of claim 13. Appropriate correction required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 recites the limitation "the processor". There is insufficient antecedent basis for this limitation in the claim.
Claim 9 depends on the claim 8 recites “the processor”. However, the claim 8 is a method claim and does not include a processor. Therefore, it is unclear to which processor claim 9 refers, rendering the scope of the claim indefinite.
Claims 10-13 recite “the processor” and are rejected as being unclear for the same reason discussed above.
Claim 16 recites “the one or more processor”. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 depends on the claim 15. Although claim 15 recites “a processor”, it does not include “one or more processor”. Therefore, it is unclear to which “one or more processor” claim 16 is refers, rendering the scope of the claim indefinite.
Claims 17-20 recite “the one or more processor” and are rejected as being unclear for the same reason discussed above.
Claim Rejections - 35 USC § 101
835 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
The claims when analyzed under 2019 Revised Patent Subject Matter Eligibility Guidance, are directed to abstract idea. Claim 1 for example, recites processors and, therefore, is a machine.
The claim 1 recites the limitation of “…read a first command…read a first authentication tag…determine if the command is a last command…and generate a second authentication tag using a sequence number”. These limitations, under broadest reasonable interpretation are directed performance of the limitation in a human mind or by a human. That is, nothing in the claim element precludes the step from practically being performed in the mind or by a human. For example, a human could look at a first instruction (read the first command) written on a piece of paper or list (command buffer), the list including next to each instruction a symbol, checkmark or a code (authentication tags) that verifies the instruction is valid, the human reads a first symbol (first authentication tag), checks (determine) whether the first instruction is a final instruction on the list, and if it is the last instruction writes a new mark or code (second authentication tag). Accordingly, claim recites amental process when analyzed under step 2A prong 1.
Claim 1 is further analyzed in step 2A prong 2, to evaluate whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by identifying whether there are any additional elements recited in the claim beyond the judicial exception, and evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. However, each of the remaining limitation (i.e., processor) is no more than mere instruction to apply the exception using a generic computer component. The combination of these additional elements is no more than generic computer functions. Thus, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limitations on practicing the abstract idea.
Claim 1 is additionally analyzed under Step 2B to evaluates whether the claim as a whole amount to significantly more than the recited exception, whether any additional element, or combination of additional elements, adds an inventive concept to the claim. When claims evaluated under step 2B, it is no more than what is well-understood, routine, conventional activity in the field. The specification does not provide any indication anything other than a generic computer component.is a last command…and generate a second authentication tag…” is a well-understood, routing and conventional function when it is claimed in a merely generic manner as it is here.
Independent claims 8 and 15 include limitations similar to the limitations of claim 1 and are rejected under 35 U.S.C. 101 as being directed to abstract idea for the same reasons discussed above with respect to claim 1.
Claims 2, 9 and 16, recite the limitation of: generate the second authentication tag without the tag sequence number upon determining that the command is not the last command in the command buffer, which could be done by a human. A human could generate on a piece of paper an authentication tag without using a sequence or order number. The claims do not recite additional element that amounts to significantly more than the judicial exception.
Claims 3, 10 and 17, recite the limitation of: determine whether the first authentication tag matches the second authentication tag, which could be done by a human. A human could compare a first authentication tag with a second authentication tag to determine if they match. The claims do not recite additional element that amounts to significantly more than the judicial exception.
Claims 4, 11 and 18, recite the limitation of: abort execution of the first command upon determining that the first authentication tag does not match the second authentication tag, which could be done by a human. A human could stop processing of a task upon determination that tags do not match. The claims do not recite additional element that amounts to significantly more than the judicial exception.
Claims 5, 12 and 19, recite the limitation of: execute the first command upon determining that the first authentication tag matches the second authentication tag, which could be done by a human. A human could process a task upon determination that tags do match. The claims do not recite additional element that amounts to significantly more than the judicial exception.
Claim 6 recites the limitation of: update a memory address for a next command in the command buffer; and update a next tag record in the tag record array, which could be done by a human. A human could update an address for a next task in a list of tasks and update or modify a next tag in a record or a list. The claim does not recite additional element that amounts to significantly more than the judicial exception.
Claims 7, 13, 14 and 20, recite the limitation of: increment an anti-replay counter to generate a second tag sequence number, which could be done by a human. A human could increment a counter to generate a second code sequence or order number. The claims do not recite additional element that amounts to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-12, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Pappachan et al. (US Publication No.2017/0024568), hereinafter Pappachan, in view of Junk (US Publication No.2020/0259635), hereinafter Junk further in view of Trichina et al. (US Publication No. 2018/0034628), hereinafter Trichina.
As per claim 1, 8 and 15, Pappachan teaches an apparatus, comprising one or more processors (paragraph [0021], “computing device”) to: read a first command from a command buffer (paragraph [0068], each metadata buffer includes authentication tag data, and paragraph [0059], authentication tag data read); read a first authentication tag [in a tag array] associated with the first command (paragraph [0059], “a metadata consumer of the computing device 100 reads and validates the AT metadata from the AT queue 318”); determine whether the first command is a last command in the command buffer; and
generate a second authentication tag using a tag sequence number upon determining that the command is a last command in the command buffer.
Pappachan does not explicitly disclose read a first authentication tag in a tag array; determine whether the first command is a last command in the command buffer; and generate a second authentication tag using a tag sequence number upon determining that the command is a last command in the command buffer.
However, in an analogous art, Junk discloses, read a first authentication tag in a tag array (figure 5, 6, paragraph [0111], “associated data 604 further includes the flags 602, a counter 608, and authenticated plaintext 610. The ciphertext 606 of the illustrated example includes authenticated encryption data 612 and a message integrity check (MIC) 614. The example flags 602 include an authentication bit 616, an encryption bit 618, a direction bit 620, a source bit 622, a version least significant bit 624, a version most significant bit 626, and an auxiliary bit 628”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Pappachan with Junk. This would have been obvious because one of ordinary kill in the art would have been motivated to include the well known authentication tag array in order to provide efficient lookup and comparison and enable fast identification and authentication.
Pappachan in view of Junk does not explicitly disclose, determine whether the first command is a last command in the command buffer; and generate a second authentication tag using a tag sequence number upon determining that the command is a last command in the command buffer. However, in an analogous art, Trichina discloses, determine whether the first command is a last command in the command buffer; and generate a second authentication tag using a tag sequence number upon determining that the command is a last command in the command buffer (paragraph [0095], responsive to determining that the current input data block is the last one, the method produces output value. The output value is produces by outputting the unmasked result of the last iteration. The unmasked result value represents the value of universal polynomial hash function, the polynomial hash function value utilized in performing authenticated encryption or decryption operation; paragraph [0049], the result of the last iteration may be unmasked by performing the exclusive disjunction operation with the mask correction value MC.sub.k=M*H.sup.k…, and paragraph [0050], where k denotes the number of iteration).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Pappachan and Junk with Trichina. This would have been obvious because one of ordinary skill in the art would have been motivated to prevent gaining unauthorized access to protected information.
As per claim 2, 9 and 16, Pappachan furthermore disclose, generate the second authentication tag without the tag sequence number upon determining that the command is not the last command in the command buffer (paragraph [0050], “In block 410, a metadata producer of the computing device 100 generates authentication tag (AT) metadata based on one or more DMA transactions. The metadata producer computes the authentication tag (AT) metadata using an authenticated encryption algorithm such as AES-GCM, using the encryption key used to protect the DMA channel, and paragraph [0053], “the metadata producer determines whether to write out the AT metadata. If not, the method 400 loops back to block 410, in which the metadata producer may generate additional AT metadata for subsequent DMA transactions”).
As per claim 3, 10 and 17, Pappachan furthermore discloses, determine whether the first authentication tag matches the second authentication tag (paragraph [0059], “in block 426, a metadata consumer of the computing device 100 reads and validates the AT metadata from the AT queue 318. The metadata consumer may match the AT metadata from the AT queue 318 with DMA transfer data stored in the DMA buffer 316 and then validate the integrity of the DMA data using the AT metadata. One potential embodiment of an AT metadata to DMA data matching and verification algorithm is described further below in connection with FIG. 6. In some embodiments, in block 428 the trusted software may validate the AT metadata for one or more input DMA transactions. For example, when the DMA transaction is completed and the trusted software (e.g., the trusted DDE 310) is notified of the DMA completion, the trusted software may read the AT data from the AT queue 318 using the AT-data matching algorithm and validate the integrity of the DMA data. In some embodiments, in block 430 the cryptographic engine 140 may validate the AT metadata for one or more output DMA transactions. For example, when the cryptographic engine 140 intercepts the output data to be read by the I/O controller 144, the cryptographic engine 140 reads the corresponding AT metadata from the AT queue 318”).
As per claim 4, 11 and 18, Pappachan furthermore discloses, abort execution of the first command upon determining that the first authentication tag does not match the second authentication tag (paragraph [0062], terminating DMA transaction).
As per claim 5, 12 and 19, Pappachan furthermore discloses, execute the first command upon determining that the first authentication tag matches the second authentication tag (paragraph [0062], “if the AT metadata is valid, the method 400 branches to block 436, in which the metadata consumer releases the DMA transaction data for processing”, paragraph [0064], “Referring now to FIG. 6, in use, the computing device 100 may execute a method 600 for matching authentication tags with associated DMA data”).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Pappachan in view of Junk and Trichina, further in view of Hars et al. (US Publication No. 2018/3/0117577), hereinafter Hars.
As per claim 6, Pappachan as modified does not explicitly disclose, but in an analogous art, Hars discloses, update a memory address for a next command in the command buffer; and update a next tag record in the tag record array (paragraph [0025],“the write counter is incremented, and a new authentication tag is computed. The write counter value, the authentication tag and the ciphertext is then written back to the memory as a value at the target address”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the modified Pappachan with Hars. This would have been obvious because one of ordinary skill in the art would have been motivated to do so in order to achieve the predictable result of protecting microprocessor accesses to a memory.
Claims 7, 13, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pappachan in view of Junk and Trichina, further in view of Jean et al. (US Publication No. 2021/0334016), hereinafter Jean.
As per claim 7, 13, 14 and 20, Pappachan as modified does not explicitly disclose, but in an analogous art, Hars discloses, wherein the processor further to increment an anti-replay counter to generate a second tag sequence number (paragraph [0017], “Writes to an RPMB portion of memory can be authenticated using a key/mac (message authentication code), such as a HMAC SHA-256 algorithm calculated from a security key (e.g., programmed into a host device or a memory device) and a counter value that is incremented each time the RPMB portion of memory is written. The counter and use of the key/mac ensures that messages cannot be captured by an attacker and then later replayed (as the key/mac will not match due to the change in the counter).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the modified Pappachan with Jean. This would have been obvious because one of ordinary skill in the art would have been motivated to provide a secure way to exchange information and avoid man in the middle attacks.
References Cited, Not Used
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Qu, et al. (US Patent No. 9,916,443) discloses, techniques for detection of malware that attempt to exploit a memory allocation vulnerability. In some embodiments, a system, process, and/or computer
program product for detecting an attempt to exploit a memory allocation vulnerability includes receiving a malware sample; monitoring an array operation performed by the malware sample using a memory monitoring component; and determining whether the array operation performed by the malware sample is suspicious.
Vermeire (US Publication No. 2007/0186083) discloses, processor having a processing pipeline is extended with an arrangement. Loop start detection until detects a loop start instruction containing information about the loop count and last instruction in the loop information about the first instruction in the loop is also present. Loop end detection until is provided with the loop end information, and fetch stage is provided with the loop start information by loop start detection until. Upon detection of a loop end, loop end detection until generates detection tags labeling the content of pipeline which are evaluated by tag detection until. Loop execution control stage compares the loop count information with detection information generated by tag detection until and, if necessary, removes superfluous instructions from pipeline.
Conclusion
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/ALI S ABYANEH/Primary Examiner, Art Unit 2437
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