DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to communication(s) filed on 12/20/2024. Claims 1-11 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 12/20/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kawaguchi US 2010/0042771 (“Kawaguchi”) in view of Murphy US 2017/0262369 (“Murphy”) and in further view of Choy et al. US 2009/0240889 (“Choy”).
As per independent claim 1, Kawaguchi teaches A method for managing cache coherence in a multicore processor system (“a plurality of processors having a cache and performs directory-based coherence control and an order guarantee method which guarantee the consistency of data stored in the shared memory and the cache,” para 0003), wherein each core has a respective cache (“each processor includes a cache that stores a copy of a part of data stored in the shared memory,” para 0011 and FIGS. 2-3) and accesses multiple banks of a memory shared between the cores (“each processor includes a cache that stores a copy of a part of data stored in the shared memory,” para 0011 and FIGS. 2-3), the method comprising the steps of:
managing a directory in each memory bank for implementing a directory-based cache coherence (“each bank includes a memory main body, a directory unit that stores area information of the memory main body for data stored in the cache and issues an invalidation request for invalidating the data stored in the cache” para 0011 and FIGS. 2-3);
writing to a current memory address by a core (“issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body” para 0011);
searching the directory assigned to the current memory address for cores that possess a cache line matching the current memory address (“The directory 32 in the bank 3 examines the coherence of the received store instruction (S12) and determines whether invalidation is necessary to maintain the consistency of the memory (S13). … if it is necessary to make the invalidation request (Y in S13), the directory 32 enqueues the invalidation request … the invalidation request is issued to the target processor (S15).” “search directory” (S12). Para 0058 and FIG. 6);
sending respective cache line invalidation commands to the cores returned by the directory, the commands including the memory address of the cache line (“transmitting the invalidation request and the identifier from each bank to at least one of the plurality of processors a sequence of queuing, and confirming return of the identifier in each processor.” Para 0012);
for each core, serving multiple invalidation commands received from different memory banks (“transmitting the invalidation request and the identifier from each bank to at least one of the plurality of processors a sequence of queuing, and confirming return of the identifier in each processor.” Para 0012);
when the count of invalidation commands received is one, transmitting the received invalidation command to the cache (“issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body,” para 0011).
Kawaguchi discloses all of the claim limitations from above and additionally teaches sending bulk invalidation commands. For example, Kawaguchi teaches “transmitting the invalidation request … to at least one of the plurality of processors”, para 0012. That is, Kawaguchi implicitly teaches sending invalidation requests to a plurality of processors if the plurality of processors have been identified as needing invalidation of their cache lines. Nevertheless, for bulk invalidation requests, a new reference is being relied upon herein. Further, Kawaguchi does not explicitly teach “wherein the step of serving multiple invalidation commands comprises the steps of: counting a number of invalidation commands received since a last clock cycle”.
In an analogous art in the same field of endeavor, Murphy teaches sending bulk invalidation requests. Murphy teaches when the count of invalidation commands received is greater than one, transmitting to the cache a single command consolidating the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines (“multiple cache lines in a multi-level cache memory system to be invalidated using a single bulk invalidate command that is configured to be received by the cache memory system. In one example, a last level cache (LLC) may receive the bulk invalidate command which may be shared and operated upon by invalidate engines within each cache level to invalidate any cache line that may be in that cache level.” Para 0051).
Given the teaching of Murphy, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kawaguchi with “when the count of invalidation commands received is greater than one, transmitting to the cache a single command consolidating the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines”. The motivation would be that processing performance may be improved, para 0005 of Murphy.
Kawaguchi in combination with Murphy discloses all of the claim limitations from above, but does not explicitly teach “wherein the step of serving multiple invalidation commands comprises the steps of: counting a number of invalidation commands received since a last clock cycle”.
However, in an analogous art in the same field of endeavor, Choy teaches wherein the step of serving multiple invalidation commands comprises the steps of: counting a number of invalidation commands received since a last clock cycle (“Inside the L1 data cache 103, there is a free running XI [cross-invalidate] counter 110 which increments when the L2 107 has received an XI request from the L3 109 (the storage controller maintaining MP coherency) and decrements when the L2 107 has processed those XI, and has sent the XI to the L1 caches 103 106 when needed.” Para 0026 and FIG. 1).
Given the teaching of Choy, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kawaguchi and Murphy with “wherein the step of serving multiple invalidation commands comprises the steps of: counting a number of invalidation commands received since a last clock cycle”. The motivation would be that if new data is unused, the problem of using the old data after the new data is prevented, para 0024 of Choy, improving coherency.
As per independent claim 7, Kawaguchi teaches A processor (“multi-core processors” para 0045 and FIG. 2) comprising:
multiple cores (“multi-core processors” para 0045 and FIG. 2), each including a local cache (“each processor includes a cache that stores a copy of a part of data stored in the shared memory,” para 0011 and FIGS. 2-3);
multiple memory banks forming a shared memory for the multiple cores (“each processor includes a cache that stores a copy of a part of data stored in the shared memory,” para 0011 and FIGS. 2-3);
a directory-based cache coherence protocol manager, comprising for each core a circuit for consolidating multiple cache line invalidation commands received from the memory banks (“each bank includes a memory main body, a directory unit that stores area information of the memory main body for data stored in the cache and issues an invalidation request for invalidating the data stored in the cache” para 0011 and FIGS. 2-3), the consolidation circuit comprising:
a selection circuit configured to, depending on whether the count of received invalidation commands is equal to 1 or greater, transmit to the cache a single received invalidation command (“issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body,” para 0011).
Kawaguchi discloses all of the claim limitations from above and additionally teaches sending bulk invalidation commands. For example, Kawaguchi teaches “transmitting the invalidation request … to at least one of the plurality of processors”, para 0012. That is, Kawaguchi implicitly teaches sending invalidation requests to a plurality of processors if the plurality of processors have been identified as needing invalidation of their cache lines. Nevertheless, for bulk invalidation requests, a new reference is being relied upon herein. Further, Kawaguchi does not explicitly teach “a counter for counting the received invalidation commands”.
In an analogous art in the same field of endeavor, Murphy teaches sending bulk invalidation requests. Murphy teaches or a consolidated invalidation command for the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines (“multiple cache lines in a multi-level cache memory system to be invalidated using a single bulk invalidate command that is configured to be received by the cache memory system. In one example, a last level cache (LLC) may receive the bulk invalidate command which may be shared and operated upon by invalidate engines within each cache level to invalidate any cache line that may be in that cache level.” Para 0051).
Given the teaching of Murphy, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kawaguchi with “or a consolidated invalidation command for the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines”. The motivation would be that processing performance may be improved, para 0005 of Murphy.
Kawaguchi in combination with Murphy discloses all of the claim limitations from above, but does not explicitly teach “a counter for counting the received invalidation commands”.
However, in an analogous art in the same field of endeavor, Choy teaches a counter for counting the received invalidation commands (“Inside the L1 data cache 103, there is a free running XI [cross-invalidate] counter 110 which increments when the L2 107 has received an XI request from the L3 109 (the storage controller maintaining MP coherency) and decrements when the L2 107 has processed those XI, and has sent the XI to the L1 caches 103 106 when needed.” Para 0026 and FIG. 1).
Given the teaching of Choy, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kawaguchi and Murphy with “a counter for counting the received invalidation commands”. The motivation would be that if new data is unused, the problem of using the old data after the new data is prevented, para 0024 of Choy, improving coherency.
Allowable Subject Matter
Claims 2-6 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10-11 are allowed.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance.
After careful considerations, examination and search of the claimed invention, the closest prior art of record does not teach or anticipate the claimed feature of claim 2 “wherein each core has a respective set-associative multi-way cache, the method further comprising the steps of: recording in the directories the ways in which the caches store the cache lines; transmitting the ways in the invalidation commands sent to the cores; and including in the consolidated invalidation command, for each received invalidation command, a pair of coordinates including a set index, extracted from the memory address, and the way” in combination with the overall claimed limitations when interpreted in light of the specification.
Kawaguchi alone or in any combination with Murphy and Choy do not teach the above-noted claim limitations with such specificity. Two additional close prior art references were considered by the Examiner that partially teach the above-noted claim limitations. The references are Arimilli et al. US 6,397,303 (“Arimilli”) and Hosokawa et al. US 2014/0006720 (“Hosokawa”).
Arimilli teaches “The cache lines stored within data array 34 are recorded in cache directory 32, which contains one directory entry for each way in data array 34. Each directory entry comprises a tag field 40, … Tag field 40 specifies which cache line is stored in the corresponding way of data array 34 by storing the tag bits of the system memory address of the cache line.” Col 4 lines 46-53 of Arimilli.
However, Arimilli does not teach “transmitting the ways in the invalidation commands sent to the cores; and including in the consolidated invalidation command, for each received invalidation command, a pair of coordinates including a set index, extracted from the memory address, and the way” required by claim 2.
Like Arimilli, Hosokawa also teaches “the directory cache 31 includes a plurality of cache lines associated with the lower addresses of the memory addresses in the memory 10. Moreover, the directory cache 31 includes a plurality of WAYs in each cache line. That is, the directory cache 31 is a multi-way cache memory. The directory cache 31 thus stores a plurality of pieces of directory data 12 stored at memory addresses with the same index in different WAYs in the same cache line.” Para 0041 of Hosokawa.
However, Hosokawa does not teach “transmitting the ways in the invalidation commands sent to the cores; and including in the consolidated invalidation command, for each received invalidation command, a pair of coordinates including a set index, extracted from the memory address, and the way” required by claim 2.
Therefore claim 2 is patentable.
Claims 3-6 depend from claim 2 and these claims are also patentable by virtue of their dependency.
Dependent claim 8 recites similar subject matter as claim 2 and this claim is also patentable for the aforementioned reason.
Dependent claim 9 depends from claim 8 and this claim is patentable by virtue of its dependency.
Independent claim 10 recites similar subject matter as claim 2 and this claim is also patentable for the aforementioned reason.
Dependent claim 11 depends from claim 10 and this claim is patentable by virtue of its dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132