DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 11-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pugsley et al. (US PGPub No. 2015/0149714), hereinafter referred to as PUGSLEY.
Consider Claim 1,
PUGSLEY teaches a processor (PUGSLEY, e.g., Fig 5; ¶0044, processor), comprising:
prefetching circuitry associated with a cache level of a hierarchy of one or more cache levels (PUGSLEY, e.g., Fig 1(105,155, 165);¶0018,0022-0023, prefetch logic of plural cache levels.), the prefetching circuitry configured to:
determine a memory level from which data associated with a prefetch request is retrieved (PUGSLEY, e.g., Fig 2, describes determining if requested data is in a current memory level or a different memory level.); and
store the data associated with the prefetch request in a level two cache in response to the memory level being a lower level cache in the hierarchy of one or more cache levels or system memory (PUGSLEY, e.g., Fig 2(250-260), if data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L2/L3 boundary; ¶0032, higher level cache is further from processor core. In other words, if the data is in L3 it is then stored in L2.).
PUGSLEY fails to expressly describe moving data to a level two cache when the requested data is lower than a level three cache in the hierarchy. However, PUGSLEY describes plural prefetch operations. PUGSLEY describes that conventional prefetch requests can prefetch requested data from a system memory (PUGSLEY, e.g., ¶0038, conventional prefetch requests may be forwarded to system memory to obtain the requested data.). In other words, PUGSLEY describes moving data from a system memory to a non-adjacent level in the caching hierarchy. Therefore, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the processor of PUGSLEY such that requested data is moved from the system memory directly to where it is needed (i.e., a L2 cache) because it avoids unnecessary data migrations when confidence is high.
Consider Claim 2,
The modified processor of PUGSLEY further teaches wherein the prefetching circuitry is further configured to transfer the data from the level two cache to a level one cache in response to the processor requesting the data associated with the prefetch request (PUGSLEY, e.g., Fig 2(250-260), if data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L1/L2 boundary; ¶0032, higher level cache is further from processor core. In other words, if the data is in L2 it is then stored in L1; Fig 1(100), prefetch circuitry is part of processor core (i.e., it is a processor request).).
Consider Claim 3,
The modified processor of PUGSLEY further teaches wherein the prefetching circuitry is further configured to store other data associated with a subsequent prefetch request in a level one cache or the level two cache in response to the memory level from which the other data is retrieved being the level two cache or the level three cache, respectively, wherein the level one cache and the level two cache being higher levels in the hierarchy (PUGSLEY, e.g., Fig 2(250-260), if other data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L1/L2 boundary; ¶0032, higher level cache is further from processor core. In other words, if the other data is in L2 it is then stored in L1.).
Consider Claim 4,
The modified processor of PUGSLEY teaches the processor of claim 1, above, and further teaches wherein the prefetching circuitry is further configured to store other data associated with a subsequent prefetch request in a closer cache in response to the memory level from which the other data is retrieved being a level one cache or the level two cache (PUGSLEY, e.g., Fig 2(250-260), if other data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L1/L2 boundary; ¶0032, higher level cache is further from processor core. In other words, if the other data is in L2 it is then stored in L1.). PUGSLEY fails to explicitly describe wherein the closer cache is a micro-op cache. However, PUGSLEY does describe an instruction cache and a trace cache with prefetch logic to generate prefetch requests (PUGSLEY, e.g., ¶0017-0018). PUGSLEY further describes the mechanism for moving data from a first cache to a cache closer to the processor (PUGSLEY, e.g., Figs 2 and 3). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the processor of PUGSLEY such that data is moved to a micro-op cache because moving the instruction elements into a dedicated cache closer to the processing elements can reduce access latencies and improve cache hit rates (PUGSLEY, e.g., ¶0001).
Consider Claim 5,
The modified processor of PUGSLEY further teaches wherein the data associated with the prefetch request is one or more instructions for execution by the processor (PUGSLEY, e.g., ¶0017, discloses an instruction cache including prefetch logic. An instruction cache prefetch is for one or more instructions.).
Consider Claim 6,
The modified processor of PUGSLEY further teaches wherein the data associated with the prefetch request is one or more constants or variables for the processor to perform operations on (PUGSLEY, e.g., ¶0057, data cache stores recently used elements/operands.).
Consider Claim 11,
PUGSLEY teaches a system comprising:
a processor (PUGSLEY, e.g., Fig 5; ¶0044, processor) including a cache system with one or more cache levels that include prefetching circuitry (PUGSLEY, e.g., Fig 1(105,155, 165);¶0018,0022-0023, prefetch logic of plural cache levels.), the processor configured to execute one or more workloads; and
the prefetching circuitry configured to:
prefetch data associated with a prefetch request into a level two cache of the one or more cache levels in response to the data being retrieved from a lower cache level than the level two cache or system memory (PUGSLEY, e.g., Fig 2(250-260), if data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L2/L3 boundary; ¶0032, higher level cache is further from processor core. In other words, if the data is in L3 it is then stored in L2.); and
upon the processor referencing the data for execution of the one or more workloads, transfer the data associated with the prefetch request into a level one cache of the one or more cache levels (PUGSLEY, e.g., Fig 2(250-260), if data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L1/L2 boundary; ¶0032, higher level cache is further from processor core. In other words, if the data is in L2 it is then stored in L1; Fig 1(100), prefetch circuitry is part of processor core (i.e., it is a processor reference).).
PUGSLEY fails to expressly describe moving data to a level two cache when the requested data is lower than a level three cache in the hierarchy. However, PUGSLEY describes plural prefetch operations. PUGSLEY describes that conventional prefetch requests can prefetch requested data from a system memory (PUGSLEY, e.g., ¶0038, conventional prefetch requests may be forwarded to system memory to obtain the requested data.). In other words, PUGSLEY describes moving data from a system memory to a non-adjacent level in the caching hierarchy. Therefore, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of PUGSLEY such that requested data is moved from the system memory directly to where it is needed (i.e., a L2 cache) because it avoids unnecessary data migrations when confidence is high .
Consider Claim 12,
The modified system of PUGSLEY further teaches wherein the prefetching circuitry is further configured to store other data associated with a subsequent prefetch request in the level one cache or the level two cache in response to the other data being retrieved from the level two cache or the level three cache, respectively (PUGSLEY, e.g., Fig 2(250-260), if other data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L1/L2 boundary; ¶0032, higher level cache is further from processor core. In other words, if the other data is in L2 it is then stored in L1.).
Consider Claim 13,
The modified system of PUGSLEY teaches the system of claim 11, above, and further teaches wherein the prefetching circuitry is further configured to store other data associated with a subsequent prefetch request in a closer cache in response to the other data being retrieved from the level two cache (PUGSLEY, e.g., Fig 2(250-260), if other data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L1/L2 boundary; ¶0032, higher level cache is further from processor core. In other words, if the other data is in L2 it is then stored in L1.). PUGSLEY fails to explicitly describe wherein the closer cache is a micro-op cache. However, PUGSLEY does describe an instruction cache and a trace cache with prefetch logic to generate prefetch requests (PUGSLEY, e.g., ¶0017-0018). PUGSLEY further describes the mechanism for moving data from a first cache to a cache closer to the processor (PUGSLEY, e.g., Figs 2 and 3). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of PUGSLEY such that data is moved to a micro-op cache because moving the instruction elements into a dedicated cache closer to the processing elements can reduce access latencies and improve cache hit rates (PUGSLEY, e.g., ¶0001).
Consider Claim 14,
The modified system of PUGSLEY further teaches wherein the data associated with the prefetch request is one or more instructions for execution by the processor (PUGSLEY, e.g., ¶0017, discloses an instruction cache including prefetch logic. An instruction cache prefetch is for one or more instructions.).
Consider Claim 15,
The modified system of PUGSLEY further teaches wherein the data associated with the prefetch request is one or more constants or variables for the processor to perform operations on (PUGSLEY, e.g., ¶0057, data cache stores recently used elements/operands.).
Consider Claim 20,
PUGSLEY teaches a method comprising:
determining a memory level from which data associated with a prefetch request is retrieved (PUGSLEY, e.g., Fig 1, describes determining if requested data is in a current memory level or a different memory level.); and
storing the data associated with the prefetch request in a level two cache in response to the memory level being a level three cache of a hierarchy of one or more cache levels or system memory (PUGSLEY, e.g., Fig 2(250-260), if data is in higher level memory, promote to lower level memory; ¶0026, prefetching may occur at L2/L3 boundary; ¶0032, higher level cache is further from processor core. In other words, if the data is in L3 it is then stored in L2.).
PUGSLEY fails to expressly describe moving data to a level two cache when the memory level is lower than a level three cache in the hierarchy. However, PUGSLEY describes plural prefetch operations. PUGSLEY describes that conventional prefetch requests can prefetch requested data from a system memory (PUGSLEY, e.g., ¶0038, conventional prefetch requests may be forwarded to system memory to obtain the requested data.). In other words, PUGSLEY describes moving data from a system memory to a non-adjacent level in the caching hierarchy. Therefore, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the method of PUGSLEY such that requested data is moved from the system memory directly to where it is needed (i.e., a L2 cache) because it avoids unnecessary data migrations when confidence is high .
Allowable Subject Matter
Claims 7-10 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the instant claims have been considered but are moot in view of the new grounds for rejection necessitated by the applicant’s amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
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/Gary W. Cygiel/Primary Examiner, Art Unit 2137
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