Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The amendment filed on May 19, 2026 has been received and entered.
Applicant’s Amendments to the Claims have been received and acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 11, line 12, it is not clear what is meant by “a second number of data lanes a second plurality of data lanes…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sharma et al. (U.S. Publication No. 2018/0285227 A1), hereafter referred to as Sharma’227.
Referring to claim 1, Sharma’227 as claimed, a signal extension device (see Fig. 9) comprising: a first plurality of data lanes having a first number of data lanes (upconfiguring the link width of the link from a x4 (i.e. 4 lane) to a x16 (i.e. 16 lane) link, see paras. [0076], [0086]); a second plurality of data lanes having a second number of data lanes that is greater than the first number of data lanes (upconfiguring the link width of the link from a x4 (i.e. 4 lane) to a x16 (i.e. 16 lane) link, see paras. [0076], [0086]; compensation for difference in frequencies between bit rates at two ends of a link, dynamically adapt retimer to support multiple different interconnect protocols see paras. [0067]-[0074]; also note: link speed change, lane width change, see paras. [0076] and [0085]; e.g. UPI to PCIe, see para. [0052]); and a control circuit configured to retransmit data received from one of the first plurality of data lanes and the second plurality of data lanes to another of the first plurality of data lanes and the second plurality of data lanes (capture the received bit stream prior to regenerating and re-transmitting the bit stream, see paras. [0064], [0072]) based on a static mapping of lanes between the first number of data lanes of the first plurality of data lanes and the second number of lanes of the second plurality of data lanes (the change mapping module may quantify the amount by which the size of the elasticity buffer may be increased or decreased in response to detecting a particular type of change to the characteristics of the link, see paras. [0076] and [0084]; also note: determine a type and scope of a link characteristic modification and consult a table or other mapping to calculate, identify, or otherwise determine an amount by which the elastic buffer size could be modified based on the link characteristic modification, see para. [0092]).
As to claim 2, Sharma’227 also discloses a ratio of the second number of lanes of the second plurality of data lanes to the first number of lanes of the first plurality of data lanes corresponds to a ratio of a first data rate of the first plurality of data lanes to a second data rate of the second plurality of data lanes (link width increase (where idle available lanes are activated and used in transmission of data on the link), see para. [0088]; also note: to scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, etc., see paras. [0049] and [0054]).
As to claim 3, Sharma’227 also discloses each of the first plurality of data lanes statically
maps (link width increase (where idle available lanes are activated and used in transmission of data on the link), see para. [0088]; also note: to scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, etc., see para. [0049] and [0054]) to more than one of the second plurality of data lanes based on the ratio of the first data rate to the second data rate (compensation for difference in frequencies between bit rates at two ends of a link, dynamically adapt retimer to support multiple different interconnect protocols see paras. [0067]-[0074]; also note: link speed change, lane width change, see paras. [0076] and [0085]).
As to claim 4, Sharma’227 also discloses to pass through credit information for a transmit flow control without updating the credit information (connection is transparent, see para. [0056]; also note: sideband messaging, see para. [0080]).
As to claim 5, Sharma’227 also discloses for a downstream transmission from the first plurality of data lanes to the second plurality of data lanes, the control circuit is configured to:
receive a data stream from the first plurality of data lanes in a first data packet format (receive a data stream at a retimer, see paras. [0072], [0143]); convert the received data stream into a second data packet format (regenerating the data for transmission on a corresponding retimer’s port, see paras. [0063], [0064], [0067], [0072]; also note: translation, see para. [0052]); store the converted data stream into a buffer (elastic buffering to handle the periodic compensation of frequency differences between devices, see paras. [0067], [0068], [0088]); and transmit the converted data stream from the buffer to the second plurality of data lanes (retransmitting the bit stream, see para. [0064]).
As to claim 6, Sharma’227 also discloses for the downstream transmission, the control circuit is further configured to: store the converted data stream into a replay buffer; transmit the converted data stream from the replay buffer to the second plurality of data lanes in response to a replay request (retransmitting the bit stream, see para. [0064]; also note: requests acknowledged, see paras. [0073], [0076], [0091]); and deallocate the converted data stream from the replay buffer in response to an acknowledgement response from the second plurality of data lanes (in the PCIe specification, the data link layer provides a reliable mechanism for exchanging TLPs between components in a link…applies packet sequence identifier, calculates and applies error detection code , and submits the modified TLPs to the Physical Layer for transmission, see paras. [0042], [0073]; also note: PCIe specification standard has a replay buffer to support retransmission of unacknowledged packets).
As to claim 7, Sharma’227 also discloses for the downstream transmission, the control circuit is further configured to: detect an error in the received data stream; and discard the received data stream in response to detecting the error (forcing the reset of the link includes changing particular data in the data stream received from a first on of the two devices to a particular value; and sending the changed particular data to the second one of the two devices, where the particular value artificially causes an error condition in the link, see paras. [0137], [0153]; also note: error detection and bits removed, see paras. [0042], [0057], [0067], and [0075]).
As to claim 8, Sharma’227 also discloses for an upstream transmission from the second
plurality of data lanes to the first plurality of data lanes, the control circuit is configured to: receive a data stream from the second plurality of data lanes in a second data packet
format; store the received data stream into a buffer (each retimer including retimer logic, protocol logic, elasticity buffer, and buffer manager logic, see para. [0071] and Fig. 9); convert the stored data stream into a first data packet format; and transmit the converted data stream from the buffer to the first plurality of data lanes (the data stream includes data sent from one of the two devices to the other (e.g. in a downstream direction), as well as the data sent in response (e.g. in the upstream direction), see para. [0092], Figs. 7A-C, 8A-B; also note: upstream, see paras. [0061], [0073], [0078]).
Note claims 9 and 19 recite similar limitations of claim 6. Therefore they are rejected based on the same reason accordingly.
Note claims 10, 14, and 16 recite similar limitations of claim 7. Therefore they are rejected based on the same reason accordingly.
Referring to claim 11, Sharma’227 as claimed, a system comprising: a memory (see Fig. 9); a processor coupled to the memory and configured to transmit at a first data rate (processor device connected to retimer, each retimer including retimer logic, protocol logic, elasticity buffer, and buffer manager logic, see para. [0071] and Fig. 9); an endpoint device configured to transmit at a second data rate that is less than the first data rate (endpoint device or another processor device, see para. [0071] and Fig. 9); a signal extension device configured to transmit data between the processor and the endpoint device and pass through credit information (credit-based flow control, see paras. [0032], [0033]) between the processor and the endpoint device, the signal extension device comprising: a first number of data lanes of a first plurality of data lanes (upconfiguring the link width of the link from a x4 (i.e. 4 lane) to a x16 (i.e. 16 lane) link, see paras. [0076], [0086]) coupled to the processor and configured to transmit data at the first data rate (link compliant with PCIe, USB, UPI, or other interconnect protocol, see para. [0059]); a second number of data lanes a second plurality of data lanes that is greater than the first number of data lanes and is coupled to the endpoint device and configured to transmit at the second data rate (upconfiguring the link width of the link from a x4 (i.e. 4 lane) to a x16 (i.e. 16 lane) link, see paras. [0076], [0086]; compensation for difference in frequencies between bit rates at two ends of a link, dynamically adapt retimer to support multiple different interconnect protocols see paras. [0067]-[0074]; also note: link speed change, lane width change, see paras. [0076] and [0085]; e.g. UPI to PCIe, see para. [0052]); and a control circuit configured to retransmit data between the first plurality of data lanes and the second plurality of data lanes (capture the received bit stream prior to regenerating and re-transmitting the bit stream, see paras. [0064], [0072]) based on a static mapping between the first plurality of data lanes and the second plurality of data lanes (the change mapping module may quantify the amount by which the size of the elasticity buffer may be increased or decreased in response to detecting a particular type of change to the characteristics of the link, see paras. [0076] and [0084]; also note: determine a type and scope of a link characteristic modification and consult a table or other mapping to calculate, identify, or otherwise determine an amount by which the elastic buffer size could be modified based on the link characteristic modification, see para. [0092]).
Note claims 12 and 18 recite the corresponding limitations of claims 2 and 3. Therefore they are rejected based on the same reason accordingly.
Note claim 13 recites similar limitations of claims 5 and 6. Therefore it is rejected based on the same reason accordingly.
Note claims 15 and 20 recite similar limitations of claims 8 and 9. Therefore they are rejected based on the same reason accordingly.
Note claim 17 recites similar limitations of claim 11. Therefore it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 5/19/2026 have been fully considered but they are not persuasive.
At the outset, Applicants are reminded that claims subject to examination will be given their broadest reasonable interpretation consistent with the specification. In re Morris, 127 F.3d 1048, 1054-55 (Fed. Cir. 1997). In fact, the "examiner has the duty of police claim language by giving it the broadest reasonable interpretation." Springs Window Fashions LP v. Novo Industries, L.P., 65 USPQ2d 1862, 1830, (Fed. Cir. 2003). Applicants are also reminded that claimed subject matter not the specification, is the measure of the invention. Disclosure contained in the specification cannot be read into the claims for the purpose of avoiding the prior art. In re Sporck, 55 CCPA 743, 386 F.2d, 155 USPQ 687 (1986).
With this in mind, the discussion will focus on how the terms and relationships thereof in the claims are met by the references. Response to any limitations that are not in the claims or any arguments that are irrelevant and/or do not relate to any specific claim language will not be warranted.
Applicant argued that “Sharma’227 does not teach a second number of data lanes that is greater than the first number of data lanes.” (Pages 14-15 of Applicant’s Amendment)
Examiner does not agree with Applicant. As set forth in the claim rejections, Sharma’227 discloses a first plurality of data lanes having a first number of data lanes (upconfiguring the link width of the link from a x4 (i.e. 4 lane) to a x16 (i.e. 16 lane) link, see paras. [0076], [0086]); a second plurality of data lanes having a second number of data lanes that is greater than the first number of data lanes (upconfiguring the link width of the link from a x4 (i.e. 4 lane) to a x16 (i.e. 16 lane) link, see paras. [0076], [0086]; compensation for difference in frequencies between bit rates at two ends of a link, dynamically adapt retimer to support multiple different interconnect protocols see paras. [0067]-[0074]; also note: link speed change, lane width change, see paras. [0076] and [0085]; e.g. UPI to PCIe, see para. [0052]). There are various configurations when extending a link connecting the devices. The link width may be reconfigured from 4 lanes to 16 lanes and replicated for each of the multiple lanes, see paras. [0070], [0071]). Applicant is suggested to expand on the ratio of the number of data lanes that corresponding to ratio of data rate relating to the static mapping of lanes.
In summary, Sharma’227 teaches the claimed limitations as set forth.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
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/TITUS WONG/Primary Examiner, Art Unit 2181
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