DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 18/990,733 filed on 12/20/2024.
Claims 1-20 have been examined.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/31/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
Claims 16-20, are method claims that include one or more contingent clauses, such as “determining whether Z, and performing X in response to X being Y” and do not explicitly claim that the condition, Y, positively occurs in the claimed language. The broadest reasonable interpretation of these claims does not include those X steps occurring. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04 (II).
Looking at claim 16, for example, the claim states, “determining whether the destination command stream has access authority in response to the destination command stream pointing to the second storage region; directing the control circuit to stop reading the second storage region in response to the destination command stream not having access authority; and directing the control circuit to read the second storage region and output a destination parameter in response to the destination command stream having access authority.” But the claim never explicitly recites that the “destination command stream pointing to the second storage region”, or that the “destination command stream not having access authority”, or that the “destination command stream having access authority”. As a result, the broadest reasonable interpretation of these limitations are that destination command stream doesn’t point to the second storage and therefore, the “determining whether the destination command stream has access authority,” “directing the control circuit to stop reading the second storage region,” and “directing the control circuit to read the second storage region and output a destination parameter” does not need to occur in the prior art for the claim to be met by the prior art.
Claims 17-20 also claim similar contingent limitations without positively reciting that their condition occurs in the claim language and therefore have similar interpretations.
Claims 17 additionally contains limitations that further define the limitations in question above from claim 16. Since the broadest reasonable interpretation of each claim is that these limitations are contingent and as written do not need to occur, the further defining limitations from claims 17 also do not need to occur in the prior art in order for the prior art to meet the limitations of each respective claim as they merely further define something that is not required to occur within the claim.
The examiner encourages the applicant to positively recite these conditions occurring in the claim limitations so that the resulting steps would be required to occur under the broadest reasonable interpretation of each claim. As an example for claim 16, “determine that the destination command stream points to the second storage region; determining whether the destination command stream has access authority in response to the destination command stream pointing to the second storage region; wherein the destination command stream comprises a first destination command stream and a second destination command stream; determining that the first destination command stream has access authority; determining that the second destination command stream not having access authority; directing the control circuit to stop reading the second storage region in response to the second destination command stream not having access authority; and directing the control circuit to read the second storage region and output a destination parameter in response to the first destination command stream having access authority.” Similar amendments need to be made to claims 17-20 to correct their language.
The examiner would like to note, that in the interest of compact prosecution, prior art is being applied to claims 16-20 as if the claims positively recited the limitations in question.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11, 14, 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2022/0414437) and Huang (US 2025/0110648).
With respect to claim 1, Liu teaches of a control chip, comprising: a storage circuit, comprising: a memory, comprising a first region and a second region (fig. 1-2; paragraph 26; where the main memory comprises an instruction memory and a data memory),
wherein the first region stores a plurality of command streams (fig. 2; paragraph 26; where the instruction memory stores one or more instructions), and
the second region stores a plurality of parameters (fig. 2; paragraph 24, 26; where the data memory stores data relating to computations, including parameters, activations, and weights); and
a control circuit configured to access the memory (fig. 1-2; paragraph 25; where the neural network accelerator accesses the main memory to read data and parameters via an interface between the accelerator and the memory); and
a neural-network processing unit (NPU) receiving a destination block and performing a destination command stream corresponding to the destination block (fig. 1-2; paragraph 36-37; where the neural network accelerator receives instructions that initiate operation to transfer parameters from the data memory to specific computing units).
Liu fails to explicitly teach of (1) wherein: in response to the destination command stream pointing to the second region, the control circuit or the NPU determines whether the destination command stream has access authority, (2) in response to the destination command stream not having access authority, the control circuit does not read the second region, (3) in response to the destination command stream having access authority, the control circuit reads the second region and provides a destination parameter stored in the second region to the NPU.
However, Huang teaches of wherein: in response to the destination command stream pointing to the second region, the control circuit or the NPU determines whether the destination command stream has access authority (fig. 1, 4, 7; paragraph 207-210, 270-277; where when the sector address for the instruction is within a range it is checked to see if it complies with the preset specific sector range rules. In the combination with Liu, that range is in the data memory),
in response to the destination command stream not having access authority, the control circuit does not read the second region (fig. 1, 4, 7; paragraph 207-210, 270-277; where when the range is a range that can neither be read nor written, a response of blank or not real data is returned and the data isn’t read),
in response to the destination command stream having access authority, the control circuit reads the second region and provides a destination parameter stored in the second region to the NPU (fig. 1, 4, 7; paragraph 207-210, 270-277; where when the range is a range that can be read, the data is read and a return response of successful execution occurs).
Liu and Huang are analogous art because they are from the same field of endeavor, as they involve data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of Liu and Huang before the time of the effective filing of the claimed invention to incorporate the protection modes of Huang into the memory of Liu. Their motivation would have been to protect the security of the stored data (Huang, paragraph 4-5).
With respect to claim 16, Liu teaches of a control method applied in a neural-network processing unit (NPU) and a control circuit, comprising: writing a plurality of command streams to a first storage region of the control circuit (fig. 2; paragraph 26; where the instruction memory stores one or more instructions);
writing a plurality of parameters to a second storage region of the control circuit (fig. 2; paragraph 24, 26; where the data memory stores data relating to computations, including parameters, activations, and weights);
triggering the NPU so that the NPU performs a destination command stream corresponding to a destination block (fig. 1-2; paragraph 36-37; where the neural network accelerator receives instructions that initiate operation to transfer parameters from the data memory to specific computing units).
Huang teaches of determining whether the destination command stream has access authority in response to the destination command stream pointing to the second storage region (fig. 1, 4, 7; paragraph 207-210, 270-277; where when the sector address for the instruction is within a range it is checked to see if it complies with the preset specific sector range rules. In the combination with Liu, that range is in the data memory);
directing the control circuit to stop reading the second storage region in response to the destination command stream not having access authority (fig. 1, 4, 7; paragraph 207-210, 270-277; where when the range is a range that can neither be read nor written, a response of blank or not real data is returned and the instruction to read data isn’t executed); and
directing the control circuit to read the second storage region and output a destination parameter in response to the destination command stream having access authority (fig. 1, 4, 7; paragraph 207-210, 270-277; where when the range is a range that can be read, the data is read and a return response of successful execution occurs).
The reasons for obviousness are the same as indicated above with respect to claim 1.
With respect to claim 2, Liu teaches of further comprising: a bus coupled between the storage circuit and the NPU (fig. 2; paragraph 26; instruction bus, 212, and ring bus 216 are connected between the main memory and the neural network accelerator); and
a transmission path independent from the bus (fig. 2; paragraph 26; instruction bus, 212 and ring bus, 216, are connected between the main memory and the neural network accelerator).
With respect to claim 3, Huang teaches of wherein: the control circuit determines whether the destination command stream has access authority according to a setting signal (paragraph 169, 514; where when the protection module/intermediate device determines that the device type is allowed to be accessed, it sends a signal to the computer device);
in response to the setting signal being at a specific level, it indicates that the destination command stream has access authority, and in response to the setting signal not being at the specific level, it indicates that the destination command stream does not have access authority (paragraph 169, 514; where when the protection module/intermediate device determines that the device type is allowed to be accessed, it sends a signal to the computer device).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 4, the combination of Liu and Huang teaches of wherein: the NPU determines whether the destination block is located in the first region (Liu paragraph 26-27, 36-37; Huang paragraph 270-277, 514; where it is determined whether the instructions being executed are within the rules for the specific sector range. In the combination with Liu, this is done by the neural network accelerator of Liu), and
in response to the destination block being located in the first region, the NPU sets the setting signal so that the setting signal is at the specific level (Liu paragraph 26-27, 36-37; Huang paragraph 270-277, 514; where it is determined that the instructions being executed are within the rules for the specific sector range, a signal is indicated allowing the instruction to execute. In the combination with Liu, this is done by the neural network accelerator of Liu), and
in response to the destination block not being located in the first region, the NPU sets the setting signal so that the setting signal is not at the specific level (Liu paragraph 26-27, 36-37; Huang paragraph 270-277, 514; where it is determined that the instructions being executed are not within the rules for the specific sector range, a signal is indicated preventing the instruction from executing. In the combination with Liu, this is done by the neural network accelerator of Liu).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 5, the combination of Liu and Huang teaches of wherein the NPU sends the setting signal to the control circuit via the bus (Liu; paragraph 29; as the instruction bus is used to communicate instructions between the main memory’s interface and the neural network accelerator, thus suggests that the signals of Huang allowing for the instructions to be sent and carried out should also use the instruction bus).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 6, the combination of Liu and Huang teaches of wherein the NPU sends the setting signal to the control circuit via the transmission path (Liu; paragraph 32; as the ring bus can be used to communicate instructions and model parameters between the main memory’s interface and the neural network accelerator’s computing units, thus suggests that the signals of Huang allowing for the instructions to be sent and carried out should also use the ring bus).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 7, the combination of Liu and Huang teaches of wherein the control circuit provides information about the first and second regions to the NPU via the transmission path (Huang 278-280; as the protection module (analogous to the neural network accelerator of Liu) reads the storage device and establishes the sector ranges for the different areas, this suggests that the address ranges for the sector areas were transferred from the storage device’s interface to the protection module. In the combination with Liu, this can be done via the instruction bus (Liu, paragraph 29)), and
the NPU determines whether the destination command stream has access authority according to the information about the first and second regions (Huang; paragraph 270-280; where the instruction falls within a preset address range, it is determined if it complies with the rules for the range).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 8, Liu teaches of wherein: in response to the destination block being in the first region, the NPU sends a command access request to instruct the control circuit to read the destination command stream from the first region (paragraph 27-28, 30, 33, 36-38; where a computing unit of the neural network accelerator instructs the memory to send the instructions and or model parameters to the computing units of the accelerator),
the NPU performs the destination command stream (paragraph 36-39; where the computing units of the accelerator execute the instructions using the parameters to compute the output activations) and
determines whether the destination command stream points to the second region according to address information about the second region, in response to the destination command stream pointing to the second region, the NPU sends a parameter access request for the control circuit to provide the destination parameter (paragraph 27-28, 30, 33, 36-39; where when the instructions are executed, the corresponding parameters are stored in the computing unit wide memories so the output activations can be computed).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 9, Huang teaches of wherein in response to a portion of the destination block not being located in the first region, the control circuit refuses to read the second region (paragraph 270-277; where when the instruction address falls into the second sector region and it doesn’t comply with the second sector region’s rules, the instruction is not read executed).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 10, Liu teaches of wherein the NPU comprises: a direct memory access interface configured to access commands and parameters from the bus (fig. 2; paragraph 32-37, 46; where the ring bus is used for DMA transfers of instructions and parameters from the memory to the computing units of the neural network accelerator).
With respect to claim 11, Liu teaches of wherein in response to the destination block being completely located in the first region and the destination command stream pointing to the second region, the control circuit provides the destination parameter to the NPU (paragraph 36-37; where when instructions in the instruction memory are multicast to the computing units of the neural network accelerator, the operations initiating the transfer of the corresponding model parameters from the data memory to the particular computing units of the neural network accelerator occur).
With respect to claim 14, Liu teaches of wherein the memory is a read-only memory (paragraph 24; where the main memory is a ROM or EEPROM).
With respect to claim 17, the combination of Liu and Huang teaches of wherein the step of determining whether the destination command stream has access authority comprises: determining whether the destination block is located in the first storage region (Liu paragraph 26-27, 36-37; Huang paragraph 270-277, 514; where it is determined whether the instructions being executed are within the rules for the specific sector range. In the combination with Liu, this is done by the neural network accelerator of Liu),
wherein: in response to determining that the destination block is located in the first storage region, this means that the destination command stream has access authority (Liu paragraph 26-27, 36-37; Huang paragraph 270-277, 514; where it is determined that the instructions being executed are within the rules for the specific sector range, the instructions are allowed to execute), and
in response to determining that the destination block is not located in the first storage region, this means that the destination command stream does not have access authority (Liu paragraph 26-27, 36-37; Huang paragraph 270-277, 514; where it is determined that the instructions being executed are not within the rules for the specific sector range, the instruction is prevented from executing).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 18, Huang teaches of directing the control circuit to output address information pertaining to the first storage region; and comparing the address information pertaining to the first storage region and address information pertaining to the destination block (paragraph 270-280; where the target sector address corresponding to the instruction is verified and compared with the preset sector address range),
wherein: in response to the address information pertaining to the first storage region comprising the address information pertaining to the destination block, this means that the destination block is located in the first storage region (paragraph 270-280; when the address falls within a preset range, the address corresponds to that specific region),
in response to the address information pertaining to the first storage region not completely comprising the address information pertaining to the destination block, this means that the destination block is not located in the first storage region (paragraph 270-280; when the address doesn’t fall within a particular preset range, the address doesn’t correspond to that specific region).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 19, Huang teaches of directing the control circuit to output address information about the second storage region; and comparing the address information about the second storage region and address information about the destination command stream in response to the address information about the first storage region comprising the address information about the destination block (paragraph 270-280; where the target sector address corresponding to the instruction is verified and compared with another preset sector address range),
wherein: in response to the address information about the second storage region comprising the address information about the destination command stream, this means that the destination command stream has access authority (paragraph 270-280; when the address falls within a preset range, and conforms to the range’s rules, it is allowed to execute),
in response to the address information about the second storage region not comprising the address information about the destination command stream, this means that the destination command stream does not have access authority (paragraph 270-280; when the address falls within a preset range, and doesn’t conform to the range’s rules, it is does not to execute).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu and Huang as applied to claims 1 above, and further in view of Briceno et al. (US 2023/0306275).
With respect to claim 12, the combination of Liu and Huang fails to explicitly teach of a central processing unit (CPU) providing the destination block, wherein the CPU drives the NPU so that the NPU performs the destination command stream corresponding to the destination block.
However, Briceno teaches of a central processing unit (CPU) providing the destination block (fig. 3; paragraph 16-17; where the CPU sends a request to the NPU to perform a set of neural network processing operations).
The combination of over Liu, Huang and Briceno teaches of wherein the CPU drives the NPU so that the NPU performs the destination command stream corresponding to the destination block (Liu, paragraph 36-39; Briceno, paragraph 16-17; where in the combination, the CPU is the host of Liu that instructs the accelerator to perform the computations for the neural network layer).
Liu, Huang, and Briceno are analogous art because they are from the same field of endeavor, as they involve data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of Liu, Huang, and Briceno before the time of the effective filing of the claimed invention to incorporate the CPU instructing the accelerator of the combination of Liu and Huang as taught in Briceno. Their motivation would have been to more efficiently manage operation of the system.
With respect to claim 13, Liu teaches of wherein the NPU comprises: a first access interface configured to receive the destination block; a second access interface configured to receive the destination parameter (fig. 1-2; paragraph 26-34; where the main memory sends the instructions and parameters to the computing units of the accelerator via the bus and ring bus);
a first register configured to store the destination block; a second register storing trigger information (fig. 1-2; paragraph 26-34; where the instruction buffers of the computing units store the instructions from the host); and
a logic circuit determining whether to perform the destination command stream corresponding to the destination block according to the trigger information (paragraph 36-40; where the accelerator executes the neural network layer computations in response to the instruction from the host).
Briceno teaches of wherein the CPU provides the trigger information (paragraph 16-17; where the CPU sends a request to the NPU to perform a set of neural network processing operations).
The reasoning for obviousness is the same as indicated above with respect to claim 12.
Claim(s) 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu and Huang as applied to claims 14 and 16 above, and further in view of Horn et al. (US 2006/0059059).
With respect to claim 15, the combination of Liu and Huang fails to explicitly teach of wherein in response to the control circuit erasing one of the command streams stored in the first region and the parameters stored in the second region, the control circuit erases the other command streams stored in the first region and the parameters stored in the second region.
However Horn teaches of wherein in response to the control circuit erasing one of the command streams stored in the first region and the parameters stored in the second region, the control circuit erases the other command streams stored in the first region and the parameters stored in the second region (paragraph 124; where after the execution of the processes is complete, the memory buffers are released and cleared. In the combination with Liu and Huang, this would clear the data memory and instruction memory of Liu).
Liu, Huang, and Horn are analogous art because they are from the same field of endeavor, as they involve data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of Liu, Huang, and Horn before the time of the effective filing of the claimed invention to incorporate the clearing of the memory after the execution is complete in the combination of Liu and Huang as taught in Horn. Their motivation would have been to ensure there is adequate memory space available.
With respect to claim 20, Horn teaches of wherein in response to either of the first or second storage regions being erased by the control circuit, the control circuit erases the other of the first and second storage regions (paragraph 124; where after the execution of the processes is complete, the memory buffers are released and cleared. In the combination with Liu and Huang, this would clear the data memory and instruction memory of Liu).
The reasoning for obviousness is the same as indicated above with respect to claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Luo (US 2024/0211615) discloses an NPU and CPU that access memory utilizing permissions that only allow the NPU read access to the memory and only allow the CPU write access to the memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138