Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 3-16 and 18-20 set forth in the amendment submitted 7/31/2026 form the basis of the present examination.
Response to Arguments
The objection to drawing (Figures 1 and 4), set forth to the Non-Final Office action mailed on 6/26/2026 has been withdrawn because of the amendment filed on 7/31/2026.
The objection to abstract, set forth to the Non-Final Office action mailed on 6/26/2026 has been withdrawn because of the amendment filed on 7/31/2026.
The objection to claim 9, set forth to the Non-Final Office action mailed on 6/26/2026 has been withdrawn because of the amendment filed on 7/31/2026.
The interpretation of the claim limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, set forth to the Non-Final Office action mailed on 6/26/2026 has been withdrawn because of the amendment filed on 7/31/2026.
Applicant’s arguments, see remarks page 10, filed 7/31/2026, with respect to the rejection(s) of Claims 16-200 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 10, of the remarks, filed on 7/31/2026, regarding the rejection(s) of Claims 16-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, that “In view of the amendment, Applicant submits the rejection is overcome.”
Examiner Response:
Applicant’s arguments, see remarks page 10 (stated above), filed 7/31/2026, with respect to the rejection(s) of Claims 16-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, as applied to the Non-Final Office Action mailed on 7/31/2026 have been fully considered and is not persuasive because applicant has amended claim 16 however claim 16 still does not recite enough structure therefore claim recites insufficient structure for performing the recited method of " generating an RF output signal and forwarding said RF output signal to a DUT; receiving a feedback signal from the DUT; dynamically generating waveform information". Paragraphs 48 of the specification teach that the system 10 provides the structure corresponding the method steps, however, claim 16 only includes RF output signal and DUT. And the new amended limitation only recites “a feedback configuration”. Claim still does not recite enough structure to the method steps. Therefore the rejection(s) of Claims 16 and 18-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, as applied to the Non-Final Office Action mailed on 7/31/2026 has been maintained, as set forth below. See the rejection set forth below.
Applicant’s arguments, see remarks page 10-13, filed 7/31/2026, with respect to the rejection(s) of Claim(s) 1-13 and 15-20 under 35 U.S.C. 102 (a) (1) as being anticipated by Gershon et al. (Hereinafter, “Gershon”) in the US Patent Number US 7072781 B1 and the rejection of Claim(s) 14 under 35 U.S.C. 103 as being unpatentable over Gershon ‘781 B1 in view of Nentwig in the US patent Application Publication Number US 20090192738 A1 have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 11-13, of the remarks, filed on 7/31/2026, regarding the rejection(s) of Claim(s) 1-13 and 15-20 under 35 U.S.C. 102 (a) (1) as being anticipated by Gershon et al. (Hereinafter, “Gershon”) in the US Patent Number US 7072781 B1 and the rejection of Claim(s) 14 under 35 U.S.C. 103 as being unpatentable over Gershon ‘781 B1 in view of Nentwig in the US patent Application Publication Number US 20090192738 A1, that “Applicant respectfully submits the Office Action misconstrues the claimed "feedback interpreter" and "feedback configuration." The claims do not merely require monitoring a DUT and causing waveform changes. Rather, the claims require "a feedback interpreter configured to generate and/or update a feedback configuration based on the feedback signal." Nothing in the (Remarks-Page 11) cited portions or anywhere else within Gershon discloses generating, maintaining, or updating any such configuration construct.
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Thus, in the Gershon system, transitions between basic waveform shapes occur dynamically upon the asynchronous occurrence of real-time physical threshold events, such as a current crossing a threshold level. Gershon completely lacks a "feedback interpreter" that evaluates feedback signals to construct or modify a software/logical data structure representing a feedback configuration.
Furthermore, Gershon fails to teach or suggest the claimed feedback configuration comprising "a number of consecutive segments, wherein each segment references or comprises a part of a respective stored or calculated waveform sample having a determined duration." By contrast, in the Gershon system, the actual temporal duration of an active slice during testing is contingent upon unpredictable external threshold crossings by the physical cell being tested (such as cell state switching times), rather than being governed by a constructed sequence of consecutive segments where each segment possesses a determined duration referenced within a feedback configuration. …………….. (Remarks-Page 12) waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration" (col. 4, lines 5-8), which describes pre-assembling simple analog signal shapes off-line during initial setup, rather than dynamically updating a segment-based sequence in real time based on feedback messages.
Consequently, Gershon lacks both the functional data construct of a feedback configuration and the dedicated processing element of a feedback interpreter. A segment whose duration is governed by an asynchronous DUT threshold crossing is materially different from a segment having a determined duration specified or represented in a generated configuration.
As anticipation under 35 U.S.C. § 102 requires that each and every element of the claim be disclosed in a prior art reference, based on the foregoing, it is clear that Gershon fails to teach all features of amended independent claims 1 and 16.
Accordingly, Applicant respectfully requests withdrawal of the anticipation rejection.
Applicant respectfully traverses the obviousness rejection of Claim 14
The introduction of the secondary reference of Nentwig, which is applied for a purported teaching of waveform generator, does not fill in the gaps of Gershon. Accordingly, the references of Gershon and Netwig, individually or in combination, fail to meet all features of the claims.
Therefore, withdrawal of the rejection is respectfully requested (Remarks-page 13).”
Examiner Response:
Applicant’s arguments, see remarks page 11-13 (stated above), filed on 7/31/2026, regarding the rejection(s) of Claim(s) 1-13 and 15-20 under 35 U.S.C. 102 (a) (1) as being anticipated by Gershon et al. (Hereinafter, “Gershon”) in the US Patent Number US 7072781 B1 and the rejection of Claim(s) 14 under 35 U.S.C. 103 as being unpatentable over Gershon ‘781 B1 in view of Nentwig in the US patent Application Publication Number US 20090192738 A1, as applied to the Non-Final Office Action mailed on 6/26/2026 have been fully considered and is not persuasive.
Applicant argues, “nothing in the (Remarks-Page 11) cited portions or anywhere else within Gershon discloses generating, maintaining, or updating any such configuration construct” which is not persuasive. Claim recites, “a feedback interpreter configured to generate and/or update a feedback configuration based on the feedback signal”. Claim recites feedback interpreter however claim does not recite any elements or structure of the feedback interpreter. Therefore, any feedback structure has the function of generating and/or updating a feedback configuration based on the feedback signal.
Gershon discloses, “The test system includes an arbitrary waveform generator (AWG) and a data acquisition system (DAS) connected through a feedback loop that enables the AWG to change its output waveform on the fly based on the parameters of a device under test (DUT) or circuit under test (CUT) that is being monitored by the DAS (Column 1 Line 67 & Column 2 Line 5). The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform (Column 2 Line 15-180). Therefore, the feedback architecture here functions as the feedback interpreter as it changes the output waveform as the feedback signal.
Then claim recites feedback configuration. However, claim does not recite any structure of feedback configuration therefore the output waveform through the feedback loop 108, the AWG 104 and DAS 106 as the feedback configuration. Therefore claim recites, “a feedback interpreter configured to generate and/or update a feedback configuration based on the feedback signal” which is equivalent to “the feedback architecture (feedback interpreter) facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform (configured to update a feedback configuration based on the feedback signal). Output waveform through the feedback loop based on the parameters of a device under test (DUT). Because Gershon discloses, “a data acquisition system (DAS) connected through a feedback loop that enables the AWG to change its output waveform on the fly based on the parameters of a device under test (DUT)”.
Therefore, as applicant did not explicitly mention what is “feedback interpreter” and what is, “feedback configuration” and which signal is “feedback signal” for the broadest reasonable interpretation Gershon disclosed the claimed limitation. Applicant needs to explain the differences between the claim limitation and from the prior art references to differentiate the present invention from prior art reference. Applicant’s argument is therefore not persuasive.
Applicant’s argument that Gershon completely lacks a "feedback interpreter" that evaluates feedback signals to construct or modify a software/logical data structure representing a feedback configuration is not persuasive as explained above.
Although Gershon system is different than the present invention however it is not needed that the prior art should suggest same purpose as the present invention.
The reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. See, e.g., In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006) (motivation question arises in the context of the general problem confronting the inventor rather than the specific problem solved by the invention); Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293, 1323, 76 USPQ2d 1662, 1685 (Fed. Cir. 2005) ("One of ordinary skill in the art need not see the identical problem addressed in a prior art reference to be motivated to apply its teachings."); In re Lintner, 458 F.2d 1013, 173 USPQ 560 (CCPA 1972) (discussed below); In re Dillon, 919 F.2d 688, 16 USPQ2d 1897 (Fed. Cir. 1990), cert. denied, 500 U.S. 904 (1991) (discussed below). Therefore, applicants argument is not persuasive.
Applicant’s argument, “Gershon fails to teach or suggest the claimed feedback configuration comprising "a number of consecutive segments, wherein each segment references or comprises a part of a respective stored or calculated waveform sample having a determined duration” is not persuasive. Claim recites feedback configuration comprises number of consecutive segment…”. However, claim does not recite what feedback configuration is. Gershon discloses, “The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16)”. For the broadest reasonable interpretation as claim does not recite what feedback configuration is and therefore the number of changes in the output waveform 110, including a change in the original order of the preassembled slices can be considered as the number of consecutive segments, where the output waveform as the waveform sample. The slices or segments are part of the output waveform 110 or calculated waveform sample. Gershon discloses, “The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 5-20). Therefore, applicant’s argument is not persuasive.
Applicant’s argument, “Consequently, Gershon lacks both the functional data construct of a feedback configuration and the dedicated processing element of a feedback interpreter” is not persuasive as explained above. Claim is rejected in light of the specification, and the limitation is not incorporated from the specification. If the present invention is different from the prior art reference and then that limitation should be in the claim. Therefore, for the broadest reasonable interpretation Gershon discloses the claim limitation and applicant’s argument is therefore not persuasive as set forth below. See the rejection set forth below.
Applicant’s argument regarding dependent claim 14 is also not persuasive because of the same reason as stated above. Therefore, the rejection(s) of Claim(s) 1 (previous claims 1+2), claims 3-13, claims 15, 16 (previous claim 16+17) and claims 18-20 under 35 U.S.C. 102 (a) (1) as being anticipated by Gershon et al. (Hereinafter, “Gershon”) in the US Patent Number US 7072781 B1 and the rejection of Claim(s) 14 under 35 U.S.C. 103 as being unpatentable over Gershon ‘781 B1 in view of Nentwig in the US patent Application Publication Number US 20090192738 A1 is maintained below. See the rejection set forth below.
For expedite prosecution Applicant is invited to call to discuss the present rejection also if any further clarification needed and to discuss any possible amendment to overcome the references to make the claims allowable.
35 USC § 112(b) Rejections
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It appears that claims 16 and 18-20 should have been rejected under 35 USC 112(b).
Referring to claim 16, it appears that the claim has recited insufficient structure for performing the recited method of having "two states," namely, " generating an RF output signal and forwarding said RF output signal to a DUT; receiving a feedback signal from the DUT; dynamically generating waveform information". Paragraphs 48 of the specification teach that the system 10 provides the structure corresponding the method steps, however, claim 16 only includes RF output signal and DUT. Consequently, the claim does not appear to recite the requisite structure for performing the claimed method. As such, the boundaries of the language are unclear because the claim does not provide a discernable boundary on what structure performs the method. The recited method does not follow from the structure recited in the claim, i.e., the generating and receiving, so it is unclear whether the method requires some other structure or is simply a result of operating the DUT. Thus, one of ordinary skill would not be able to draw a clear boundary between what is and is not covered by the claim. See MPEP 2173.05(g).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-13, 15-16 and 18-20 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Gershon et al. (Hereinafter, “Gershon”) in the US Patent Number US 7072781 B1.
Regarding claim 1, Gershon teaches a system for testing a device-under-test, DUT [112/114] (a test system that is a tool for investigating device behavior or circuit behavior; Column 1 Line 60-61; FIG. 1 illustrates a test system in accordance with the present invention; Column 2 Line 42-43), comprising:
an output port (Figure 1: Modified Figure 1 of Gershon below shows an output port for being connected to the DUT 112) arranged for being connected to the DUT [112] (Referring now to FIG. 1, there is illustrated a test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114; Column 3 Line 60-65);
a waveform generator [116] (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104. The AWG 104 includes a waveform generator 116 that outputs the waveform 110; Column 3 Line 60-67 & Column 4 Line 1-2) configured to generate an RF output signal [110] and to forward said RF output signal to the DUT [112] via the output port (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT; Column 4 Line 1-10; An arbitrary waveform generator (AWG) can indeed be used to generate radio frequency (RF) signals);
a communication interface [108] in Figure 1 (feedback loop 108 as the communication interface as it communicated the signal from the DUT to the DAS)/ [306] in Figure 3 (a tester interface 306 that provides the hardware communication and data connections to the DUT/CUT; Column 4 Line 66-67 & Column 5 Line 1) (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 60-67 & Column 4 Line 1) configured to receive a feedback signal from the DUT [112] (feedback look 108 receives signal from the DUT 112 and transfers to the DAS 106; Figure 1: Modified Figure 1 of Gershon below shows a communication interface [108] receives a feedback signal from the DUT [112]); and
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Figure 1: Modified Figure 1 of Gershon
a processor [106]/Figure 3 (Figure 3 shows the detail of the processor comprising elements 302+106+304+308+306) (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108; Column 3 Line 60-64; Referring now to FIG. 3, there is illustrated a more detailed block diagram of a tester 300; Column 4 Line 57-58) configured to dynamically generate waveform information based on the received feedback signal, wherein the processor is configured to generate the waveform information from stored and/or from real time calculated waveform samples (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106. The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 3 Line 60-67 & Column 4 Line 1-16);
wherein the waveform generator [116] is configured to adjust the RF output signal [110] based on the waveform information (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 1-20);
wherein the processor comprises a feedback interpreter configured to generate and/or update a feedback configuration based on the feedback signal (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1),
wherein the feedback configuration comprises a number of consecutive segments (selection and calibration) (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16),
wherein each segment references or comprises a part of a respective stored or calculated waveform sample (the output waveform 110 in small slices (or segments)) having a determined duration (The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 5-20).
Regarding claim 3, Gershon teaches a system,
wherein the processor comprises a feedback configurator configured to map, for each segment (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16; preassembled slices are the mapping of each segment),
the feedback signal to the respective part of the stored or calculated waveform sample based on a mapping rule and to forward said mapping to the feedback interpreter (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 13-20; Claim 20. A method of testing a device, comprising: defining an output signal in advance of the test; providing a set of base waveforms in a memory; defining initial settings of a test waveform to be applied to the device; slicing the set of base waveforms into waveform slices; assembling selected waveform slices in a sequence to form the test waveform; choosing events that trigger switching from one slice of a sequence to another slice of a sequence during test; applying the test waveform to the device during a test phase; and changing the test waveform in response to a measured change in the device);
wherein the feedback interpreter is configured to generate the feedback configuration based on said mapping (Claim 28. A system that facilitates testing a cell, comprising: means for defining an output signal in advance of the test; means for providing a set of base waveforms in a memory; means for slicing the set of base waveforms into waveform slices; means for determining a sequence of the waveform slices that constitute a test waveform; means for selecting one or more events that trigger switching from one slice to a next slice; means for assembling selects ones of the waveform slices to form the test waveform; means for applying the test waveform to the cell during a test phase; and means for changing the test waveform in response to a measured change in the cell during the test phase; means for set of slicing is a kind of mapping as claim does not recite any specific mapping process).
Regarding claim 4, Gershon teaches a system,
wherein the feedback configurator is configured to calculate at least one waveform sample based on the feedback message in real time (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1; As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT (in real time). For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110; Column 4 Line 8-12).
Regarding claim 5, Gershon teaches a system,
wherein the processor [106]/ [302, 304, 306, and 308] further comprises a sample provider [304+308] (user interface 308 as the sample provider as it functions as external monitor that interfaces to the tester 300 via the tester interface 306 for providing a means of perceiving data and control information of the tester subsystems) configured to continuously receive the feedback configuration and to dynamically generate the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration (Referring now to FIG. 3, there is illustrated a more detailed block diagram of a tester 300. The tester 300 includes the AWG subsystem 104 to control output of the waveform, the waveform manager subsystem 116 that processes the waveform according to changed DUT/CUT parameters, the DAS subsystem 106 that connects to the DUT/CUT to receive parameter signals during the test operation, a processor subsystem 302 that facilitates control and interaction of tester subsystems, a trigger system 304 that facilitates event triggering, and a tester interface 306 that provides the hardware communication and data connections to the DUT/CUT. The tester 300 can also include a user interface (UI) subsystem 308 that facilitates visual and user interaction therewith. The UI 308 can be an LCD monitor, a plasma monitor, or any suitable display, for example. Each of the subsystems (104, 106, 302, 304, 306, and 308) is interconnected by an internal communication bus 310, according to conventional communication schemes. Note that the UI 308 can be an external monitor that interfaces to the tester 300 via the tester interface 306 for providing a means of perceiving data and control information of the tester subsystems. The tester interface 306 can also accommodate user input devices, such as a wired/wireless keyboard, mouse, trackball, etc., to allow the user to interact therewith; Column 4 Line 57-67 & Column 5 Line 1-14; therefore the sample provider [308]+304 configured to continuously receive the feedback configuration and to dynamically generate the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration).
Regarding claim 6, Gershon teaches a system, further comprising:
a memory configured to store the stored waveform samples (The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106). Fast ADC (analog-to-digital converter) devices and DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) using existing off-the-shelf components; Column 4 Line 16-23; Claim 9. The system of claim 1, further comprising a memory that stores standard waveforms that are used to generate the output signal).
Regarding claim 7, Gershon teaches a system,
wherein the memory is a shared memory in a communication network (The basic waveforms can be stored in the shape 1606 memory with standard offsets and amplitudes. This part of memory can be a ROM (Read-Only Memory). During the initialization of the system, the logic extracts the series of slices that are selected by the user, adjusts their amplitudes, offsets or slopes, and stores them in the Sample Buffer 1618 at the correct locations dictated by their sequencing; Column 17 Line 46-52; In hardware, shared memory refers to a block of random access memory (RAM) that can be accessed by several different central processing units (CPUs) in a multiprocessor computer system.
https://www.bing.com/search?q=is%20RAM%20shared%20memory&qs=n&form=QBRE&sp=-1&ghc=1&lq=0&pq=is%20ram%20shared%20memory&sc=9-20&sk=&cvid=E601DB93C16B401BA8A0A3155E937BDE; Therefore, the memory disclosed by Gershon in Figure 16 can be a Rom and can be a shared memory).
Regarding claim 8, Gershon teaches a system,
wherein the system further comprises an access unit [1618] (buffer 1618 as the access unit as it access from the memory) for accessing the memory and to forward the parts of the stored waveform samples from the memory to the sample provider (The digital blocks assemble the slices into a continuous waveform sampled at, for example, 100 Msps. The rules of assembly have been described hereinabove and are based on user selections (made off-line during initialization) and the trigger signals received from the DAS. Throughout the signal path, which includes Waveform Control, MUX, Digital Adjust, Sample Buffer and the DAC, the sampling rate is supplied by the SRCLK signal (e.g., 100 Msps). The triggering functions and associated outputs need to be faster than the sample time (in this example on the order of 1 2 nsec maximum), in order to minimize uncertainty in the waveform and efficiently protect the DUT/CUT (e.g., a cell) from over current and power; Column 16 Line 57-67 & Column 17 Line 1; The basic waveforms can be stored in the shape 1606 memory with standard offsets and amplitudes. This part of memory can be a ROM (Read-Only Memory). During the initialization of the system, the logic extracts the series of slices that are selected by the user, adjusts their amplitudes, offsets or slopes, and stores them in the Sample Buffer 1618 at the correct locations dictated by their sequencing. Some adjustments of amplitude or offset can be made on the fly by the signal path circuits. At any trigger input, the signal path logic will be ready to move to the next slice, make the necessary adjustments to it, and deliver the samples to the DAC 1622. Both the DAC 1622 and the output amplifier 1626 are off-the-shelf components. The amplifier/filter has a fixed gain. To meet the relatively high voltage output and current drive requirements, the last stage is designed with discrete components; Column 17 Line 46-61).
Regarding claim 9, Gershon teaches a system,
wherein the access unit is further configured to receive further waveform samples of different duration and/or with different characteristics and to store said further waveform samples in the memory (The basic waveforms can be stored in the shape 1606 memory with standard offsets and amplitudes. This part of memory can be a ROM (Read-Only Memory). During the initialization of the system, the logic extracts the series of slices that are selected by the user, adjusts their amplitudes, offsets or slopes, and stores them in the Sample Buffer 1618 at the correct locations dictated by their sequencing. Some adjustments of amplitude or offset can be made on the fly by the signal path circuits. At any trigger input, the signal path logic will be ready to move to the next slice, make the necessary adjustments to it, and deliver the samples to the DAC 1622. Both the DAC 1622 and the output amplifier 1626 are off-the-shelf components. The amplifier/filter has a fixed gain. To meet the relatively high voltage output and current drive requirements, the last stage is designed with discrete components; Column 17 Line 46-61).
Regarding claim 10, Gershon teaches a system,
wherein the communication interface is a wireless or wire-bound interface (The tester interface 306 can also accommodate user input devices, such as a wired/wireless keyboard, mouse, trackball, etc., to allow the user to interact therewith; Column 5 Line 11-14).
Regarding claim 11, Gershon teaches a system,
wherein the communication interface is a serial interface configured to receive the feedback signal with a serial data rate (The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106). Fast ADC (analog-to-digital converter) devices and DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) using existing off-the-shelf components; Column 4 Line 5-23; DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) and DAC is one component of the waveform generator and therefore the communication interface is a serial interface configured to receive the feedback signal with a serial data rate).
Regarding claim 12, Gershon teaches a system,
wherein the waveform generator [104] comprises an IQ sample streamer (not required by the claim) and/or a digital-to-analog, DAC, converter (The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106). Fast ADC (analog-to-digital converter) devices and DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) using existing off-the-shelf components; Column 4 Line 16-23).
Regarding claim 13, Gershon teaches a system,
wherein the waveform generator and the processor are integrated in a common device [102] (tester 102 as the common device) (The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108; Column 3 Line 61-64), or
wherein the waveform generator is a standalone device (not required by the claim).
Regarding claim 15, Gershon teaches a system,
wherein the system [100] is an RF signal generator [116] (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT; Column 4 Line 1-10; An arbitrary waveform generator (AWG) can indeed be used to generate radio frequency (RF) signals therefore it can be a RSF signal generator).
Regarding claim 16, Gershon teaches a method for testing a device-under-test, DUT [112/114] (a test system that is a tool for investigating device behavior or circuit behavior; Column 1 Line 60-61; FIG. 1 illustrates a test system in accordance with the present invention; Column 2 Line 42-43), comprising:
generating an RF output signal [110] (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104. The AWG 104 includes a waveform generator 116 that outputs the waveform 110; Column 3 Line 60-67 & Column 4 Line 1-2) and forwarding said RF output signal [110] to a DUT [112] (Referring now to FIG. 1, there is illustrated a test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114; Column 3 Line 60-65) (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT; Column 4 Line 1-10; An arbitrary waveform generator (AWG) can indeed be used to generate radio frequency (RF) signals);
receiving a feedback signal from the DUT [112] (feedback loop 108 receives signal from the DUT 112 and transfers to the DAS 106; Figure 1: Modified Figure 1 of Gershon above shows a communication interface [108] receives a feedback signal from the DUT [112]);
dynamically generating waveform information based on the received feedback signal, wherein the waveform information is generated from stored and/or from real time calculated waveform samples (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106. The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 3 Line 60-67 & Column 4 Line 1-16); and
adjusting the RF output signal [110] based on the waveform information (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 1-20); and
generating and/or updating a feedback configuration based on the feedback signal (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1),
wherein the feedback configuration comprises a number of consecutive segments (selection and calibration) (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16),
wherein each segment references or comprises a part of a respective stored or calculated waveform sample (the output waveform 110 in small slices (or segments)) having a determined duration (The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 5-20).
Regarding claim 18, Gershon teaches a method, further comprising:
mapping, for each segment (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16; preassembled slices are the mapping of each segment), the feedback signal to the respective part of the stored or calculated waveform sample based on a mapping rule and to forward said mapping to the feedback interpreter (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 13-20; Claim 20. A method of testing a device, comprising: defining an output signal in advance of the test; providing a set of base waveforms in a memory; defining initial settings of a test waveform to be applied to the device; slicing the set of base waveforms into waveform slices; assembling selected waveform slices in a sequence to form the test waveform; choosing events that trigger switching from one slice of a sequence to another slice of a sequence during test; applying the test waveform to the device during a test phase; and changing the test waveform in response to a measured change in the device);
wherein the feedback interpreter is configured to generate the feedback configuration based on said mapping (Claim 28. A system that facilitates testing a cell, comprising: means for defining an output signal in advance of the test; means for providing a set of base waveforms in a memory; means for slicing the set of base waveforms into waveform slices; means for determining a sequence of the waveform slices that constitute a test waveform; means for selecting one or more events that trigger switching from one slice to a next slice; means for assembling selects ones of the waveform slices to form the test waveform; means for applying the test waveform to the cell during a test phase; and means for changing the test waveform in response to a measured change in the cell during the test phase; slicing the set of waveform is the mapping as claim does not specifically recites what is mapping and how mapping is done).
Regarding claim 19, Gershon teaches a method, further comprising:
calculating at least one waveform sample based on the feedback message in real time (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1; As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT (in real time). For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110; Column 4 Line 8-12).
Regarding claim 20, Gershon teaches a method, further comprising:
continuously receiving the feedback configuration and dynamically generating the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration (Referring now to FIG. 3, there is illustrated a more detailed block diagram of a tester 300. The tester 300 includes the AWG subsystem 104 to control output of the waveform, the waveform manager subsystem 116 that processes the waveform according to changed DUT/CUT parameters, the DAS subsystem 106 that connects to the DUT/CUT to receive parameter signals during the test operation, a processor subsystem 302 that facilitates control and interaction of tester subsystems, a trigger system 304 that facilitates event triggering, and a tester interface 306 that provides the hardware communication and data connections to the DUT/CUT. The tester 300 can also include a user interface (UI) subsystem 308 that facilitates visual and user interaction therewith. The UI 308 can be an LCD monitor, a plasma monitor, or any suitable display, for example. Each of the subsystems (104, 106, 302, 304, 306, and 308) is interconnected by an internal communication bus 310, according to conventional communication schemes. Note that the UI 308 can be an external monitor that interfaces to the tester 300 via the tester interface 306 for providing a means of perceiving data and control information of the tester subsystems. The tester interface 306 can also accommodate user input devices, such as a wired/wireless keyboard, mouse, trackball, etc., to allow the user to interact therewith; Column 4 Line 57-67 & Column 5 Line 1-14; therefore the sample provider [308]+304 configured to continuously receive the feedback configuration and to dynamically generate the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gershon ‘781 B1 in view of Nentwig in the US patent Application Publication Number US 20090192738 A1.
Regarding claim 14, Gershon fails to teach a system, wherein the waveform generator is configured to receive the waveform information in the form of an IQ data stream, wherein the waveform generator is configured to dynamically adjust the RF output signal based on the IQ data stream.
Nentwig teaches a method and apparatus and, in particular but not exclusively, to a method for calibrating power amplifiers for use in a device in a telecommunications system (Paragraph [0001] Line 1-4), wherein
the waveform generator [1] in Figure 2 is configured to receive the waveform information in the form of an IQ data stream [4] [S.sub.ref], wherein the waveform generator is configured to dynamically adjust the RF output signal [s.sub.out] based on the IQ data stream (An IQ data stream representing a modulated signal, S.sub.ref, is uploaded to an IQ signal source 4 in an RF signal generator 1 with arbitrary waveform generation capabilities. The signal is upconverted to a radio frequency in quadrature upconverter 5, and then applied to an input of the device under test 2. The maximum output power level at the output of power amplifier 2 should correspond to the highest output power at that node required to meet the maximum power requirement of the relevant radio standard. The signal at the output of the power amplifier 2 is then applied to an input of a RF vector signal analyzer 3. The signal is down converted in quadrature downconverter 6 and sampled and stored in IQ data storage 7 in the RF vector signal analyzer 3 resulting in a stream of output samples s.sub.out; Paragraph [0056] Line 4-17). The purpose of doing so is to align the sample streams is FFT (Fast Fourier Transform) correlation, to allow a cross correlation coefficient between the transmitted and received signal to be calculated in order to find the optimum signal alignment, when the absolute timing between the transmitted and received signals is unknown and to correctly predistort the input signal, the distortion due to the amplifier must be known. Accurate determination of the distortion characteristics of the amplifier allows more effective linearization of the amplifier using predistortion.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Gershon in view of Nentwig, because Nentwig teaches to receive the waveform information in the form of an IQ data stream aligns the sample streams is FFT (Fast Fourier Transform) correlation, allows a cross correlation coefficient between the transmitted and received signal to be calculated in order to find the optimum signal alignment, when the absolute timing between the transmitted and received signals is unknown (Paragraph [0058]), correctly predistorts the input signal, the distortion due to the amplifier must be known. Accurate determination of the distortion characteristics of the amplifier allows more effective linearization of the amplifier using predistortion (Paragraph [0006]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
SUN et al. (US 20200355738 A1) discloses, “APPARATUS AND METHOD OF TESTING ELECTRONIC COMPONENTS-[0001] The present disclosure relates generally to an apparatus of testing electronic components and a method of testing electronic components. [0026] FIG. 1 illustrates a schematic view of an apparatus for testing electronic components in accordance with some embodiments of the present disclosure. The apparatus 1 can be used in the failure analysis of an integrated device/electronic component. The apparatus 1 can be used in the automatic test of an integrated device/electronic component. [0027] The apparatus 1 includes a computing device 2, a controlling device 4, a testing device 6 and a load board 8. One or more electronic connections exist between the computing device 2 and the controlling device 4. One or more electronic connections exist between the controlling device 4 and the testing device 6. One or more electronic connections exist between the testing device 6 and the load board 8. [0028] The computing device 2 includes a processing unit 10 and a memory unit 12. [0029] The processing unit 10 may include but is not limited to, for example, a central processing unit (CPU), a microprocessor, an application-specific instruction set processor (ASIP), a machine control unit (MCU), a graphics processing unit (GPU), a physics processing unit (PPU), a digital signal processor (DSP), an image processor, a coprocessor, a storage controller, a floating-point unit, a network processor, a multi-core processor, a front-end processor or the like. The processing unit 10 can be electrically connected to the memory unit 12. [0030] The memory unit 12 may include but is not limited to a random-access memory (RAM) such as a static RAM (SRAM) or a dynamic RAM (DRAM). In some embodiments, the memory unit 12 may include a read-only memory (ROM). The memory unit 12 may include a cache (not shown) for storing data that have recently been accessed, so that future requests for that data can be served faster. The data stored in the cache may include the result of an earlier computation of the processing unit 10. The data stored in the cache may include a copy of data stored in the memory unit 12. 0044] FIG. 2A illustrates a perspective view of a device under test (DUT) in accordance with some embodiments of the present disclosure. Referring to FIG. 2A, the DUT 28 includes eight pins. It can be contemplated that the DUT 28 may include more pins or less pins. During the failure analysis or the automatic test, one or more test signals/commands may be provided to the DUT 28. In some embodiments, a signal S1 is provided to the DUT 28 and a signal S2 is provided to the DUT 28. The DUT 28 generates an output signal (or feedback signal) Z in response to the signal S1 and the signal S2-However Sun does not disclose wherein the processor comprises a feedback interpreter configured to generate and/or update a feedback configuration based on the feedback signal, wherein the feedback configuration comprises a number of consecutive segments, wherein each segment references or comprises a part of a respective stored or calculated waveform sample having a determined duration.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
