Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/06/2025, 12/20/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawing is objected to because they fail to label the element boxes in Figures 1 and 4. Without some indication as to the content of the boxes (or preferably symbols of the actual elements) it is not clear as to what the elements are and they are not explanatory to a reader as a quick method of determining the general background of the invention. See MPEP 608.02 and 37 CFR 1.84 (o) -- Legends --
Suitable descriptive legends may be used, or may be required by the Examiner, where necessary for understanding of the drawing, subject to approval by the Office. They should contain as few words as possible.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the elements in Figure 1 and 4 as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because:
The opening sentence “The disclosure relates to a system for testing a device-under-test, DUT.” is improper.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 Line 3-4 recites, “said further waveform samples in in the memory” should read “said further waveform samples in the memory”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a processing unit” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
In this application in claim 1 the recited “a processing unit” coupled with the functional language “to dynamically generate waveform information based on the received feedback signal”.
All these limitations in claim 1 have no structural meaning and are considered a generic placeholder.
In the present application (PGPUB NO: US 20250258215 A1) discloses:
In Paragraph 15, 56, 58 and 61, “[0015] The processing unit can comprise or be formed by a digital signal processor (DSP).
[0056] The processing unit can comprise one or more microprocessors of the system 10.
[0058] The processing unit 14 can comprise a feedback interpreter 15.
[0061] The processing unit 14 can further comprises a feedback configurator 16.”
35 USC § 112(b) Rejections
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It appears that claims 16-20 should have been rejected under 35 USC 112(b).
Referring to claim 16, it appears that the claim has recited insufficient structure for performing the recited method of having "two states," namely, " generating an RF output signal and forwarding said RF output signal to a DUT; receiving a feedback signal from the DUT; dynamically generating waveform information". Paragraphs 48 of the specification teach that the system 10 provides the structure corresponding the method steps, however, claim 1 only includes RF output signal and DUT. Consequently, the claim does not appear to recite the requisite structure for performing the claimed method. As such, the boundaries of the language are unclear because the claim does not provide a discernable boundary on what structure performs the method. The recited method does not follow from the structure recited in the claim, i.e., the generating and receiving, so it is unclear whether the method requires some other structure or is simply a result of operating the DUT. Thus, one of ordinary skill would not be able to draw a clear boundary between what is and is not covered by the claim. See MPEP 2173.05(g).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 and 15-20 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Gershon et al. (Hereinafter, “Gershon”) in the US Patent Number US 7072781 B1.
Regarding claim 1, Gershon teaches a system for testing a device-under-test, DUT [112/114] (a test system that is a tool for investigating device behavior or circuit behavior; Column 1 Line 60-61; FIG. 1 illustrates a test system in accordance with the present invention; Column 2 Line 42-43), comprising:
an output port (Figure 1: Modified Figure 1 of Gershon below shows an output port for being connected to the DUT 112) arranged for being connected to the DUT [112] (Referring now to FIG. 1, there is illustrated a test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114; Column 3 Line 60-65);
a waveform generator [116] (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104. The AWG 104 includes a waveform generator 116 that outputs the waveform 110; Column 3 Line 60-67 & Column 4 Line 1-2) configured to generate an RF output signal [110] and to forward said RF output signal to the DUT [112] via the output port (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT; Column 4 Line 1-10; An arbitrary waveform generator (AWG) can indeed be used to generate radio frequency (RF) signals);
a communication interface [108] in Figure 1 (feedback loop 108 as the communication interface as it communicated the signal from the DUT to the DAS)/ [306] in Figure 3 (a tester interface 306 that provides the hardware communication and data connections to the DUT/CUT; Column 4 Line 66-67 & Column 5 Line 1) (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 60-67 & Column 4 Line 1) configured to receive a feedback signal from the DUT [112] (feedback look 108 receives signal from the DUT 112 and transfers to the DAS 106; Figure 1: Modified Figure 1 of Gershon below shows a communication interface [108] receives a feedback signal from the DUT [112]); and
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Figure 1: Modified Figure 1 of Gershon
a processing unit [106]/Figure 3 (Figure 3 shows the detail of the processing unit comprising elements 302+106+304+308+306) (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108; Column 3 Line 60-64; Referring now to FIG. 3, there is illustrated a more detailed block diagram of a tester 300; Column 4 Line 57-58) configured to dynamically generate waveform information based on the received feedback signal, wherein the processing unit is configured to generate the waveform information from stored and/or from real time calculated waveform samples (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106. The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 3 Line 60-67 & Column 4 Line 1-16);
wherein the waveform generator [116] is configured to adjust the RF output signal [110] based on the waveform information (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 1-20).
Regarding claim 2, Gershon teaches a system,
wherein the processing unit comprises a feedback interpreter [ 106] (configured to generate and/or update a feedback configuration based on the feedback signal (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1),
wherein the feedback configuration comprises a number of consecutive segments (selection and calibration) (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16), wherein each segment references or comprises a part of a respective stored or calculated waveform sample (the output waveform 110 in small slices (or segments)) having a determined duration (The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 5-20).
Regarding claim 3, Gershon teaches a system,
wherein the processing unit comprises a feedback configurator configured to map, for each segment (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16; preassembled slices are the mapping of each segment),
the feedback signal to the respective part of the stored or calculated waveform sample based on a mapping rule and to forward said mapping to the feedback interpreter (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 13-20; Claim 20. A method of testing a device, comprising: defining an output signal in advance of the test; providing a set of base waveforms in a memory; defining initial settings of a test waveform to be applied to the device; slicing the set of base waveforms into waveform slices; assembling selected waveform slices in a sequence to form the test waveform; choosing events that trigger switching from one slice of a sequence to another slice of a sequence during test; applying the test waveform to the device during a test phase; and changing the test waveform in response to a measured change in the device);
wherein the feedback interpreter is configured to generate the feedback configuration based on said mapping (Claim 28. A system that facilitates testing a cell, comprising: means for defining an output signal in advance of the test; means for providing a set of base waveforms in a memory; means for slicing the set of base waveforms into waveform slices; means for determining a sequence of the waveform slices that constitute a test waveform; means for selecting one or more events that trigger switching from one slice to a next slice; means for assembling selects ones of the waveform slices to form the test waveform; means for applying the test waveform to the cell during a test phase; and means for changing the test waveform in response to a measured change in the cell during the test phase; means for set of slicing is a kind of mapping as claim does not recite any specific mapping process).
Regarding claim 4, Gershon teaches a system,
wherein the feedback configurator [106] is configured to calculate at least one waveform sample based on the feedback message in real time (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1; As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT (in real time). For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110; Column 4 Line 8-12).
Regarding claim 5, Gershon teaches a system,
wherein the processing unit [106]/ [302, 304, 306, and 308] further comprises a sample provider [304+308] (user interface 308 as the sample provider as it functions as external monitor that interfaces to the tester 300 via the tester interface 306 for providing a means of perceiving data and control information of the tester subsystems) configured to continuously receive the feedback configuration and to dynamically generate the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration (Referring now to FIG. 3, there is illustrated a more detailed block diagram of a tester 300. The tester 300 includes the AWG subsystem 104 to control output of the waveform, the waveform manager subsystem 116 that processes the waveform according to changed DUT/CUT parameters, the DAS subsystem 106 that connects to the DUT/CUT to receive parameter signals during the test operation, a processor subsystem 302 that facilitates control and interaction of tester subsystems, a trigger system 304 that facilitates event triggering, and a tester interface 306 that provides the hardware communication and data connections to the DUT/CUT. The tester 300 can also include a user interface (UI) subsystem 308 that facilitates visual and user interaction therewith. The UI 308 can be an LCD monitor, a plasma monitor, or any suitable display, for example. Each of the subsystems (104, 106, 302, 304, 306, and 308) is interconnected by an internal communication bus 310, according to conventional communication schemes. Note that the UI 308 can be an external monitor that interfaces to the tester 300 via the tester interface 306 for providing a means of perceiving data and control information of the tester subsystems. The tester interface 306 can also accommodate user input devices, such as a wired/wireless keyboard, mouse, trackball, etc., to allow the user to interact therewith; Column 4 Line 57-67 & Column 5 Line 1-14; therefore the sample provider [308]+304 configured to continuously receive the feedback configuration and to dynamically generate the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration).
Regarding claim 6, Gershon teaches a system, further comprising:
a memory configured to store the stored waveform samples (The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106). Fast ADC (analog-to-digital converter) devices and DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) using existing off-the-shelf components; Column 4 Line 16-23; Claim 9. The system of claim 1, further comprising a memory that stores standard waveforms that are used to generate the output signal).
Regarding claim 7, Gershon teaches a system,
wherein the memory is a shared memory in a communication network ((101) The basic waveforms can be stored in the shape 1606 memory with standard offsets and amplitudes. This part of memory can be a ROM (Read-Only Memory). During the initialization of the system, the logic extracts the series of slices that are selected by the user, adjusts their amplitudes, offsets or slopes, and stores them in the Sample Buffer 1618 at the correct locations dictated by their sequencing; Column 17 Line 46-52; In hardware, shared memory refers to a block of random access memory (RAM) that can be accessed by several different central processing units (CPUs) in a multiprocessor computer system.
https://www.bing.com/search?q=is%20RAM%20shared%20memory&qs=n&form=QBRE&sp=-1&ghc=1&lq=0&pq=is%20ram%20shared%20memory&sc=9-20&sk=&cvid=E601DB93C16B401BA8A0A3155E937BDE; Therefore the memory disclosed by Gershon in Figure 16 can be a Rom and can be a shared memory).
Regarding claim 8, Gershon teaches a system,
wherein the system further comprises an access unit [1618] (buffer 1618 as the access unit as it access from the memory) for accessing the memory and to forward the parts of the stored waveform samples from the memory to the sample provider (The digital blocks assemble the slices into a continuous waveform sampled at, for example, 100 Msps. The rules of assembly have been described hereinabove and are based on user selections (made off-line during initialization) and the trigger signals received from the DAS. Throughout the signal path, which includes Waveform Control, MUX, Digital Adjust, Sample Buffer and the DAC, the sampling rate is supplied by the SRCLK signal (e.g., 100 Msps). The triggering functions and associated outputs need to be faster than the sample time (in this example on the order of 1 2 nsec maximum), in order to minimize uncertainty in the waveform and efficiently protect the DUT/CUT (e.g., a cell) from over current and power; Column 16 Line 57-67 & Column 17 Line 1; The basic waveforms can be stored in the shape 1606 memory with standard offsets and amplitudes. This part of memory can be a ROM (Read-Only Memory). During the initialization of the system, the logic extracts the series of slices that are selected by the user, adjusts their amplitudes, offsets or slopes, and stores them in the Sample Buffer 1618 at the correct locations dictated by their sequencing. Some adjustments of amplitude or offset can be made on the fly by the signal path circuits. At any trigger input, the signal path logic will be ready to move to the next slice, make the necessary adjustments to it, and deliver the samples to the DAC 1622. Both the DAC 1622 and the output amplifier 1626 are off-the-shelf components. The amplifier/filter has a fixed gain. To meet the relatively high voltage output and current drive requirements, the last stage is designed with discrete components; Column 17 Line 46-61).
Regarding claim 9, Gershon teaches a system,
wherein the access unit is further configured to receive further waveform samples of different duration and/or with different characteristics and to store said further waveform samples in the memory (The basic waveforms can be stored in the shape 1606 memory with standard offsets and amplitudes. This part of memory can be a ROM (Read-Only Memory). During the initialization of the system, the logic extracts the series of slices that are selected by the user, adjusts their amplitudes, offsets or slopes, and stores them in the Sample Buffer 1618 at the correct locations dictated by their sequencing. Some adjustments of amplitude or offset can be made on the fly by the signal path circuits. At any trigger input, the signal path logic will be ready to move to the next slice, make the necessary adjustments to it, and deliver the samples to the DAC 1622. Both the DAC 1622 and the output amplifier 1626 are off-the-shelf components. The amplifier/filter has a fixed gain. To meet the relatively high voltage output and current drive requirements, the last stage is designed with discrete components; Column 17 Line 46-61).
Regarding claim 10, Gershon teaches a system,
wherein the communication interface is a wireless or wire-bound interface (The tester interface 306 can also accommodate user input devices, such as a wired/wireless keyboard, mouse, trackball, etc., to allow the user to interact therewith; Column 5 Line 11-14).
Regarding claim 11, Gershon teaches a system,
wherein the communication interface is a serial interface configured to receive the feedback signal with a serial data rate (The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106). Fast ADC (analog-to-digital converter) devices and DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) using existing off-the-shelf components; Column 4 Line 5-23; DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) and DAC is one component of the waveform generator and therefore the communication interface is a serial interface configured to receive the feedback signal with a serial data rate).
Regarding claim 12, Gershon teaches a system,
wherein the waveform generator [104] comprises an IQ sample streamer (not required by the claim) and/or a digital-to-analog, DAC, converter (The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106). Fast ADC (analog-to-digital converter) devices and DAC (digital-to-analog converter) devices allow speeds up to one giga-samples per second (Gsps) using existing off-the-shelf components; Column 4 Line 16-23).
Regarding claim 13, Gershon teaches a system,
wherein the waveform generator and the processing unit are integrated in a common device [102] (tester 102 as the common device) (The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108; Column 3 Line 61-64), or
wherein the waveform generator is a standalone device (not required by the claim).
Regarding claim 15, Gershon teaches a system,
wherein the system [100] is an RF signal generator [116] (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT; Column 4 Line 1-10; An arbitrary waveform generator (AWG) can indeed be used to generate radio frequency (RF) signals therefore it can be a RSF signal generator).
Regarding claim 16, Gershon teaches a method for testing a device-under-test, DUT [112/114] (a test system that is a tool for investigating device behavior or circuit behavior; Column 1 Line 60-61; FIG. 1 illustrates a test system in accordance with the present invention; Column 2 Line 42-43), comprising:
generating an RF output signal [110] (Referring now to FIG. 1, there is illustrated a test system 100 in accordance with the present invention. The test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104. The AWG 104 includes a waveform generator 116 that outputs the waveform 110; Column 3 Line 60-67 & Column 4 Line 1-2) and forwarding said RF output signal [110] to a DUT [112] (Referring now to FIG. 1, there is illustrated a test system 100 comprises a tester 102 that includes an arbitrary waveform generator (AWG) 104 and a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114; Column 3 Line 60-65) (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT; Column 4 Line 1-10; An arbitrary waveform generator (AWG) can indeed be used to generate radio frequency (RF) signals);
receiving a feedback signal from the DUT [112] (feedback loop 108 receives signal from the DUT 112 and transfers to the DAS 106; Figure 1: Modified Figure 1 of Gershon above shows a communication interface [108] receives a feedback signal from the DUT [112]);
dynamically generating waveform information based on the received feedback signal, wherein the waveform information is generated from stored and/or from real time calculated waveform samples (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106. The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 3 Line 60-67 & Column 4 Line 1-16); and
adjusting the RF output signal [110] based on the waveform information (The AWG 104 includes a waveform generator 116 that outputs the waveform 110 in accordance with initial configuration parameters, which initial parameters can then be adjusted dynamically as the test on the DUT/CUT proceeds. The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 1-20).
Regarding claim 17, Gershon teaches a method, further comprising:
generating and/or updating a feedback configuration based on the feedback signal (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1),
wherein the feedback configuration comprises a number of consecutive segments (selection and calibration) (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16), wherein each segment references or comprises a part of a respective stored or calculated waveform sample (the output waveform 110 in small slices (or segments)) having a determined duration (The generator 116 builds the output waveform 110 in small slices (or segments) that are assembled together through a process of selection and calibration. As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT. For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110. The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 5-20).
Regarding claim 18, Gershon teaches a method,
mapping, for each segment (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110; Column 4 Line 13-16; preassembled slices are the mapping of each segment), the feedback signal to the respective part of the stored or calculated waveform sample based on a mapping rule and to forward said mapping to the feedback interpreter (The feedback architecture facilitates a number of changes in the output waveform 110, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform 110. The system tester 102 is built as a combination of fast analog and digital circuits, programmable logic for user interface and settings, and waveform memory (on both the AWG 104 and DAS 106); Column 4 Line 13-20; Claim 20. A method of testing a device, comprising: defining an output signal in advance of the test; providing a set of base waveforms in a memory; defining initial settings of a test waveform to be applied to the device; slicing the set of base waveforms into waveform slices; assembling selected waveform slices in a sequence to form the test waveform; choosing events that trigger switching from one slice of a sequence to another slice of a sequence during test; applying the test waveform to the device during a test phase; and changing the test waveform in response to a measured change in the device);
wherein the feedback interpreter is configured to generate the feedback configuration based on said mapping (Claim 28. A system that facilitates testing a cell, comprising: means for defining an output signal in advance of the test; means for providing a set of base waveforms in a memory; means for slicing the set of base waveforms into waveform slices; means for determining a sequence of the waveform slices that constitute a test waveform; means for selecting one or more events that trigger switching from one slice to a next slice; means for assembling selects ones of the waveform slices to form the test waveform; means for applying the test waveform to the cell during a test phase; and means for changing the test waveform in response to a measured change in the cell during the test phase; slicing the set of waveform is the mapping as claim does not specifically recites what is mapping and how mapping is done).
Regarding claim 19, Gershon teaches a method,
calculating at least one waveform sample based on the feedback message in real time (a data acquisition system (DAS) 106 connected through a feedback loop 108 that enables the AWG 104 to change its output waveform 110 on-the-fly based on the status of a device under test (DUT) 112 or circuit under test (CUT) 114 that is being monitored by the DAS 106; Column 3 Line 63-67 & Column 4 Line 1; As the waveform 110 is imposed on the DUT/CUT, the DAS 106 monitors one or more parameters of the DUT/CUT (in real time). For example, the DUT/CUT could manifest a certain current or voltage (or other parameter or combination of parameters) that requires a change in the waveform 110; Column 4 Line 8-12).
Regarding claim 20, Gershon teaches a method,
continuously receiving the feedback configuration and dynamically generating the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration (Referring now to FIG. 3, there is illustrated a more detailed block diagram of a tester 300. The tester 300 includes the AWG subsystem 104 to control output of the waveform, the waveform manager subsystem 116 that processes the waveform according to changed DUT/CUT parameters, the DAS subsystem 106 that connects to the DUT/CUT to receive parameter signals during the test operation, a processor subsystem 302 that facilitates control and interaction of tester subsystems, a trigger system 304 that facilitates event triggering, and a tester interface 306 that provides the hardware communication and data connections to the DUT/CUT. The tester 300 can also include a user interface (UI) subsystem 308 that facilitates visual and user interaction therewith. The UI 308 can be an LCD monitor, a plasma monitor, or any suitable display, for example. Each of the subsystems (104, 106, 302, 304, 306, and 308) is interconnected by an internal communication bus 310, according to conventional communication schemes. Note that the UI 308 can be an external monitor that interfaces to the tester 300 via the tester interface 306 for providing a means of perceiving data and control information of the tester subsystems. The tester interface 306 can also accommodate user input devices, such as a wired/wireless keyboard, mouse, trackball, etc., to allow the user to interact therewith; Column 4 Line 57-67 & Column 5 Line 1-14; therefore the sample provider [308]+304 configured to continuously receive the feedback configuration and to dynamically generate the waveform information based on the parts of the stored or calculated waveform samples referenced in or comprised by the consecutive segments in the feedback configuration).
.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gershon ‘781 B1 in view of Nentwig in the US patent Application Publication Number US 20090192738 A1.
Regarding claim 14, Gershon fails to teach a system, wherein the waveform generator is configured to receive the waveform information in the form of an IQ data stream, wherein the waveform generator is configured to dynamically adjust the RF output signal based on the IQ data stream.
Nentwig teaches a method and apparatus and, in particular but not exclusively, to a method for calibrating power amplifiers for use in a device in a telecommunications system (Paragraph [0001] Line 1-4), wherein
the waveform generator [1] in Figure 2 is configured to receive the waveform information in the form of an IQ data stream [4] [S.sub.ref], wherein the waveform generator is configured to dynamically adjust the RF output signal [s.sub.out] based on the IQ data stream (An IQ data stream representing a modulated signal, S.sub.ref, is uploaded to an IQ signal source 4 in an RF signal generator 1 with arbitrary waveform generation capabilities. The signal is upconverted to a radio frequency in quadrature upconverter 5, and then applied to an input of the device under test 2. The maximum output power level at the output of power amplifier 2 should correspond to the highest output power at that node required to meet the maximum power requirement of the relevant radio standard. The signal at the output of the power amplifier 2 is then applied to an input of a RF vector signal analyzer 3. The signal is down converted in quadrature downconverter 6 and sampled and stored in IQ data storage 7 in the RF vector signal analyzer 3 resulting in a stream of output samples s.sub.out; Paragraph [0056] Line 4-17). The purpose of doing so is to align the sample streams is FFT (Fast Fourier Transform) correlation, to allow a cross correlation coefficient between the transmitted and received signal to be calculated in order to find the optimum signal alignment, when the absolute timing between the transmitted and received signals is unknown and to correctly predistort the input signal, the distortion due to the amplifier must be known. Accurate determination of the distortion characteristics of the amplifier allows more effective linearization of the amplifier using predistortion.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Gershon in view of Nentwig, because Nentwig teaches to receive the waveform information in the form of an IQ data stream aligns the sample streams is FFT (Fast Fourier Transform) correlation, allows a cross correlation coefficient between the transmitted and received signal to be calculated in order to find the optimum signal alignment, when the absolute timing between the transmitted and received signals is unknown (Paragraph [0058]), correctly predistorts the input signal, the distortion due to the amplifier must be known. Accurate determination of the distortion characteristics of the amplifier allows more effective linearization of the amplifier using predistortion (Paragraph [0006]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Vahey et al. (US 10749618 B1) discloses, “Methods Of Closed-loop Control Of A Radio Frequency (RF) Test Environment Based On Machine Learning- systems, radio frequency (RF) testing may be performed in a setup that includes components such as an RF generator and a device under test (DUT). In order to emulate real-word testing of the DUT, a number of different RF waveforms may be used by the RF generator. In such testing, latency requirements related to switching between RF waveforms may be challenging, in some cases (Column 1 Line 17-23). FIG. 1 illustrates an example system 100 and example scenarios 110, 120 in accordance with some embodiments. Embodiments are not limited to the name, number, type, arrangement and/or other aspects of the components shown in FIG. 1. The scenarios 110 and 120 illustrate non-limiting example scenarios. It is understood that embodiments are not limited to these scenarios, as other scenarios are possible. In some embodiments, one or more of the techniques, operations, and/or methods described herein may be applicable to the scenario 110, the scenario 120 and/or other scenarios. Although some techniques, operations and/or methods may be described herein in terms of one of the scenarios 110, 120, the scope of embodiments is not limited to the scenarios 110, 120, as one or more of those techniques, operations and/or methods may be applicable to other scenarios (Column 1 Line 52-67). The system 100 may include a controller device 102, a radio frequency (RF) generator 104, and a device under test (DUT) 106. Example DUTs 106 may include, but are not limited to, a radar warning receiver (RWR), electronic intelligence (ELINT) device, a communication device, a radar device, or any device for which one or more tests are performed. Examples of test equipment setup goals, and/or test setup performance metrics may include, but are not limited to: the number of pulses per second that can be generated, power, time accuracy, phase accuracy, a number of simulated active emitters, the number of antennas on the DUT 106 capable of being driven, the number of simultaneous RF signals supported, and/or other(s). The goals, test metrics, and/or performance metrics related test result measurements may include, but are not limited to: ID accuracy, response accuracy, and/or other(s). In addition, the goals, test metrics, and/or performance metrics described above may be related to the DUT 106, the RF generator 104 and/or other component(s), although the scope of embodiments is not limited in this respect (Column 2 Line 1-21)-However Vahey does not disclose wherein the processing unit comprises a feedback interpreter configured to generate and/or update a feedback configuration based on the feedback signal, wherein the feedback configuration comprises a number of consecutive segments, wherein each segment references or comprises a part of a respective stored or calculated waveform sample having a determined duration.”
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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