DETAILED ACTION
The instant application having Application No. 18/990,844 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,174,776 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application and the corresponding patent document disclose a system for selecting a protocol where in a first protocol the system then selects the appropriate speed/bandwidth.
Instant Application 18/990,844
Patent Number US 12,174,776 B2
Claim 1
A system comprising: a controller;
and a storage device comprising a solid state drive (SSD) connected to the controller, wherein the storage device operates in a first protocol or a second protocol,
and wherein in the first protocol, the SSD of the storage device selects a first operating speed from among two or more operating speeds in the first protocol, the first operating speed of the SSD being above a minimum speed of the SSD in the first protocol.
Claim 1
A system comprising: a controller;
and a storage device comprising a solid state drive (SSD) connected to the controller via a mid-plane, wherein the storage device operates in a first protocol or a second protocol based on a first input received from the controller via one or more device ports over the mid-plane, and wherein in the first protocol, the SSD of the storage device selects a first operating speed from among two or more operating speeds above a predetermined threshold speed available during the first protocol based on a second input received from the controller via the one or more device ports.
Claim 2
wherein the storage device further comprises a field programmable gate array (FPGA) in communication with the SSD of the storage device via a connector and a bus.
Claim 2
wherein the storage device further comprises a field programmable gate array (FPGA) in communication with the SSD of the storage device via a connector and a bus.
Claim 3
wherein the connector is a SSD connector and the bus is a peripheral component interconnect express (PCIe) bus,
and wherein the storage device operates in the first protocol or the second protocol based on a first input received from the controller via one or more device ports over a mid-plane.
Claim 3
wherein the connector is a SSD connector and the bus is a peripheral component interconnect express (PCIe) bus.
Claim 1
A system comprising: a controller;
and a storage device comprising a solid state drive (SSD) connected to the controller via a mid-plane, wherein the storage device operates in a first protocol or a second protocol based on a first input received from the controller via one or more device ports over the mid-plane,
and wherein in the first protocol, the SSD of the storage device selects a first operating speed from among two or more operating speeds above a predetermined threshold speed available during the first protocol based on a second input received from the controller via the one or more device ports.
Claim 4
wherein the SSD is connected to the mid-plane via a small form factor (SFF) connector and the controller is a baseband management controller (BMC).
Claim 4
wherein the SSD is connected to the mid-plane via a small form factor (SFF) connector and the controller is a baseband management controller (BMC).
Claim 5
wherein the first input is determined by a physical pin on a chassis of a motherboard connected to the mid-plane or by an in-band command from the controller.
Claim 5
wherein the first input is determined by a physical pin on a chassis of a motherboard connected to the mid-plane or by an in-band command from the controller.
Claim 6
wherein the SSD of the storage device selects the first operating speed of the SSD from among the two or more operating speeds based on a second input from the mid-plane via the one or more device ports,
and wherein the second input is determined by one or more general-purpose input/output (GPIO) pins controlled by the controller or a local central processing unit (CPU) of a motherboard connected to the mid-plane, or one or more registers associated with the FPGA of the storage device.
Claim 4
wherein the SSD is connected to the mid-plane via a small form factor (SFF) connector and the controller is a baseband management controller (BMC).
Claim 6
wherein the second input is determined by one or more general-purpose input/output (GPIO) pins controlled by the controller or a local central processing unit (CPU) of a motherboard connected to the mid-plane, or one or more registers associated with a field programmable gate array (FPGA) of the storage device.
Claim 7
wherein the first protocol is a non-volatile memory express (NVMe) protocol and the second protocol is a NVMe over fabrics (NVMe-oF) protocol.
Claim 7
wherein the first protocol is a non-volatile memory express (NVMe) protocol and the second protocol is a NVMe over fabrics (NVMe-oF) protocol.
Claim 8
wherein the one or more device ports are connected to the storage device via a U.2 connector and the storage device operates in a high-availability (HA) mode.
Claim 8
wherein the one or more device ports are connected to the storage device via a U.2 connector and the storage device operates in a high-availability (HA) mode.
Claim 9
wherein the storage device supports, via the U.2 connector, one or more Serial Attached Small Computer System Interface (SAS) ports and one or more peripheral component interconnect express (PCIe) X4 lanes of a PCIe X4 bus, wherein the one or more SAS ports are used as one or more Fabric attached ports, and wherein the one or more Fabric attached ports comprise Ethernet ports, Fibre-channel ports, or InfiniBand ports.
Claim 9
wherein the storage device supports, via the U.2 connector, one or more Serial Attached Small Computer System Interface (SAS) ports and one or more peripheral component interconnect express (PCIe) X4 lanes of a PCIe X4 bus, wherein the one or more SAS ports are used as one or more Fabric attached ports, and wherein the one or more Fabric attached ports comprise Ethernet ports, Fibre-channel ports, or InfiniBand ports.
Claim 10
wherein in the second protocol, the storage device supports, via the U.2 connector, at least two PCIe X4 lanes of the one or more PCIe X4 lanes for control plane for the one or more Fabric attached ports and remaining PCIe X4 lanes of the one or more PCIe X4 lanes as additional Fabric attached ports.
Claim 10
wherein in the second protocol, the storage device supports, via the U.2 connector, at least two PCIe X4 lanes of the one or more PCIe X4 lanes for control plane for the one or more Fabric attached ports and remaining PCIe X4 lanes of the one or more PCIe X4 lanes as additional Fabric attached ports.
Claim 11
wherein the storage device further comprises a first storage device and a second storage device, wherein the first storage device or the second storage device operates in accordance with the first protocol or the second protocol at the first operating speed or at a second operating speed from the two or more operating speeds.
Claim 11
The system of claim 1, wherein the storage device further comprises a first storage device and a second storage device, wherein the first storage device or the second storage device operates in accordance with the first protocol or the second protocol at the first operating speed or at a second operating speed from the two or more operating speeds.
Claim 12
A method comprising: selecting, by a storage device comprising a solid state drive (SSD), a first operating protocol or a second operating protocol;
and in the first operating protocol, selecting, by the SSD of the storage device, a first operating speed of the SSD from among two or more operating speeds in the first operating protocol, wherein the first operating speed of the SSD is above a minimum speed of the SSD in the first operating protocol.
Claim 12
A method comprising: receiving, at a storage device comprising a solid state drive (SSD), a first input from a controller connected to the storage device via one or more device ports over a mid-plane, wherein the storage device operates in a first protocol or a second protocol based on the first input;
in the second protocol, receiving, at the storage device, a second input from the mid-plane via the one or more device ports; and selecting, by the SSD of the storage device, an operating speed of the storage device from among two or more operating speeds above a predetermined threshold speed available during the second protocol based on the second input.
Claim 13
wherein the storage device operates in the first operating protocol or the second operating protocol based on a first input received from a controller via one or more device ports over a mid-plane,
wherein the SSD of the storage device selects the first operating speed of the SSD from among the two or more operating speeds based on a second input from the mid-plane via the one or more device ports,
and wherein the SSD is connected to the mid-plane via a small form factor (SFF) connector and the controller is a baseband management controller (BMC).
Claim 12
A method comprising: receiving, at a storage device comprising a solid state drive (SSD), a first input from a controller connected to the storage device via one or more device ports over a mid-plane, wherein the storage device operates in a first protocol or a second protocol based on the first input; in the second protocol, receiving, at the storage device, a second input from the mid-plane via the one or more device ports;
and selecting, by the SSD of the storage device, an operating speed of the storage device from among two or more operating speeds above a predetermined threshold speed available during the second protocol based on the second input.
Claim 13
wherein the SSD is connected to the mid-plane via a small form factor (SFF) connector and the controller is a baseband management controller (BMC).
Claim 14
wherein the first input is determined by a physical pin on a chassis of a motherboard connected to the mid-plane or by an in-band command from the controller.
Claim 14
wherein the first input is determined by a physical pin on a chassis of a motherboard connected to the mid-plane or by an in-band command from the controller.
Claim 15
wherein the second input is determined by one or more general-purpose input/output (GPIO) pins controlled by the controller or a local central processing unit (CPU) of a motherboard connected to the mid-plane, or one or more registers associated with a field programmable gate array (FPGA) of the storage device, the FPGA being in communication with the SSD via a connector and a bus.
Claim 15
wherein the second input is determined by one or more general-purpose input/output (GPIO) pins controlled by the controller or a local central processing unit (CPU) of a motherboard connected to the mid-plane, or one or more registers associated with a field programmable gate array (FPGA) of the storage device, the FPGA being in communication with the SSD via a connector and a bus.
Claim 16
wherein the first operating protocol is a non-volatile memory express (NVMe) protocol and the second operating protocol is a NVMe over fabrics (NVMe-oF) protocol.
Claim 16
wherein the first protocol is a non-volatile memory express (NVMe) protocol and the second protocol is a NVMe over fabrics (NVMe-oF) protocol.
Claim 17
A storage device comprising: a solid state drive (SSD) in communication with a field programmable gate array (FPGA), wherein the storage device operates in a first protocol or a second protocol, and wherein in the first protocol, the SSD of the storage device selects a first operating speed from among two or more operating speeds in the first protocol, the first operating speed of the SSD being above a minimum speed of the SSD in the first protocol.
Claim 17
A storage device comprising: a solid state drive (SSD) in communication with a field programmable gate array (FPGA) via a first connector and a bus, wherein the storage device operates in a first protocol or a second protocol based on a first input received via a second connector, and wherein in the first protocol, the SSD of the storage device selects a first operating speed from among two or more operating speeds above a predetermined threshold speed available during the second protocol based on a second input received via the second connector.
Claim 18
wherein the SSD is connected to the FPGA via a first connector and a bus, wherein the storage device operates in the first protocol or the second protocol based on a first input received via a second connector, wherein the first input is received from a motherboard or a controller connected to the storage device via one or more device ports over a mid-plane, wherein the SSD of the storage device selects the first operating speed of the SSD from among the two or more operating speeds based on a second input from the mid-plane via the one or more device ports and the second input is received from the mid-plane via the one or more device ports,
wherein the first input is determined by a physical pin on a chassis of the motherboard or by an in-band command from the controller and the second input is determined by one or more general-purpose input/output (GPIO) pins controlled by the controller or a local central processing unit (CPU) of the motherboard, or one or more registers associated with the FPGA, and wherein the SSD is connected to the mid-plane via a small form factor (SFF) connector.
Claim 17
A storage device comprising: a solid state drive (SSD) in communication with a field programmable gate array (FPGA) via a first connector and a bus, wherein the storage device operates in a first protocol or a second protocol based on a first input received via a second connector, and wherein in the first protocol, the SSD of the storage device selects a first operating speed from among two or more operating speeds above a predetermined threshold speed available during the second protocol based on a second input received via the second connector.
Claim 18
wherein the first input is received from a motherboard or a controller connected to the storage device via one or more device ports over a mid-plane and the second input is received from the mid-plane via the one or more device ports, wherein the first input is determined by a physical pin on a chassis of the motherboard or by an in-band command from the controller and the second input is determined by one or more general-purpose input/output (GPIO) pins controlled by the controller or a local central processing unit (CPU) of the motherboard, or one or more registers associated with the FPGA, and wherein the SSD is connected to the mid-plane via a small form factor (SFF) connector.
Claim 19
wherein the first connector is a SSD connector, the bus is a peripheral component interconnect express (PCIe) bus, the second connector is a U.2 connector, and the first protocol is a non-volatile memory express (NVMe) protocol and the second protocol is a NVMe over fabrics (NVMe-oF) protocol.
Claim 19
wherein the first connector is a SSD connector, the bus is a peripheral component interconnect express (PCIe) bus, the second connector is a U.2 connector, and the first protocol is a non-volatile memory express (NVMe) protocol and the second protocol is a NVMe over fabrics (NVMe-oF) protocol.
Claim 20
wherein the storage device further comprises a first storage device and a second storage device, wherein the first storage device or the second storage device operates in accordance with the first protocol or the second protocol at the first operating speed or at a second operating speed from the two or more operating speeds.
Claim 20
wherein the storage device further comprises a first storage device and a second storage device, wherein the first storage device or the second storage device operates in accordance with the first protocol or the second protocol at the first operating speed or at a second operating speed from the two or more operating speeds.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated December 20, 2024, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.W.Y/Examiner, Art Unit 2181 March 5, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181