DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This office action is in response to the Application filed on 12/20/2024.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 9-11 and 14, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al. (US2022/0057954; hereinafter Cui) in view of Meyer (US 2022/0283975).
Regarding independent claims 1, 9 and 14,taking claim 14 as exemplary analysis, Cui teaches A data processing system (Fig. 1; [0056], A storage system provided in an embodiment includes a computing node cluster and a storage node cluster. The computing node cluster includes one or more computing nodes 100), comprising a computing node (Fig. 1, computing node 100) and a storage node (Fig. 1, storage node 20),
wherein the computing node comprises a first data processing unit (DPU) ([0056], The client 102 {first DPU} is configured to: receive a data access request triggered by the application 101, interact with a storage node 20, and send the data access request to the storage node 20. The client 102 is further configured to: receive data from the storage node, and forward the data to the application 101...Any client 102 in the computing node cluster may access any storage node 20 in the storage node cluster.)) and a central processing unit (CPU) ([0056], The computing node 100 is a computing device on a user side, such as a server or a desktop computer. In terms of hardware, a processor and a memory (which are not shown in FIG. 1) are disposed in the computing node 100; [0067], the applications may directly trigger a data write request or a data read request through a client in the storage node 20 to be processed by the storage node 20 or sent to another storage node 20 for processing),
the storage node comprises a second DPU ([0063], the storage node 20 has its own IO controller 22 that is configured to communicate with a computing node 100 and is further configured to communicate with another storage node;
Fig. 3 & [0064], the IO controller 22 includes a communication unit 220 and a computing unit 221 … The computing unit is a programmable electronic part, and is configured to perform calculation processing and the like on data. In this embodiment, a data processing unit (DPU) {second DPU}) and a storage (Fig. 2, Storage node comprises DRAM and SCM),
a communication link is established between the first DPU and the second DPU (Fig. 6, a communication link is between Client {first DPU} and IO controller {second DPU is in the IO controller}),
Although Cui teaches the first DPU send the data access request to the storage node ([0056], The client 102 {first DPU} is configured to: receive a data access request triggered by the application 101, interact with a storage node 20, and send the data access request to the storage node 20), and Cui teaches correspondence between each global address and a physical address of the global address is recorded in an index table as shown in [0072],
Cui does not expressly teach the first DPU stores memory address assignment information.
In an analogous art of memory control, Meyer teaches the first DPU stores memory address assignment information (Fig. 8B, wherein Description ring stores source address destination address mapping;
[0097], as shown in FIG. 8B, a DMA engine {DPU} may be located within Host A. The DMA engine may access memory locations and descriptor ring of its host, generate TLPs, and transmit the TLPs to the NT fabric using NT EP 1; [0101], the descriptor includes a base address, an address translation rule, and a destination partition. For example, the descriptor may indicate that data needs to be accessed at address range 1 of Host A, that the data needs to be transmitted/written to address range 2 of Host B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Cui and Meyer before them, to improve Cui’s index table with Meyer’s storing address mapping table in host node for the motivation that the host agent can perform the data movement by accessing memory address assignment information (Meyer, [0084], a descriptor ring (e.g., located on host A memory)).
The combination of Cui and Meyer further teaches the first DPU stores memory address assignment information that indicates a virtual memory address corresponding to a physical memory in the storage allocated by the storage node to the computing node (Cui, [0072], A correspondence between each global address and a physical address of the global address is recorded in an index table, and the management node synchronizes the index table to each storage node 20;
Meyer, [0084], The DMA engine process looks into the descriptor ring for a new entry, reads the source and destination addresses of the entry, and executes the data movement (e.g., moving TLP from the host memory to the NT EP BAR space, performing address translation/editing));
the CPU is configured to send a memory allocation request from a first service process to the first DPU (Cui, [0056], The client 102 {first DPU} is configured to: receive a data access request triggered by the application 101, interact with a storage node 20, and send the data access request to the storage node 20;
[0013], when receiving data write requests for these pages, the storage node allocates physical space from a storage device, writes to-be-written data into the physical space, and records a mapping relationship between global addresses and physical addresses of the pages in the index table),
wherein the first service process is a map process running on the CPU; the first DPU is configured to determine, based on the memory address assignment information and in the virtual memory address corresponding to the physical memory allocated by the storage node to the computing node, a virtual memory address range assigned to the first service process (
Meyer [0084], The DMA engine process looks into the descriptor ring for a new entry, reads the source and destination addresses of the entry, and executes the data movement (e.g., moving TLP from the host memory to the NT EP BAR space, performing address translation/editing));
the CPU is further configured to send a data storage request from the first service process to the first DPU, wherein the data storage request comprises first data and a first memory address, and the first memory address belongs to the virtual memory address range (Cui, Fig. 9 & [0081] S101: A computing node 100 sends a data write request to a storage node, where the data write request carries to-be-written data and a logical address of the to-be-written data);
the first DPU is configured to send a write data request to the second DPU over the communication link, wherein the write data request comprises the first data and the first memory address; the second DPU is configured to write the first data into the physical memory corresponding to the first memory address; and the second DPU is further configured to send a write data response to the first DPU over the communication link, wherein the write data response indicates that the first data is successfully written (Cui, [0089], When sending the data write request, the computing node may select a global address of a free page, and include the global address in the data write request. Specifically, after completing execution of a data write request, the storage node 20 sends a response message to the computing node 100. The computing node 100 may mark, in the bitmap based on the response message, a global address (set to “1”) of a page corresponding to the request. After receiving the data write request, a communication unit 220 of the storage node 20 stores the data write request in a DRAM 222)
Regarding Claims 2, 10 and 16, the combination of Cui and Meyer further teaches
wherein after the sending, by the first DPU, a write data request to the second DPU over the communication link, the method further comprises: in response to determining the first DPU receives a write data response from the second DPU over the communication link and the write data response indicates that the first data is successfully written, sending, by the first DPU, a data storage response to the first service process, wherein the data storage response indicates that the first data is successfully stored; and storing, by the first service process in a metadata service device, first metadata corresponding to the first data, wherein the first metadata comprises the first memory address (Cui, [0089], When sending the data write request, the computing node may select a global address of a free page, and include the global address in the data write request. Specifically, after completing execution of a data write request, the storage node 20 sends a response message to the computing node 100. The computing node 100 may mark, in the bitmap based on the response message, a global address (set to “1”) of a page corresponding to the request. After receiving the data write request, a communication unit 220 of the storage node 20 stores the data write request in a DRAM 222).
Regarding Claims 3, 11 and 17, the combination of Cui and Meyer further teaches wherein the method further comprises: when the first DPU receives a data read request from a second service process in the computing node, sending, by the first DPU, a read data request to the second DPU over the communication link, wherein the data read request comprises a second memory address, the second memory address is the virtual memory address corresponding to the physical memory of the storage node, the read data request comprises the second memory address, and the read data request is used for requesting the second DPU to read second data from the physical memory corresponding to the second memory address (Cui, Fig. 11 & [0102]-[0106], A computing node 100 sends a data read request to a storage node, where the data read request carries a logical address of to-be-read data, and an IO controller 22 of the storage node receives the data read request. In an application scenario of LUN semantics, the logical address includes a LUN ID, an LBA, and a length. In an application scenario of memory semantics, the logical address includes an ID, a start address, and a length of virtual space. After receiving the data read request, a communication unit 220 of the storage node stores the data write request in a DRAM 222; claim 5, receive a data read request from the computing node, wherein the data read request comprises the first logical address; identify the first global address based on the first logical address; identify, based on the index table, the first physical address corresponding to the first global address; and obtain the first data from the physical space indicated by the first physical address).
Allowable Subject Matter
Claims 4-8, 12-13, 15, 18-20 would be allowable pending on resolving the aforementioned double patenting rejection. The following is an examiner’s statement of reasons for allowance. The closest prior art identified:
Conclusion
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138