DETAILED ACTION
Claims 1 and 11 are amended. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/5/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (USPN: 2014/0013184) in view of Venkatakrishnan et al. (USPN: 10,496,777), hereinafter Venkatakrishnan, further in view of Jenkins et al. (USPN: 2013/0003475) hereinafter, Jenkins
As per claim 1, Takahashi teaches a method (see Fig. 3) for time borrowing in memory timing paths of a memory, comprising:
holding memory input data in a latch buffer (3) according to a core clock (CLK);
delaying the core clock (7) to generate a memory clock (CLKD);
feeding the memory input data from the latch buffer to a memory input (output of 4) of the memory according to the memory clock (CLKD); and
accessing a memory output of the memory according to the core clock (see CLK input to the output buffer (6)).
Takahashi does not teach delaying the core clock comprises introducing a delay sufficient to transfer positive setup slack from an output side of the memory to an input side of the memory. Venkatakrishnan, however, teaches about delaying the clock by borrowing time from the outside of the load (see Col. 11, line 53 – Col. 12, line 8 and Figs. 7B-7C). Accordingly, it would have been obvious to one of ordinary skills in the art to implement the teachings of Venkatakrishnan into the method of Takahashi to avoid any possible single/common clock challenges at slow memory compared to fast core clock.
As per claim 2, Takahashi further teaches that the memory comprising reading the memory output according to the core clock (CLK); and storing read data in a memory output buffer (6) (see Fig. 3).
As per claim 3, Takahashi further teaches about feeding the core clock (CLK) to a memory output buffer (6) (see Fig. 3).
As per claim 4, Takahashi further teaches that holding the memory input data comprises: reading the memory input from a memory input buffer (3) according to the core clock (CLK).
Although neither Takahashi nor Venkatakrishnan does not specifically teach, it is well-known in the computer art to store the memory input data in the latch buffer according to the core clock. Therefore, it would have been obvious to one of ordinary skill in the art to implement this step in the method taught by the combination of Takahashi and Venkatakrishnan to store/buffer the data multiple times to avoid disparity between the main core and memory clocks.
As per claim 5, Takahashi further teaches that the memory input data comprises a write/read address data (2), write data (3), and/or control signals (see Fig. 3).
As per claim 6, Takahashi teaches the memory (101 in Fig. 1 and 1 in Fig. 3) comprises a level-two (L2) and/or a level-three (L3) cache.
As per claim 8, Takahashi further teaches that delaying the core clock comprises latching the core clock (CLK) at one or more buffers (7) prior to a clock input of the memory (see Fig. 3).
As per claim 9, Takahashi further teaches that feeding the memory input data comprises completing setup of the memory input data within a single clock cycle of the memory clock (see Fig. 4).
As per claim 10, Takahashi and Venkatakrishnan teaches the claimed invention as described above but failed to teach about performing a read data setup check at the output of the memory prior to an input data setup check at input pins of the memory. However, this an old and well-known memory behavior known as ‘read-before-write’ (also known as ‘old data’ behavior), where memory first returns the value currently stored at an address prior to the new data is written to the same address. In other words, if the read and write commands to the same address are issued simultaneously, the output shows the previous value, not the newly written one that way it guarantees the access to the old value at that address before it gets overwritten by new value. Therefore, it would have been obvious to one of ordinary skills in the art at the time of the current invention was made to apply ‘read-before-write’ technique in the method taught by the combination of Takahashi and Venkatakrishnan to avoid missing the data by getting it overwritten by the new one.
Claims 11-16 and 18-20 are directed to a non-transitory computer-readable medium having a program code stored on it when executed on a processor performs steps of known method claims 1-6 and 8-10, respectively. It would have been obvious to one of ordinary skills in the art at the time of the current invention was made to implement the known method via a processor.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Venkatakrishnan, further in view of Jenkins et al. (USPN: 2013/0003475) hereinafter, Jenkins.
As per claim 7, the combination of Takahashi and Venkatakrishnan teaches the claimed invention as described above but failed to teach the further limitation of performing a read data setup check in two clock cycles of the core clock.
Jenkins, however, teaches setting the read data setup check to two clock cycles (see [0064]-[0068] and Fig. 5). It would have been obvious to one of ordinary skills in the art at the time of the current invention was made to implement Jenkin’s teaching in the method taught by the combination of Takahashi and Venkatakrishnan so data from slow memory can be read and to avoid slowing the entire chip clock.
Claims 17 are directed to a non-transitory computer-readable medium having a program code stored on it when executed on a processor performs steps of known method claim 7. It would have been obvious to one of ordinary skills in the art at the time of the current invention was made to implement the known method via a processor.
Conclusion
Claims 1-20 are rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Hetul Patel/
Supervisory Patent Examiner
Art Unit 3992
Prosecution Insights