DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim interpretation under 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claim limitations in claims 19 and 20 have been interpreted under 35 U.S.C. 112(f), because they use a generic placeholder “means for” coupled with functional language. Claim limitations in claims 19 and 20 have been interpreted to cover the corresponding structure described in the specification and Fig. 2 that achieve the claimed function, and equivalents thereof.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 11, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1).
Consider claims 1, 11 and 19:
Pagano discloses a system for decoding a pulse width modulation (PWM) signal transmitted through a channel (see Fig. 10 and paragraph 0082, where Pagano describes a pulse width modulator (PWM) 314), the system comprising:
a pulse modulator configured to generate a PWM signal, wherein the PWM signal is selected from four modulation levels (see Fig. 10 and paragraph 0082, where Pagano describes that the pulse width modulator (PWM) 314 provides a PWM signal 366 having a first voltage level 394 and a second voltage level 396);
a decoder including an AC detector and a DC detector (see paragraph 0027, where Pagano describes a decoder in a receiver);
a channel configured to transmit the PWM signal from the pulse modulator to the decoder (see paragraph 0027, where Pagano describes that signals are transmitted through a channel and the decoder is a channel decoder);
the AC detector configured to detect an alternating current (AC) component of the PWM signal (see Fig. 11 and paragraph 0088, where Pagano describes that the PWM signal is received through switch module 302; see Fig. 11 and paragraph 0089, where Pagano describes that a high pass filter module 1104 provides alternating current (AC) component 1166 by filtering out DC component 1164 from the PWM signal received from the switch module 302); and
the DC detector configured to detect a direct current (DC) component of the PWM signal (see Fig. 11 and paragraph 0088, where Pagano describes that a lower pass filter 1102 provides a direct current (DC) component 1152 from the PWM signal received from the switch module 302).
As discussed above, Pagano discloses that the PWM signal is selected from two modulation levels (see Fig. 10 and paragraph 0082, where Pagano describes that the PWM signal 366 has a first voltage level 394 and a second voltage level 396).
Pagano does not specifically disclose: the PWM signal is selected from four modulation levels.
Choi teaches: a PWM signal is selected from four modulation levels (see Fig. 3 and paragraph 0041, where Choi describes a multi-level signal which is generated based on 4-level pulse width modulation).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the PWM signal is selected from four modulation levels, as taught by Choi to modify the method of Pagano in order to receive two data bits during one data transmission period, as discussed by Choi (see paragraph 0041).
Consider claims 2 and 12:
Pagano in view of Choi discloses the invention of claims 1 and 11 above. Pagano discloses: a high pass filter configured to filter the transmitted PWM signal to separate the AC component from the DC component of the PWM signal (see Fig. 11 and paragraph 0089, where Pagano describes that a high pass filter module 1104 provides alternating current (AC) component 1166 by filtering out DC component 1164 from the PWM signal received from the switch module 302); and a low pass filter configured to filter the transmitted PWM signal to separate the DC component from the AC component of the PWM signal (see Fig. 11 and paragraph 0088, where Pagano describes that a lower pass filter 1102 provides a direct current (DC) component 1152 from the PWM signal received from the switch module 302).
Claims 3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1), as applied to claims 1 and 19, and further in view of GLOSSMANN et al. (US 2025/0187453 A1).
Consider claims 3 and 20:
Pagano in view of Choi discloses the invention of claims 1 and 19 above. Pagano does not specifically disclose: the AC detector is configured to determine whether the PWM signal includes a duty cycle other than 0% or 100%.
GLOSSMANN teaches: an AC detector is configured to determine whether PWM signal includes a duty cycle other than 0% or 100% (see paragraph 0071, where GLOSSMANN describes a PWM signal that may be variable, and the duty cycle is in the range of 10-96.5% in a AC charging).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the AC detector is configured to determine whether the PWM signal includes a duty cycle other than 0% or 100%, as taught by GLOSSMANN to modify the method of Pagano et al. in order to be easy to install, as discussed by GLOSSMANN (see paragraph 0002).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1) and GLOSSMANN et al. (US 2025/0187453 A1), as applied to claim 3 above, and further in view of Finfter (US 9,705,485 B1).
Consider claim 4:
Pagano in view of Choi and GLOSSMANN discloses the invention of claim 3 above. Pagano does not specifically disclose: output a signal representing a 0 if the duty cycle is either 0% or 100%; and output a signal representing a 1 if the duty cycle is something other than 0% or 100%.
Finfter teaches: output a signal representing a 0 if the duty cycle is either 0% or 100% (see col. 6, lines 7-12, where Finfter describes a binary value of “0” has a corresponding duty cycle is 0% in a PWM), and output a signal representing a 1 if the duty cycle is something other than 0% or 100% (see col. 6, lines 7-12, where Finfter describes a binary value of “1” has a corresponding duty cycle is 0.39% in a PWM).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: output a signal representing a 0 if the duty cycle is either 0% or 100%; and output a signal representing a 1 if the duty cycle is something other than 0% or 100%, as taught by Finfter to modify the method of Pagano et al. in order to have a controllable duty cycle, as discussed by Finfter (see col. 5, lines 62-67).
Claims 5, 7, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1), as applied to claims 1 and 11 above, and further in view of Yu et al. (US 2022/0278616 A1).
Consider claims 5 and 15:
Pagano in view of Choi discloses the invention of claims 1 and 11 above. Pagano does not specifically disclose: the DC detector is configured to distinguish between at least two PWM duty cycles based on a threshold duty cycle.
Yu teaches: a detector is configured to distinguish between at least two PWM duty cycles based on a threshold duty cycle (see paragraph 0072-0073, where Yu describes a detector which detects a duty cycle 90% and a duty cycle 70% based on a preset duty cycle threshold in a pulse width modulation).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the DC detector is configured to distinguish between at least two PWM duty cycles based on a threshold duty cycle, as taught by Yu to modify the method of Pagano et al. in order to detect over-shoot, as discussed by Yu (see paragraph 0073).
Consider claims 7 and 17:
Pagano in view of Choi discloses the invention of claims 1 and 11 above. Pagano does not specifically disclose: the DC detector is configured to distinguish between more than two PWM duty cycles based on multiple threshold duty cycles.
Yu teaches: a detector is configured to distinguish between more than two PWM duty cycles based on multiple threshold duty cycles (see paragraph 0072-0073, where Yu describes a detector which detects duty cycles based on a preset duty cycle threshold 70% and another preset duty cycle threshold 80% in a pulse width modulation).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the DC detector is configured to distinguish between more than two PWM duty cycles based on multiple threshold duty cycles, as taught by Yu to modify the method of Pagano et al. in order to detect over-shoot, as discussed by Yu (see paragraph 0073).
Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1), as applied to claims 1 and 11 above, and further in view of Averyt et al. (US 2021/0084726 A1).
Consider claims 10 and 18:
Pagano in view of Choi discloses the invention of claims 1 and 11 above. Pagano does not specifically disclose: a frequency detector configured to detect a frequency of the PWM signal.
Averyt teaches: a frequency detector configured to detect a frequency of a PWM signal (see Fig. 4 and paragraph 0039, where Averyt describes a frequency detector 420 which determines a frequency value of the PWM input).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a frequency detector configured to detect a frequency of the PWM signal, as taught by Averyt to modify the method of Pagano et al. in order to adjust output PWM signal, as discussed by Averyt (see paragraph 0039).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1), as applied to claim 11 above, and further in view of Zhou et al. (US 2022/0201817 A1).
Consider claim 13:
Pagano in view of Choi discloses the method of claim 11 above. Pagano does not specifically disclose: determining whether the PWM signal is modulated based on a threshold.
Zhou teaches: determining whether a PWM signal is modulated based on a threshold (see Fig. 7D and paragraph 0152, where Zhou describes that a determining circuit 241 is configured to detect whether a modulated signal Pin_C is in a range of threshold values in a PWM receiver).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: determining whether the PWM signal is modulated based on a threshold, as taught by Zhou to modify the method of Pagano et al. in order to judge the modulated signal for zero voltage, as discussed by Zhou (see paragraph 0152).
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1) and Yu et al. (US 2022/0278616 A1), as applied to claims 5 and 15 above, and further in view of Pearson et al. (US 2022/0099100 A1).
Consider claims 6 and 16:
Pagano in view of Choi discloses the invention of claims 5 and 15 above. Pagano does not specifically disclose: output a signal representing a 0 if an input signal to the DC detector is less than 50%, and output a signal representing a 1 if the input signal to the DC detector is greater than 50%.
Pearson teaches: output a signal representing a 0 if an input signal to the DC detector is less than 50% (see paragraph 0023, where Pearson describes that a duty cycle of 25% may be used to indicate a binary 0), and output a signal representing a 1 if the input signal to the DC detector is greater than 50% (see paragraph 0023, where Pearson describes that a duty cycle of 75% may be used to indicate a binary 1).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: output a signal representing a 0 if an input signal to the DC detector is less than 50%, and output a signal representing a 1 if the input signal to the DC detector is greater than 50%, as taught by Pearson to modify the method of Pagano et al. in order to optimize the system, as discussed by Pearson (see paragraph 0008).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Pagano (US 2011/0031934 A1) in view of Choi et al. (US 2022/0059155 A1) and Zhou et al. (US 2022/0201817 A1), as applied to claim 13 above, and further in view of Pearson et al. (US 2022/0099100 A1).
Consider claim 14:
Pagano in view of Choi discloses the invention of claim 13 above. Pagano does not specifically disclose: output a signal representing a 0 if an input signal to the DC detector is less than 50%, and output a signal representing a 1 if the input signal to the DC detector is greater than 50%.
Pearson teaches: output a signal representing a 0 if an input signal to the DC detector is less than 50% (see paragraph 0023, where Pearson describes that a duty cycle of 25% may be used to indicate a binary 0), and output a signal representing a 1 if the input signal to the DC detector is greater than 50% (see paragraph 0023, where Pearson describes that a duty cycle of 75% may be used to indicate a binary 1).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: output a signal representing a 0 if an input signal to the DC detector is less than 50%, and output a signal representing a 1 if the input signal to the DC detector is greater than 50%, as taught by Pearson to modify the method of Pagano et al. in order to optimize the system, as discussed by Pearson (see paragraph 0008).
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIHONG YU whose telephone number is (571)270-5147. The examiner can normally be reached 10:00 am-6:00 pm EST Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hannah S. Wang can be reached at (571)272-9018. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LIHONG YU/Primary Examiner, Art Unit 2631
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